1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _TI_DPLL_CLOCK_H_ 31 #define _TI_DPLL_CLOCK_H_ 32 33 #include <dev/clk/clk.h> 34 35 /* Registers are described in AM335x TRM chapter 8.1.12.2.* */ 36 37 /* Register offsets */ 38 #define CM_CLKSEL_DPLL_PERIPH 0x49C 39 40 /* CM_IDLEST_DPLL_xxx */ 41 #define ST_MN_BYPASS_MASK 0x0100 42 #define ST_MN_BYPASS_SHIFT 8 43 #define ST_DPLL_CLK_MASK 0x0001 44 45 /* CM_CLKMODE_DPLL_DPLL_EN feature flag */ 46 #define LOW_POWER_STOP_MODE_FLAG 0x01 47 #define MN_BYPASS_MODE_FLAG 0x02 48 #define IDLE_BYPASS_LOW_POWER_MODE_FLAG 0x04 49 #define IDLE_BYPASS_FAST_RELOCK_MODE_FLAG 0x08 50 #define LOCK_MODE_FLAG 0x10 51 52 /* CM_CLKMODE_DPLL_xxx */ 53 #define DPLL_EN_LOW_POWER_STOP_MODE 0x01 54 #define DPLL_EN_MN_BYPASS_MODE 0x04 55 #define DPLL_EN_IDLE_BYPASS_LOW_POWER_MODE 0x05 56 #define DPLL_EN_IDLE_BYPASS_FAST_RELOCK_MODE 0x06 57 #define DPLL_EN_LOCK_MODE 0x07 58 59 #define TI_CLK_FACTOR_ZERO_BASED 0x0002 60 #define TI_CLK_FACTOR_FIXED 0x0008 61 #define TI_CLK_FACTOR_MIN_VALUE 0x0020 62 #define TI_CLK_FACTOR_MAX_VALUE 0x0040 63 64 /* Based on aw_clk_factor sys/arm/allwinner/clkng/aw_clk.h */ 65 struct ti_clk_factor { 66 uint32_t shift; /* Shift bits for the factor */ 67 uint32_t mask; /* Mask to get the factor */ 68 uint32_t width; /* Number of bits for the factor */ 69 uint32_t value; /* Fixed value */ 70 71 uint32_t min_value; 72 uint32_t max_value; 73 74 uint32_t flags; /* Flags */ 75 }; 76 77 struct ti_clk_dpll_def { 78 struct clknode_init_def clkdef; 79 80 uint32_t ti_clkmode_offset; /* control */ 81 uint8_t ti_clkmode_flags; 82 83 uint32_t ti_idlest_offset; 84 85 uint32_t ti_clksel_offset; /* mult-div1 */ 86 struct ti_clk_factor ti_clksel_mult; 87 struct ti_clk_factor ti_clksel_div; 88 89 uint32_t ti_autoidle_offset; 90 }; 91 92 int ti_clknode_dpll_register(struct clkdom *clkdom, struct ti_clk_dpll_def *clkdef); 93 94 #endif /* _TI_DPLL_CLOCK_H_ */ 95