1 /*- 2 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * NXP TDA19988 HDMI encoder 30 */ 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/clock.h> 36 #include <sys/eventhandler.h> 37 #include <sys/time.h> 38 #include <sys/bus.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/types.h> 42 #include <sys/systm.h> 43 44 #include <dev/iicbus/iicbus.h> 45 #include <dev/iicbus/iiconf.h> 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/videomode/videomode.h> 52 #include <dev/videomode/edidvar.h> 53 54 #include "iicbus_if.h" 55 #include "crtc_if.h" 56 57 #define MKREG(page, addr) (((page) << 8) | (addr)) 58 59 #define REGPAGE(reg) (((reg) >> 8) & 0xff) 60 #define REGADDR(reg) ((reg) & 0xff) 61 62 #define TDA_VERSION MKREG(0x00, 0x00) 63 #define TDA_MAIN_CNTRL0 MKREG(0x00, 0x01) 64 #define MAIN_CNTRL0_SR (1 << 0) 65 #define TDA_VERSION_MSB MKREG(0x00, 0x02) 66 #define TDA_SOFTRESET MKREG(0x00, 0x0a) 67 #define SOFTRESET_I2C (1 << 1) 68 #define SOFTRESET_AUDIO (1 << 0) 69 #define TDA_DDC_CTRL MKREG(0x00, 0x0b) 70 #define DDC_ENABLE 0 71 #define TDA_CCLK MKREG(0x00, 0x0c) 72 #define CCLK_ENABLE 1 73 #define TDA_INT_FLAGS_2 MKREG(0x00, 0x11) 74 #define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 75 76 #define TDA_VIP_CNTRL_0 MKREG(0x00, 0x20) 77 #define TDA_VIP_CNTRL_1 MKREG(0x00, 0x21) 78 #define TDA_VIP_CNTRL_2 MKREG(0x00, 0x22) 79 #define TDA_VIP_CNTRL_3 MKREG(0x00, 0x23) 80 #define VIP_CNTRL_3_SYNC_HS (2 << 4) 81 #define VIP_CNTRL_3_V_TGL (1 << 2) 82 #define VIP_CNTRL_3_H_TGL (1 << 1) 83 84 #define TDA_VIP_CNTRL_4 MKREG(0x00, 0x24) 85 #define VIP_CNTRL_4_BLANKIT_NDE (0 << 2) 86 #define VIP_CNTRL_4_BLANKIT_HS_VS (1 << 2) 87 #define VIP_CNTRL_4_BLANKIT_NHS_VS (2 << 2) 88 #define VIP_CNTRL_4_BLANKIT_HE_VE (3 << 2) 89 #define VIP_CNTRL_4_BLC_NONE (0 << 0) 90 #define VIP_CNTRL_4_BLC_RGB444 (1 << 0) 91 #define VIP_CNTRL_4_BLC_YUV444 (2 << 0) 92 #define VIP_CNTRL_4_BLC_YUV422 (3 << 0) 93 #define TDA_VIP_CNTRL_5 MKREG(0x00, 0x25) 94 #define VIP_CNTRL_5_SP_CNT(n) (((n) & 3) << 1) 95 #define TDA_MUX_VP_VIP_OUT MKREG(0x00, 0x27) 96 #define TDA_MAT_CONTRL MKREG(0x00, 0x80) 97 #define MAT_CONTRL_MAT_BP (1 << 2) 98 #define TDA_VIDFORMAT MKREG(0x00, 0xa0) 99 #define TDA_REFPIX_MSB MKREG(0x00, 0xa1) 100 #define TDA_REFPIX_LSB MKREG(0x00, 0xa2) 101 #define TDA_REFLINE_MSB MKREG(0x00, 0xa3) 102 #define TDA_REFLINE_LSB MKREG(0x00, 0xa4) 103 #define TDA_NPIX_MSB MKREG(0x00, 0xa5) 104 #define TDA_NPIX_LSB MKREG(0x00, 0xa6) 105 #define TDA_NLINE_MSB MKREG(0x00, 0xa7) 106 #define TDA_NLINE_LSB MKREG(0x00, 0xa8) 107 #define TDA_VS_LINE_STRT_1_MSB MKREG(0x00, 0xa9) 108 #define TDA_VS_LINE_STRT_1_LSB MKREG(0x00, 0xaa) 109 #define TDA_VS_PIX_STRT_1_MSB MKREG(0x00, 0xab) 110 #define TDA_VS_PIX_STRT_1_LSB MKREG(0x00, 0xac) 111 #define TDA_VS_LINE_END_1_MSB MKREG(0x00, 0xad) 112 #define TDA_VS_LINE_END_1_LSB MKREG(0x00, 0xae) 113 #define TDA_VS_PIX_END_1_MSB MKREG(0x00, 0xaf) 114 #define TDA_VS_PIX_END_1_LSB MKREG(0x00, 0xb0) 115 #define TDA_VS_LINE_STRT_2_MSB MKREG(0x00, 0xb1) 116 #define TDA_VS_LINE_STRT_2_LSB MKREG(0x00, 0xb2) 117 #define TDA_VS_PIX_STRT_2_MSB MKREG(0x00, 0xb3) 118 #define TDA_VS_PIX_STRT_2_LSB MKREG(0x00, 0xb4) 119 #define TDA_VS_LINE_END_2_MSB MKREG(0x00, 0xb5) 120 #define TDA_VS_LINE_END_2_LSB MKREG(0x00, 0xb6) 121 #define TDA_VS_PIX_END_2_MSB MKREG(0x00, 0xb7) 122 #define TDA_VS_PIX_END_2_LSB MKREG(0x00, 0xb8) 123 #define TDA_HS_PIX_START_MSB MKREG(0x00, 0xb9) 124 #define TDA_HS_PIX_START_LSB MKREG(0x00, 0xba) 125 #define TDA_HS_PIX_STOP_MSB MKREG(0x00, 0xbb) 126 #define TDA_HS_PIX_STOP_LSB MKREG(0x00, 0xbc) 127 #define TDA_VWIN_START_1_MSB MKREG(0x00, 0xbd) 128 #define TDA_VWIN_START_1_LSB MKREG(0x00, 0xbe) 129 #define TDA_VWIN_END_1_MSB MKREG(0x00, 0xbf) 130 #define TDA_VWIN_END_1_LSB MKREG(0x00, 0xc0) 131 #define TDA_VWIN_START_2_MSB MKREG(0x00, 0xc1) 132 #define TDA_VWIN_START_2_LSB MKREG(0x00, 0xc2) 133 #define TDA_VWIN_END_2_MSB MKREG(0x00, 0xc3) 134 #define TDA_VWIN_END_2_LSB MKREG(0x00, 0xc4) 135 #define TDA_DE_START_MSB MKREG(0x00, 0xc5) 136 #define TDA_DE_START_LSB MKREG(0x00, 0xc6) 137 #define TDA_DE_STOP_MSB MKREG(0x00, 0xc7) 138 #define TDA_DE_STOP_LSB MKREG(0x00, 0xc8) 139 140 #define TDA_TBG_CNTRL_0 MKREG(0x00, 0xca) 141 #define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 142 #define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 143 144 #define TDA_TBG_CNTRL_1 MKREG(0x00, 0xcb) 145 #define TBG_CNTRL_1_DWIN_DIS (1 << 6) 146 #define TBG_CNTRL_1_TGL_EN (1 << 2) 147 #define TBG_CNTRL_1_V_TGL (1 << 1) 148 #define TBG_CNTRL_1_H_TGL (1 << 0) 149 150 #define TDA_HVF_CNTRL_0 MKREG(0x00, 0xe4) 151 #define HVF_CNTRL_0_PREFIL_NONE (0 << 2) 152 #define HVF_CNTRL_0_INTPOL_BYPASS (0 << 0) 153 #define TDA_HVF_CNTRL_1 MKREG(0x00, 0xe5) 154 #define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 155 #define HVF_CNTRL_1_VQR_FULL HVF_CNTRL_1_VQR(0) 156 #define TDA_ENABLE_SPACE MKREG(0x00, 0xd6) 157 #define TDA_RPT_CNTRL MKREG(0x00, 0xf0) 158 159 #define TDA_PLL_SERIAL_1 MKREG(0x02, 0x00) 160 #define PLL_SERIAL_1_SRL_MAN_IP (1 << 6) 161 #define TDA_PLL_SERIAL_2 MKREG(0x02, 0x01) 162 #define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 163 #define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0) 164 #define TDA_PLL_SERIAL_3 MKREG(0x02, 0x02) 165 #define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 166 #define PLL_SERIAL_3_SRL_DE (1 << 2) 167 #define PLL_SERIAL_3_SRL_CCIR (1 << 0) 168 #define TDA_SERIALIZER MKREG(0x02, 0x03) 169 #define TDA_BUFFER_OUT MKREG(0x02, 0x04) 170 #define TDA_PLL_SCG1 MKREG(0x02, 0x05) 171 #define TDA_PLL_SCG2 MKREG(0x02, 0x06) 172 #define TDA_PLL_SCGN1 MKREG(0x02, 0x07) 173 #define TDA_PLL_SCGN2 MKREG(0x02, 0x08) 174 #define TDA_PLL_SCGR1 MKREG(0x02, 0x09) 175 #define TDA_PLL_SCGR2 MKREG(0x02, 0x0a) 176 177 #define TDA_SEL_CLK MKREG(0x02, 0x11) 178 #define SEL_CLK_ENA_SC_CLK (1 << 3) 179 #define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 180 #define SEL_CLK_SEL_CLK1 (1 << 0) 181 #define TDA_ANA_GENERAL MKREG(0x02, 0x12) 182 183 #define TDA_EDID_DATA0 MKREG(0x09, 0x00) 184 #define TDA_EDID_CTRL MKREG(0x09, 0xfa) 185 #define TDA_DDC_ADDR MKREG(0x09, 0xfb) 186 #define TDA_DDC_OFFS MKREG(0x09, 0xfc) 187 #define TDA_DDC_SEGM_ADDR MKREG(0x09, 0xfd) 188 #define TDA_DDC_SEGM MKREG(0x09, 0xfe) 189 190 #define TDA_IF_VSP MKREG(0x10, 0x20) 191 #define TDA_IF_AVI MKREG(0x10, 0x40) 192 #define TDA_IF_SPD MKREG(0x10, 0x60) 193 #define TDA_IF_AUD MKREG(0x10, 0x80) 194 #define TDA_IF_MPS MKREG(0x10, 0xa0) 195 196 #define TDA_ENC_CNTRL MKREG(0x11, 0x0d) 197 #define ENC_CNTRL_DVI_MODE (0 << 2) 198 #define ENC_CNTRL_HDMI_MODE (1 << 2) 199 #define TDA_DIP_IF_FLAGS MKREG(0x11, 0x0f) 200 #define DIP_IF_FLAGS_IF5 (1 << 5) 201 #define DIP_IF_FLAGS_IF4 (1 << 4) 202 #define DIP_IF_FLAGS_IF3 (1 << 3) 203 #define DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */ 204 #define DIP_IF_FLAGS_IF1 (1 << 1) 205 206 #define TDA_TX3 MKREG(0x12, 0x9a) 207 #define TDA_TX4 MKREG(0x12, 0x9b) 208 #define TX4_PD_RAM (1 << 1) 209 #define TDA_HDCP_TX33 MKREG(0x12, 0xb8) 210 #define HDCP_TX33_HDMI (1 << 1) 211 212 #define TDA_CURPAGE_ADDR 0xff 213 214 #define TDA_CEC_ENAMODS 0xff 215 #define ENAMODS_RXSENS (1 << 2) 216 #define ENAMODS_HDMI (1 << 1) 217 #define TDA_CEC_FRO_IM_CLK_CTRL 0xfb 218 #define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 219 #define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 220 221 /* EDID reading */ 222 #define EDID_LENGTH 0x80 223 #define MAX_READ_ATTEMPTS 100 224 225 /* EDID fields */ 226 #define EDID_MODES0 35 227 #define EDID_MODES1 36 228 #define EDID_TIMING_START 38 229 #define EDID_TIMING_END 54 230 #define EDID_TIMING_X(v) (((v) + 31) * 8) 231 #define EDID_FREQ(v) (((v) & 0x3f) + 60) 232 #define EDID_RATIO(v) (((v) >> 6) & 0x3) 233 #define EDID_RATIO_10x16 0 234 #define EDID_RATIO_3x4 1 235 #define EDID_RATIO_4x5 2 236 #define EDID_RATIO_9x16 3 237 238 #define TDA19988 0x0301 239 240 struct tda19988_softc { 241 device_t sc_dev; 242 uint32_t sc_addr; 243 uint32_t sc_cec_addr; 244 uint16_t sc_version; 245 int sc_current_page; 246 uint8_t *sc_edid; 247 uint32_t sc_edid_len; 248 }; 249 250 static int 251 tda19988_set_page(struct tda19988_softc *sc, uint8_t page) 252 { 253 uint8_t addr = TDA_CURPAGE_ADDR; 254 uint8_t cmd[2]; 255 int result; 256 struct iic_msg msg[] = { 257 { sc->sc_addr, IIC_M_WR, 2, cmd }, 258 }; 259 260 cmd[0] = addr; 261 cmd[1] = page; 262 263 result = (iicbus_transfer(sc->sc_dev, msg, 1)); 264 if (result) 265 printf("tda19988_set_page failed: %d\n", result); 266 else 267 sc->sc_current_page = page; 268 269 return (result); 270 } 271 272 static int 273 tda19988_cec_read(struct tda19988_softc *sc, uint8_t addr, uint8_t *data) 274 { 275 int result; 276 struct iic_msg msg[] = { 277 { sc->sc_cec_addr, IIC_M_WR, 1, &addr }, 278 { sc->sc_cec_addr, IIC_M_RD, 1, data }, 279 }; 280 281 result = iicbus_transfer(sc->sc_dev, msg, 2); 282 if (result) 283 printf("tda19988_cec_read failed: %d\n", result); 284 return (result); 285 } 286 287 static int 288 tda19988_cec_write(struct tda19988_softc *sc, uint8_t address, uint8_t data) 289 { 290 uint8_t cmd[2]; 291 int result; 292 struct iic_msg msg[] = { 293 { sc->sc_cec_addr, IIC_M_WR, 2, cmd }, 294 }; 295 296 cmd[0] = address; 297 cmd[1] = data; 298 299 result = iicbus_transfer(sc->sc_dev, msg, 1); 300 if (result) 301 printf("tda19988_cec_write failed: %d\n", result); 302 return (result); 303 } 304 305 static int 306 tda19988_block_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data, int len) 307 { 308 uint8_t reg; 309 int result; 310 struct iic_msg msg[] = { 311 { sc->sc_addr, IIC_M_WR, 1, ® }, 312 { sc->sc_addr, IIC_M_RD, len, data }, 313 }; 314 315 reg = REGADDR(addr); 316 317 if (sc->sc_current_page != REGPAGE(addr)) 318 tda19988_set_page(sc, REGPAGE(addr)); 319 320 result = (iicbus_transfer(sc->sc_dev, msg, 2)); 321 if (result) 322 device_printf(sc->sc_dev, "tda19988_block_read failed: %d\n", result); 323 return (result); 324 } 325 326 static int 327 tda19988_reg_read(struct tda19988_softc *sc, uint16_t addr, uint8_t *data) 328 { 329 uint8_t reg; 330 int result; 331 struct iic_msg msg[] = { 332 { sc->sc_addr, IIC_M_WR, 1, ® }, 333 { sc->sc_addr, IIC_M_RD, 1, data }, 334 }; 335 336 reg = REGADDR(addr); 337 338 if (sc->sc_current_page != REGPAGE(addr)) 339 tda19988_set_page(sc, REGPAGE(addr)); 340 341 result = (iicbus_transfer(sc->sc_dev, msg, 2)); 342 if (result) 343 device_printf(sc->sc_dev, "tda19988_reg_read failed: %d\n", result); 344 return (result); 345 } 346 347 static int 348 tda19988_reg_write(struct tda19988_softc *sc, uint16_t address, uint8_t data) 349 { 350 uint8_t cmd[2]; 351 int result; 352 struct iic_msg msg[] = { 353 { sc->sc_addr, IIC_M_WR, 2, cmd }, 354 }; 355 356 cmd[0] = REGADDR(address); 357 cmd[1] = data; 358 359 if (sc->sc_current_page != REGPAGE(address)) 360 tda19988_set_page(sc, REGPAGE(address)); 361 362 result = iicbus_transfer(sc->sc_dev, msg, 1); 363 if (result) 364 device_printf(sc->sc_dev, "tda19988_reg_write failed: %d\n", result); 365 366 return (result); 367 } 368 369 static int 370 tda19988_reg_write2(struct tda19988_softc *sc, uint16_t address, uint16_t data) 371 { 372 uint8_t cmd[3]; 373 int result; 374 struct iic_msg msg[] = { 375 { sc->sc_addr, IIC_M_WR, 3, cmd }, 376 }; 377 378 cmd[0] = REGADDR(address); 379 cmd[1] = (data >> 8); 380 cmd[2] = (data & 0xff); 381 382 if (sc->sc_current_page != REGPAGE(address)) 383 tda19988_set_page(sc, REGPAGE(address)); 384 385 result = iicbus_transfer(sc->sc_dev, msg, 1); 386 if (result) 387 device_printf(sc->sc_dev, "tda19988_reg_write2 failed: %d\n", result); 388 389 return (result); 390 } 391 392 static void 393 tda19988_reg_set(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 394 { 395 uint8_t data; 396 397 tda19988_reg_read(sc, addr, &data); 398 data |= flags; 399 tda19988_reg_write(sc, addr, data); 400 } 401 402 static void 403 tda19988_reg_clear(struct tda19988_softc *sc, uint16_t addr, uint8_t flags) 404 { 405 uint8_t data; 406 407 tda19988_reg_read(sc, addr, &data); 408 data &= ~flags; 409 tda19988_reg_write(sc, addr, data); 410 } 411 412 static int 413 tda19988_probe(device_t dev) 414 { 415 416 if (!ofw_bus_is_compatible(dev, "nxp,tda998x")) 417 return (ENXIO); 418 419 return (BUS_PROBE_DEFAULT); 420 } 421 422 static void 423 tda19988_init_encoder(struct tda19988_softc *sc, const struct videomode *mode) 424 { 425 uint16_t ref_pix, ref_line, n_pix, n_line; 426 uint16_t hs_pix_start, hs_pix_stop; 427 uint16_t vs1_pix_start, vs1_pix_stop; 428 uint16_t vs1_line_start, vs1_line_end; 429 uint16_t vs2_pix_start, vs2_pix_stop; 430 uint16_t vs2_line_start, vs2_line_end; 431 uint16_t vwin1_line_start, vwin1_line_end; 432 uint16_t vwin2_line_start, vwin2_line_end; 433 uint16_t de_start, de_stop; 434 uint8_t reg, div; 435 436 n_pix = mode->htotal; 437 n_line = mode->vtotal; 438 439 hs_pix_stop = mode->hsync_end - mode->hdisplay; 440 hs_pix_start = mode->hsync_start - mode->hdisplay; 441 442 de_stop = mode->htotal; 443 de_start = mode->htotal - mode->hdisplay; 444 ref_pix = hs_pix_start + 3; 445 446 if (mode->flags & VID_HSKEW) 447 ref_pix += mode->hskew; 448 449 if ((mode->flags & VID_INTERLACE) == 0) { 450 ref_line = 1 + mode->vsync_start - mode->vdisplay; 451 vwin1_line_start = mode->vtotal - mode->vdisplay - 1; 452 vwin1_line_end = vwin1_line_start + mode->vdisplay; 453 454 vs1_pix_start = vs1_pix_stop = hs_pix_start; 455 vs1_line_start = mode->vsync_start - mode->vdisplay; 456 vs1_line_end = vs1_line_start + mode->vsync_end - mode->vsync_start; 457 458 vwin2_line_start = vwin2_line_end = 0; 459 vs2_pix_start = vs2_pix_stop = 0; 460 vs2_line_start = vs2_line_end = 0; 461 } else { 462 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 463 vwin1_line_start = (mode->vtotal - mode->vdisplay)/2; 464 vwin1_line_end = vwin1_line_start + mode->vdisplay/2; 465 466 vs1_pix_start = vs1_pix_stop = hs_pix_start; 467 vs1_line_start = (mode->vsync_start - mode->vdisplay)/2; 468 vs1_line_end = vs1_line_start + (mode->vsync_end - mode->vsync_start)/2; 469 470 vwin2_line_start = vwin1_line_start + mode->vtotal/2; 471 vwin2_line_end = vwin2_line_start + mode->vdisplay/2; 472 473 vs2_pix_start = vs2_pix_stop = hs_pix_start + mode->htotal/2; 474 vs2_line_start = vs1_line_start + mode->vtotal/2 ; 475 vs2_line_end = vs2_line_start + (mode->vsync_end - mode->vsync_start)/2; 476 } 477 478 div = 148500 / mode->dot_clock; 479 if (div != 0) { 480 div--; 481 if (div > 3) 482 div = 3; 483 } 484 485 /* set HDMI HDCP mode off */ 486 tda19988_reg_set(sc, TDA_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 487 tda19988_reg_clear(sc, TDA_HDCP_TX33, HDCP_TX33_HDMI); 488 tda19988_reg_write(sc, TDA_ENC_CNTRL, ENC_CNTRL_DVI_MODE); 489 490 /* no pre-filter or interpolator */ 491 tda19988_reg_write(sc, TDA_HVF_CNTRL_0, 492 HVF_CNTRL_0_INTPOL_BYPASS | HVF_CNTRL_0_PREFIL_NONE); 493 tda19988_reg_write(sc, TDA_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 494 tda19988_reg_write(sc, TDA_VIP_CNTRL_4, 495 VIP_CNTRL_4_BLANKIT_NDE | VIP_CNTRL_4_BLC_NONE); 496 497 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 498 tda19988_reg_clear(sc, TDA_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IP); 499 tda19988_reg_clear(sc, TDA_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 500 tda19988_reg_write(sc, TDA_SERIALIZER, 0); 501 tda19988_reg_write(sc, TDA_HVF_CNTRL_1, HVF_CNTRL_1_VQR_FULL); 502 503 tda19988_reg_write(sc, TDA_RPT_CNTRL, 0); 504 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 505 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 506 507 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 508 PLL_SERIAL_2_SRL_PR(0)); 509 510 tda19988_reg_set(sc, TDA_MAT_CONTRL, MAT_CONTRL_MAT_BP); 511 512 tda19988_reg_write(sc, TDA_ANA_GENERAL, 0x09); 513 514 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 515 516 /* 517 * Sync on rising HSYNC/VSYNC 518 */ 519 reg = VIP_CNTRL_3_SYNC_HS; 520 if (mode->flags & VID_NHSYNC) 521 reg |= VIP_CNTRL_3_H_TGL; 522 if (mode->flags & VID_NVSYNC) 523 reg |= VIP_CNTRL_3_V_TGL; 524 tda19988_reg_write(sc, TDA_VIP_CNTRL_3, reg); 525 526 reg = TBG_CNTRL_1_TGL_EN; 527 if (mode->flags & VID_NHSYNC) 528 reg |= TBG_CNTRL_1_H_TGL; 529 if (mode->flags & VID_NVSYNC) 530 reg |= TBG_CNTRL_1_V_TGL; 531 tda19988_reg_write(sc, TDA_TBG_CNTRL_1, reg); 532 533 /* Program timing */ 534 tda19988_reg_write(sc, TDA_VIDFORMAT, 0x00); 535 536 tda19988_reg_write2(sc, TDA_REFPIX_MSB, ref_pix); 537 tda19988_reg_write2(sc, TDA_REFLINE_MSB, ref_line); 538 tda19988_reg_write2(sc, TDA_NPIX_MSB, n_pix); 539 tda19988_reg_write2(sc, TDA_NLINE_MSB, n_line); 540 541 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_1_MSB, vs1_line_start); 542 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_1_MSB, vs1_pix_start); 543 tda19988_reg_write2(sc, TDA_VS_LINE_END_1_MSB, vs1_line_end); 544 tda19988_reg_write2(sc, TDA_VS_PIX_END_1_MSB, vs1_pix_stop); 545 tda19988_reg_write2(sc, TDA_VS_LINE_STRT_2_MSB, vs2_line_start); 546 tda19988_reg_write2(sc, TDA_VS_PIX_STRT_2_MSB, vs2_pix_start); 547 tda19988_reg_write2(sc, TDA_VS_LINE_END_2_MSB, vs2_line_end); 548 tda19988_reg_write2(sc, TDA_VS_PIX_END_2_MSB, vs2_pix_stop); 549 tda19988_reg_write2(sc, TDA_HS_PIX_START_MSB, hs_pix_start); 550 tda19988_reg_write2(sc, TDA_HS_PIX_STOP_MSB, hs_pix_stop); 551 tda19988_reg_write2(sc, TDA_VWIN_START_1_MSB, vwin1_line_start); 552 tda19988_reg_write2(sc, TDA_VWIN_END_1_MSB, vwin1_line_end); 553 tda19988_reg_write2(sc, TDA_VWIN_START_2_MSB, vwin2_line_start); 554 tda19988_reg_write2(sc, TDA_VWIN_END_2_MSB, vwin2_line_end); 555 tda19988_reg_write2(sc, TDA_DE_START_MSB, de_start); 556 tda19988_reg_write2(sc, TDA_DE_STOP_MSB, de_stop); 557 558 if (sc->sc_version == TDA19988) 559 tda19988_reg_write(sc, TDA_ENABLE_SPACE, 0x00); 560 561 /* must be last register set */ 562 tda19988_reg_clear(sc, TDA_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 563 } 564 565 static int 566 tda19988_read_edid_block(struct tda19988_softc *sc, uint8_t *buf, int block) 567 { 568 int attempt, err; 569 uint8_t data; 570 571 err = 0; 572 573 tda19988_reg_set(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 574 575 /* Block 0 */ 576 tda19988_reg_write(sc, TDA_DDC_ADDR, 0xa0); 577 tda19988_reg_write(sc, TDA_DDC_OFFS, (block % 2) ? 128 : 0); 578 tda19988_reg_write(sc, TDA_DDC_SEGM_ADDR, 0x60); 579 tda19988_reg_write(sc, TDA_DDC_SEGM, block / 2); 580 581 tda19988_reg_write(sc, TDA_EDID_CTRL, 1); 582 tda19988_reg_write(sc, TDA_EDID_CTRL, 0); 583 584 data = 0; 585 for (attempt = 0; attempt < MAX_READ_ATTEMPTS; attempt++) { 586 tda19988_reg_read(sc, TDA_INT_FLAGS_2, &data); 587 if (data & INT_FLAGS_2_EDID_BLK_RD) 588 break; 589 pause("EDID", 1); 590 } 591 592 if (attempt == MAX_READ_ATTEMPTS) { 593 err = -1; 594 goto done; 595 } 596 597 if (tda19988_block_read(sc, TDA_EDID_DATA0, buf, EDID_LENGTH) != 0) { 598 err = -1; 599 goto done; 600 } 601 602 done: 603 tda19988_reg_clear(sc, TDA_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 604 605 return (err); 606 } 607 608 static int 609 tda19988_read_edid(struct tda19988_softc *sc) 610 { 611 int err; 612 int blocks, i; 613 uint8_t *buf; 614 615 err = 0; 616 if (sc->sc_version == TDA19988) 617 tda19988_reg_clear(sc, TDA_TX4, TX4_PD_RAM); 618 619 err = tda19988_read_edid_block(sc, sc->sc_edid, 0); 620 if (err) 621 goto done; 622 623 blocks = sc->sc_edid[0x7e]; 624 if (blocks > 0) { 625 sc->sc_edid = realloc(sc->sc_edid, 626 EDID_LENGTH*(blocks+1), M_DEVBUF, M_WAITOK); 627 sc->sc_edid_len = EDID_LENGTH*(blocks+1); 628 for (i = 0; i < blocks; i++) { 629 /* TODO: check validity */ 630 buf = sc->sc_edid + EDID_LENGTH*(i+1); 631 err = tda19988_read_edid_block(sc, buf, i); 632 if (err) 633 goto done; 634 } 635 } 636 637 EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev, HDMI_EVENT_CONNECTED); 638 done: 639 if (sc->sc_version == TDA19988) 640 tda19988_reg_set(sc, TDA_TX4, TX4_PD_RAM); 641 642 return (err); 643 } 644 645 static void 646 tda19988_start(struct tda19988_softc *sc) 647 { 648 device_t dev; 649 uint8_t data; 650 uint16_t version; 651 652 dev = sc->sc_dev; 653 654 tda19988_cec_write(sc, TDA_CEC_ENAMODS, ENAMODS_RXSENS | ENAMODS_HDMI); 655 DELAY(1000); 656 tda19988_cec_read(sc, 0xfe, &data); 657 658 /* Reset core */ 659 tda19988_reg_set(sc, TDA_SOFTRESET, 3); 660 DELAY(100); 661 tda19988_reg_clear(sc, TDA_SOFTRESET, 3); 662 DELAY(100); 663 664 /* reset transmitter: */ 665 tda19988_reg_set(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 666 tda19988_reg_clear(sc, TDA_MAIN_CNTRL0, MAIN_CNTRL0_SR); 667 668 /* PLL registers common configuration */ 669 tda19988_reg_write(sc, TDA_PLL_SERIAL_1, 0x00); 670 tda19988_reg_write(sc, TDA_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 671 tda19988_reg_write(sc, TDA_PLL_SERIAL_3, 0x00); 672 tda19988_reg_write(sc, TDA_SERIALIZER, 0x00); 673 tda19988_reg_write(sc, TDA_BUFFER_OUT, 0x00); 674 tda19988_reg_write(sc, TDA_PLL_SCG1, 0x00); 675 tda19988_reg_write(sc, TDA_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 676 tda19988_reg_write(sc, TDA_PLL_SCGN1, 0xfa); 677 tda19988_reg_write(sc, TDA_PLL_SCGN2, 0x00); 678 tda19988_reg_write(sc, TDA_PLL_SCGR1, 0x5b); 679 tda19988_reg_write(sc, TDA_PLL_SCGR2, 0x00); 680 tda19988_reg_write(sc, TDA_PLL_SCG2, 0x10); 681 682 /* Write the default value MUX register */ 683 tda19988_reg_write(sc, TDA_MUX_VP_VIP_OUT, 0x24); 684 685 version = 0; 686 tda19988_reg_read(sc, TDA_VERSION, &data); 687 version |= data; 688 tda19988_reg_read(sc, TDA_VERSION_MSB, &data); 689 version |= (data << 8); 690 691 /* Clear feature bits */ 692 sc->sc_version = version & ~0x30; 693 switch (sc->sc_version) { 694 case TDA19988: 695 device_printf(dev, "TDA19988\n"); 696 break; 697 default: 698 device_printf(dev, "Unknown device: %04x\n", sc->sc_version); 699 return; 700 } 701 702 tda19988_reg_write(sc, TDA_DDC_CTRL, DDC_ENABLE); 703 tda19988_reg_write(sc, TDA_TX3, 39); 704 705 tda19988_cec_write(sc, TDA_CEC_FRO_IM_CLK_CTRL, 706 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 707 708 if (tda19988_read_edid(sc) < 0) { 709 device_printf(dev, "failed to read EDID\n"); 710 return; 711 } 712 713 /* Default values for RGB 4:4:4 mapping */ 714 tda19988_reg_write(sc, TDA_VIP_CNTRL_0, 0x23); 715 tda19988_reg_write(sc, TDA_VIP_CNTRL_1, 0x01); 716 tda19988_reg_write(sc, TDA_VIP_CNTRL_2, 0x45); 717 } 718 719 static int 720 tda19988_attach(device_t dev) 721 { 722 struct tda19988_softc *sc; 723 phandle_t node; 724 725 sc = device_get_softc(dev); 726 727 sc->sc_dev = dev; 728 sc->sc_addr = iicbus_get_addr(dev); 729 sc->sc_cec_addr = (0x34 << 1); /* hardcoded */ 730 sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO); 731 sc->sc_edid_len = EDID_LENGTH; 732 733 device_set_desc(dev, "NXP TDA19988 HDMI transmitter"); 734 735 node = ofw_bus_get_node(dev); 736 OF_device_register_xref(OF_xref_from_node(node), dev); 737 738 tda19988_start(sc); 739 740 return (0); 741 } 742 743 static int 744 tda19988_detach(device_t dev) 745 { 746 747 /* XXX: Do not let unload drive */ 748 return (EBUSY); 749 } 750 751 static int 752 tda19988_get_edid(device_t dev, uint8_t **edid, uint32_t *edid_len) 753 { 754 struct tda19988_softc *sc; 755 756 sc = device_get_softc(dev); 757 758 if (sc->sc_edid) { 759 *edid = sc->sc_edid; 760 *edid_len = sc->sc_edid_len; 761 } else 762 return (ENXIO); 763 764 return (0); 765 } 766 767 static int 768 tda19988_set_videomode(device_t dev, const struct videomode *mode) 769 { 770 struct tda19988_softc *sc; 771 772 sc = device_get_softc(dev); 773 774 tda19988_init_encoder(sc, mode); 775 776 return (0); 777 } 778 779 static device_method_t tda_methods[] = { 780 DEVMETHOD(device_probe, tda19988_probe), 781 DEVMETHOD(device_attach, tda19988_attach), 782 DEVMETHOD(device_detach, tda19988_detach), 783 784 /* CRTC methods */ 785 DEVMETHOD(crtc_get_edid, tda19988_get_edid), 786 DEVMETHOD(crtc_set_videomode, tda19988_set_videomode), 787 {0, 0}, 788 }; 789 790 static driver_t tda_driver = { 791 "tda", 792 tda_methods, 793 sizeof(struct tda19988_softc), 794 }; 795 796 DRIVER_MODULE(tda, iicbus, tda_driver, 0, 0); 797 MODULE_VERSION(tda, 1); 798 MODULE_DEPEND(tda, iicbus, 1, 1, 1); 799