1 /*- 2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/stdint.h> 30 #include <sys/stddef.h> 31 #include <sys/param.h> 32 #include <sys/queue.h> 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 #include <sys/sysctl.h> 42 #include <sys/sx.h> 43 #include <sys/unistd.h> 44 #include <sys/callout.h> 45 #include <sys/malloc.h> 46 #include <sys/priv.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 55 #include <dev/usb/usb_core.h> 56 #include <dev/usb/usb_busdma.h> 57 #include <dev/usb/usb_process.h> 58 #include <dev/usb/usb_util.h> 59 60 #define USB_DEBUG_VAR usbssdebug 61 62 #include <dev/usb/usb_controller.h> 63 #include <dev/usb/usb_bus.h> 64 #include <dev/usb/controller/musb_otg.h> 65 #include <dev/usb/usb_debug.h> 66 67 #include <sys/rman.h> 68 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_scm.h> 71 #include <arm/ti/am335x/am335x_scm.h> 72 73 #define USBCTRL_REV 0x00 74 #define USBCTRL_CTRL 0x14 75 #define USBCTRL_STAT 0x18 76 #define USBCTRL_IRQ_STAT0 0x30 77 #define IRQ_STAT0_RXSHIFT 16 78 #define IRQ_STAT0_TXSHIFT 0 79 #define USBCTRL_IRQ_STAT1 0x34 80 #define IRQ_STAT1_DRVVBUS (1 << 8) 81 #define USBCTRL_INTEN_SET0 0x38 82 #define USBCTRL_INTEN_SET1 0x3C 83 #define USBCTRL_INTEN_USB_ALL 0x1ff 84 #define USBCTRL_INTEN_USB_SOF (1 << 3) 85 #define USBCTRL_INTEN_CLR0 0x40 86 #define USBCTRL_INTEN_CLR1 0x44 87 #define USBCTRL_UTMI 0xE0 88 #define USBCTRL_UTMI_FSDATAEXT (1 << 1) 89 #define USBCTRL_MODE 0xE8 90 #define USBCTRL_MODE_IDDIG (1 << 8) 91 #define USBCTRL_MODE_IDDIGMUX (1 << 7) 92 93 /* USBSS resource + 2 MUSB ports */ 94 95 #define RES_USBCORE 0 96 #define RES_USBCTRL 1 97 98 #define USB_WRITE4(sc, idx, reg, val) do { \ 99 bus_write_4((sc)->sc_mem_res[idx], (reg), (val)); \ 100 } while (0) 101 102 #define USB_READ4(sc, idx, reg) bus_read_4((sc)->sc_mem_res[idx], (reg)) 103 104 #define USBCTRL_WRITE4(sc, reg, val) \ 105 USB_WRITE4((sc), RES_USBCTRL, (reg), (val)) 106 #define USBCTRL_READ4(sc, reg) \ 107 USB_READ4((sc), RES_USBCTRL, (reg)) 108 109 static struct resource_spec am335x_musbotg_mem_spec[] = { 110 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 111 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 112 { -1, 0, 0 } 113 }; 114 115 #ifdef USB_DEBUG 116 static int usbssdebug = 0; 117 118 static SYSCTL_NODE(_hw_usb, OID_AUTO, am335x_usbss, CTLFLAG_RW, 0, "AM335x USBSS"); 119 SYSCTL_INT(_hw_usb_am335x_usbss, OID_AUTO, debug, CTLFLAG_RW, 120 &usbssdebug, 0, "Debug level"); 121 #endif 122 123 static device_probe_t musbotg_probe; 124 static device_attach_t musbotg_attach; 125 static device_detach_t musbotg_detach; 126 127 struct musbotg_super_softc { 128 struct musbotg_softc sc_otg; 129 struct resource *sc_mem_res[2]; 130 int sc_irq_rid; 131 }; 132 133 static void 134 musbotg_vbus_poll(struct musbotg_super_softc *sc) 135 { 136 uint32_t stat; 137 138 if (sc->sc_otg.sc_mode == MUSB2_DEVICE_MODE) 139 musbotg_vbus_interrupt(&sc->sc_otg, 1); 140 else { 141 stat = USBCTRL_READ4(sc, USBCTRL_STAT); 142 musbotg_vbus_interrupt(&sc->sc_otg, stat & 1); 143 } 144 } 145 146 /* 147 * Arg to musbotg_clocks_on and musbot_clocks_off is 148 * a uint32_t * pointing to the SCM register offset. 149 */ 150 static uint32_t USB_CTRL[] = {SCM_USB_CTRL0, SCM_USB_CTRL1}; 151 152 static void 153 musbotg_clocks_on(void *arg) 154 { 155 struct musbotg_softc *sc; 156 uint32_t c, reg; 157 158 sc = arg; 159 reg = USB_CTRL[sc->sc_id]; 160 161 ti_scm_reg_read_4(reg, &c); 162 c &= ~3; /* Enable power */ 163 c |= 1 << 19; /* VBUS detect enable */ 164 c |= 1 << 20; /* Session end enable */ 165 ti_scm_reg_write_4(reg, c); 166 } 167 168 static void 169 musbotg_clocks_off(void *arg) 170 { 171 struct musbotg_softc *sc; 172 uint32_t c, reg; 173 174 sc = arg; 175 reg = USB_CTRL[sc->sc_id]; 176 177 /* Disable power to PHY */ 178 ti_scm_reg_read_4(reg, &c); 179 ti_scm_reg_write_4(reg, c | 3); 180 } 181 182 static void 183 musbotg_ep_int_set(struct musbotg_softc *sc, int ep, int on) 184 { 185 struct musbotg_super_softc *ssc = sc->sc_platform_data; 186 uint32_t epmask; 187 188 epmask = ((1 << ep) << IRQ_STAT0_RXSHIFT); 189 epmask |= ((1 << ep) << IRQ_STAT0_TXSHIFT); 190 if (on) 191 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_SET0, epmask); 192 else 193 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_CLR0, epmask); 194 } 195 196 static void 197 musbotg_wrapper_interrupt(void *arg) 198 { 199 struct musbotg_softc *sc = arg; 200 struct musbotg_super_softc *ssc = sc->sc_platform_data; 201 uint32_t stat, stat0, stat1; 202 203 stat = USBCTRL_READ4(ssc, USBCTRL_STAT); 204 stat0 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT0); 205 stat1 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT1); 206 if (stat0) 207 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT0, stat0); 208 if (stat1) 209 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT1, stat1); 210 211 DPRINTFN(4, "port%d: stat0=%08x stat1=%08x, stat=%08x\n", 212 sc->sc_id, stat0, stat1, stat); 213 214 if (stat1 & IRQ_STAT1_DRVVBUS) 215 musbotg_vbus_interrupt(sc, stat & 1); 216 217 musbotg_interrupt(arg, ((stat0 >> 16) & 0xffff), 218 stat0 & 0xffff, stat1 & 0xff); 219 } 220 221 static int 222 musbotg_probe(device_t dev) 223 { 224 if (!ofw_bus_status_okay(dev)) 225 return (ENXIO); 226 227 if (!ofw_bus_is_compatible(dev, "ti,musb-am33xx")) 228 return (ENXIO); 229 230 device_set_desc(dev, "TI AM33xx integrated USB OTG controller"); 231 232 return (BUS_PROBE_DEFAULT); 233 } 234 235 static int 236 musbotg_attach(device_t dev) 237 { 238 struct musbotg_super_softc *sc = device_get_softc(dev); 239 char mode[16]; 240 int err; 241 uint32_t reg; 242 243 sc->sc_otg.sc_id = device_get_unit(dev); 244 245 /* Request the memory resources */ 246 err = bus_alloc_resources(dev, am335x_musbotg_mem_spec, 247 sc->sc_mem_res); 248 if (err) { 249 device_printf(dev, 250 "Error: could not allocate mem resources\n"); 251 return (ENXIO); 252 } 253 254 /* Request the IRQ resources */ 255 sc->sc_otg.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 256 &sc->sc_irq_rid, RF_ACTIVE); 257 if (sc->sc_otg.sc_irq_res == NULL) { 258 device_printf(dev, 259 "Error: could not allocate irq resources\n"); 260 return (ENXIO); 261 } 262 263 /* setup MUSB OTG USB controller interface softc */ 264 sc->sc_otg.sc_clocks_on = &musbotg_clocks_on; 265 sc->sc_otg.sc_clocks_off = &musbotg_clocks_off; 266 sc->sc_otg.sc_clocks_arg = &sc->sc_otg; 267 268 sc->sc_otg.sc_ep_int_set = musbotg_ep_int_set; 269 270 /* initialise some bus fields */ 271 sc->sc_otg.sc_bus.parent = dev; 272 sc->sc_otg.sc_bus.devices = sc->sc_otg.sc_devices; 273 sc->sc_otg.sc_bus.devices_max = MUSB2_MAX_DEVICES; 274 sc->sc_otg.sc_bus.dma_bits = 32; 275 276 /* get all DMA memory */ 277 if (usb_bus_mem_alloc_all(&sc->sc_otg.sc_bus, 278 USB_GET_DMA_TAG(dev), NULL)) { 279 device_printf(dev, 280 "Failed allocate bus mem for musb\n"); 281 return (ENOMEM); 282 } 283 sc->sc_otg.sc_io_res = sc->sc_mem_res[RES_USBCORE]; 284 sc->sc_otg.sc_io_tag = 285 rman_get_bustag(sc->sc_otg.sc_io_res); 286 sc->sc_otg.sc_io_hdl = 287 rman_get_bushandle(sc->sc_otg.sc_io_res); 288 sc->sc_otg.sc_io_size = 289 rman_get_size(sc->sc_otg.sc_io_res); 290 291 sc->sc_otg.sc_bus.bdev = device_add_child(dev, "usbus", -1); 292 if (!(sc->sc_otg.sc_bus.bdev)) { 293 device_printf(dev, "No busdev for musb\n"); 294 goto error; 295 } 296 device_set_ivars(sc->sc_otg.sc_bus.bdev, 297 &sc->sc_otg.sc_bus); 298 299 err = bus_setup_intr(dev, sc->sc_otg.sc_irq_res, 300 INTR_TYPE_BIO | INTR_MPSAFE, 301 NULL, (driver_intr_t *)musbotg_wrapper_interrupt, 302 &sc->sc_otg, &sc->sc_otg.sc_intr_hdl); 303 if (err) { 304 sc->sc_otg.sc_intr_hdl = NULL; 305 device_printf(dev, 306 "Failed to setup interrupt for musb\n"); 307 goto error; 308 } 309 310 sc->sc_otg.sc_platform_data = sc; 311 if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", mode, 312 sizeof(mode)) > 0) { 313 if (strcasecmp(mode, "host") == 0) 314 sc->sc_otg.sc_mode = MUSB2_HOST_MODE; 315 else 316 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE; 317 } else { 318 /* Beaglebone defaults: USB0 device, USB1 HOST. */ 319 if (sc->sc_otg.sc_id == 0) 320 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE; 321 else 322 sc->sc_otg.sc_mode = MUSB2_HOST_MODE; 323 } 324 325 /* 326 * software-controlled function 327 */ 328 329 if (sc->sc_otg.sc_mode == MUSB2_HOST_MODE) { 330 reg = USBCTRL_READ4(sc, USBCTRL_MODE); 331 reg |= USBCTRL_MODE_IDDIGMUX; 332 reg &= ~USBCTRL_MODE_IDDIG; 333 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg); 334 USBCTRL_WRITE4(sc, USBCTRL_UTMI, 335 USBCTRL_UTMI_FSDATAEXT); 336 } else { 337 reg = USBCTRL_READ4(sc, USBCTRL_MODE); 338 reg |= USBCTRL_MODE_IDDIGMUX; 339 reg |= USBCTRL_MODE_IDDIG; 340 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg); 341 } 342 343 reg = USBCTRL_INTEN_USB_ALL & ~USBCTRL_INTEN_USB_SOF; 344 USBCTRL_WRITE4(sc, USBCTRL_INTEN_SET1, reg); 345 USBCTRL_WRITE4(sc, USBCTRL_INTEN_CLR0, 0xffffffff); 346 347 err = musbotg_init(&sc->sc_otg); 348 if (!err) 349 err = device_probe_and_attach(sc->sc_otg.sc_bus.bdev); 350 351 if (err) 352 goto error; 353 354 /* poll VBUS one time */ 355 musbotg_vbus_poll(sc); 356 357 return (0); 358 359 error: 360 musbotg_detach(dev); 361 return (ENXIO); 362 } 363 364 static int 365 musbotg_detach(device_t dev) 366 { 367 struct musbotg_super_softc *sc = device_get_softc(dev); 368 int err; 369 370 /* during module unload there are lots of children leftover */ 371 device_delete_children(dev); 372 373 if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) { 374 /* 375 * only call musbotg_uninit() after musbotg_init() 376 */ 377 musbotg_uninit(&sc->sc_otg); 378 379 err = bus_teardown_intr(dev, sc->sc_otg.sc_irq_res, 380 sc->sc_otg.sc_intr_hdl); 381 sc->sc_otg.sc_intr_hdl = NULL; 382 } 383 384 usb_bus_mem_free_all(&sc->sc_otg.sc_bus, NULL); 385 386 /* Free resources if any */ 387 if (sc->sc_mem_res[0]) 388 bus_release_resources(dev, am335x_musbotg_mem_spec, 389 sc->sc_mem_res); 390 391 if (sc->sc_otg.sc_irq_res) 392 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 393 sc->sc_otg.sc_irq_res); 394 395 return (0); 396 } 397 398 static device_method_t musbotg_methods[] = { 399 /* Device interface */ 400 DEVMETHOD(device_probe, musbotg_probe), 401 DEVMETHOD(device_attach, musbotg_attach), 402 DEVMETHOD(device_detach, musbotg_detach), 403 DEVMETHOD(device_suspend, bus_generic_suspend), 404 DEVMETHOD(device_resume, bus_generic_resume), 405 DEVMETHOD(device_shutdown, bus_generic_shutdown), 406 407 DEVMETHOD_END 408 }; 409 410 static driver_t musbotg_driver = { 411 .name = "musbotg", 412 .methods = musbotg_methods, 413 .size = sizeof(struct musbotg_super_softc), 414 }; 415 416 static devclass_t musbotg_devclass; 417 418 DRIVER_MODULE(musbotg, usbss, musbotg_driver, musbotg_devclass, 0, 0); 419 MODULE_DEPEND(musbotg, usbss, 1, 1, 1); 420