1 /*- 2 * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/clock.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <arm/ti/ti_prcm.h> 53 #include <arm/ti/ti_scm.h> 54 55 #include "am335x_lcd.h" 56 #include "am335x_pwm.h" 57 58 #define LCD_PID 0x00 59 #define LCD_CTRL 0x04 60 #define CTRL_DIV_MASK 0xff 61 #define CTRL_DIV_SHIFT 8 62 #define CTRL_AUTO_UFLOW_RESTART (1 << 1) 63 #define CTRL_RASTER_MODE 1 64 #define CTRL_LIDD_MODE 0 65 #define LCD_LIDD_CTRL 0x0C 66 #define LCD_LIDD_CS0_CONF 0x10 67 #define LCD_LIDD_CS0_ADDR 0x14 68 #define LCD_LIDD_CS0_DATA 0x18 69 #define LCD_LIDD_CS1_CONF 0x1C 70 #define LCD_LIDD_CS1_ADDR 0x20 71 #define LCD_LIDD_CS1_DATA 0x24 72 #define LCD_RASTER_CTRL 0x28 73 #define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 74 #define RASTER_CTRL_TFT24 (1 << 25) 75 #define RASTER_CTRL_STN565 (1 << 24) 76 #define RASTER_CTRL_TFTPMAP (1 << 23) 77 #define RASTER_CTRL_NIBMODE (1 << 22) 78 #define RASTER_CTRL_PALMODE_SHIFT 20 79 #define PALETTE_PALETTE_AND_DATA 0x00 80 #define PALETTE_PALETTE_ONLY 0x01 81 #define PALETTE_DATA_ONLY 0x02 82 #define RASTER_CTRL_REQDLY_SHIFT 12 83 #define RASTER_CTRL_MONO8B (1 << 9) 84 #define RASTER_CTRL_RBORDER (1 << 8) 85 #define RASTER_CTRL_LCDTFT (1 << 7) 86 #define RASTER_CTRL_LCDBW (1 << 1) 87 #define RASTER_CTRL_LCDEN (1 << 0) 88 #define LCD_RASTER_TIMING_0 0x2C 89 #define RASTER_TIMING_0_HBP_SHIFT 24 90 #define RASTER_TIMING_0_HFP_SHIFT 16 91 #define RASTER_TIMING_0_HSW_SHIFT 10 92 #define RASTER_TIMING_0_PPLLSB_SHIFT 4 93 #define RASTER_TIMING_0_PPLMSB_SHIFT 3 94 #define LCD_RASTER_TIMING_1 0x30 95 #define RASTER_TIMING_1_VBP_SHIFT 24 96 #define RASTER_TIMING_1_VFP_SHIFT 16 97 #define RASTER_TIMING_1_VSW_SHIFT 10 98 #define RASTER_TIMING_1_LPP_SHIFT 0 99 #define LCD_RASTER_TIMING_2 0x34 100 #define RASTER_TIMING_2_HSWHI_SHIFT 27 101 #define RASTER_TIMING_2_LPP_B10_SHIFT 26 102 #define RASTER_TIMING_2_PHSVS (1 << 25) 103 #define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 104 #define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 105 #define RASTER_TIMING_2_IOE (1 << 23) 106 #define RASTER_TIMING_2_IPC (1 << 22) 107 #define RASTER_TIMING_2_IHS (1 << 21) 108 #define RASTER_TIMING_2_IVS (1 << 20) 109 #define RASTER_TIMING_2_ACBI_SHIFT 16 110 #define RASTER_TIMING_2_ACB_SHIFT 8 111 #define RASTER_TIMING_2_HBPHI_SHIFT 4 112 #define RASTER_TIMING_2_HFPHI_SHIFT 0 113 #define LCD_RASTER_SUBPANEL 0x38 114 #define LCD_RASTER_SUBPANEL2 0x3C 115 #define LCD_LCDDMA_CTRL 0x40 116 #define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 117 #define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 118 #define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 119 #define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 120 #define LCDDMA_CTRL_BE (1 << 1) 121 #define LCDDMA_CTRL_FB0_ONLY 0 122 #define LCDDMA_CTRL_FB0_FB1 (1 << 0) 123 #define LCD_LCDDMA_FB0_BASE 0x44 124 #define LCD_LCDDMA_FB0_CEILING 0x48 125 #define LCD_LCDDMA_FB1_BASE 0x4C 126 #define LCD_LCDDMA_FB1_CEILING 0x50 127 #define LCD_SYSCONFIG 0x54 128 #define SYSCONFIG_STANDBY_FORCE (0 << 4) 129 #define SYSCONFIG_STANDBY_NONE (1 << 4) 130 #define SYSCONFIG_STANDBY_SMART (2 << 4) 131 #define SYSCONFIG_IDLE_FORCE (0 << 2) 132 #define SYSCONFIG_IDLE_NONE (1 << 2) 133 #define SYSCONFIG_IDLE_SMART (2 << 2) 134 #define LCD_IRQSTATUS_RAW 0x58 135 #define LCD_IRQSTATUS 0x5C 136 #define LCD_IRQENABLE_SET 0x60 137 #define LCD_IRQENABLE_CLEAR 0x64 138 #define IRQ_EOF1 (1 << 9) 139 #define IRQ_EOF0 (1 << 8) 140 #define IRQ_PL (1 << 6) 141 #define IRQ_FUF (1 << 5) 142 #define IRQ_ACB (1 << 3) 143 #define IRQ_SYNC_LOST (1 << 2) 144 #define IRQ_RASTER_DONE (1 << 1) 145 #define IRQ_FRAME_DONE (1 << 0) 146 #define LCD_CLKC_ENABLE 0x6C 147 #define CLKC_ENABLE_DMA (1 << 2) 148 #define CLKC_ENABLE_LDID (1 << 1) 149 #define CLKC_ENABLE_CORE (1 << 0) 150 #define LCD_CLKC_RESET 0x70 151 #define CLKC_RESET_MAIN (1 << 3) 152 #define CLKC_RESET_DMA (1 << 2) 153 #define CLKC_RESET_LDID (1 << 1) 154 #define CLKC_RESET_CORE (1 << 0) 155 156 #define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 157 #define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 158 #define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 159 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 160 #define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 161 162 #define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 163 #define LCD_WRITE4(_sc, reg, value) \ 164 bus_write_4((_sc)->sc_mem_res, reg, value); 165 166 167 /* Backlight is controlled by eCAS interface on PWM unit 0 */ 168 #define PWM_UNIT 0 169 #define PWM_PERIOD 100 170 171 struct am335x_lcd_softc { 172 device_t sc_dev; 173 struct resource *sc_mem_res; 174 struct resource *sc_irq_res; 175 void *sc_intr_hl; 176 struct mtx sc_mtx; 177 int sc_backlight; 178 struct sysctl_oid *sc_oid; 179 180 /* Framebuffer */ 181 bus_dma_tag_t sc_dma_tag; 182 bus_dmamap_t sc_dma_map; 183 size_t sc_fb_size; 184 bus_addr_t sc_fb_phys; 185 uint8_t *sc_fb_base; 186 }; 187 188 static void 189 am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 190 { 191 bus_addr_t *addr; 192 193 if (err) 194 return; 195 196 addr = (bus_addr_t*)arg; 197 *addr = segs[0].ds_addr; 198 } 199 200 static uint32_t 201 am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 202 { 203 uint32_t div; 204 /* Raster mode case: divisors are in range from 2 to 255 */ 205 for (div = 2; div < 255; div++) 206 if (reference/div <= freq) 207 return (div); 208 209 return (255); 210 } 211 212 static int 213 am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 214 { 215 struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 216 int error; 217 int backlight; 218 219 backlight = sc->sc_backlight;; 220 error = sysctl_handle_int(oidp, &backlight, 0, req); 221 222 if (error != 0 || req->newptr == NULL) 223 return (error); 224 225 if (backlight < 0) 226 backlight = 0; 227 if (backlight > 100) 228 backlight = 100; 229 230 LCD_LOCK(sc); 231 error = am335x_pwm_config_ecas(PWM_UNIT, PWM_PERIOD, 232 backlight*PWM_PERIOD/100); 233 if (error == 0) 234 sc->sc_backlight = backlight; 235 LCD_UNLOCK(sc); 236 237 return (error); 238 } 239 240 static int 241 am335x_read_panel_property(device_t dev, const char *name, uint32_t *val) 242 { 243 phandle_t node; 244 pcell_t cell; 245 246 node = ofw_bus_get_node(dev); 247 if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 248 device_printf(dev, "missing '%s' attribute in LCD panel info\n", 249 name); 250 return (ENXIO); 251 } 252 253 *val = fdt32_to_cpu(cell); 254 255 return (0); 256 } 257 258 static int 259 am335x_read_panel_info(device_t dev, struct panel_info *panel) 260 { 261 int error; 262 263 error = 0; 264 if ((error = am335x_read_panel_property(dev, 265 "panel_width", &panel->panel_width))) 266 goto out; 267 268 if ((error = am335x_read_panel_property(dev, 269 "panel_height", &panel->panel_height))) 270 goto out; 271 272 if ((error = am335x_read_panel_property(dev, 273 "panel_hfp", &panel->panel_hfp))) 274 goto out; 275 276 if ((error = am335x_read_panel_property(dev, 277 "panel_hbp", &panel->panel_hbp))) 278 goto out; 279 280 if ((error = am335x_read_panel_property(dev, 281 "panel_hsw", &panel->panel_hsw))) 282 goto out; 283 284 if ((error = am335x_read_panel_property(dev, 285 "panel_vfp", &panel->panel_vfp))) 286 goto out; 287 288 if ((error = am335x_read_panel_property(dev, 289 "panel_vbp", &panel->panel_vbp))) 290 goto out; 291 292 if ((error = am335x_read_panel_property(dev, 293 "panel_vsw", &panel->panel_vsw))) 294 goto out; 295 296 if ((error = am335x_read_panel_property(dev, 297 "panel_pxl_clk", &panel->panel_pxl_clk))) 298 goto out; 299 300 if ((error = am335x_read_panel_property(dev, 301 "panel_invert_pxl_clk", &panel->panel_invert_pxl_clk))) 302 goto out; 303 304 if ((error = am335x_read_panel_property(dev, 305 "ac_bias", &panel->ac_bias))) 306 goto out; 307 308 if ((error = am335x_read_panel_property(dev, 309 "ac_bias_intrpt", &panel->ac_bias_intrpt))) 310 goto out; 311 312 if ((error = am335x_read_panel_property(dev, 313 "dma_burst_sz", &panel->dma_burst_sz))) 314 goto out; 315 316 if ((error = am335x_read_panel_property(dev, 317 "bpp", &panel->bpp))) 318 goto out; 319 320 if ((error = am335x_read_panel_property(dev, 321 "fdd", &panel->fdd))) 322 goto out; 323 324 if ((error = am335x_read_panel_property(dev, 325 "invert_line_clock", &panel->invert_line_clock))) 326 goto out; 327 328 if ((error = am335x_read_panel_property(dev, 329 "invert_frm_clock", &panel->invert_frm_clock))) 330 goto out; 331 332 if ((error = am335x_read_panel_property(dev, 333 "sync_edge", &panel->sync_edge))) 334 goto out; 335 336 error = am335x_read_panel_property(dev, 337 "sync_ctrl", &panel->sync_ctrl); 338 339 out: 340 return (error); 341 } 342 343 static void 344 am335x_lcd_intr(void *arg) 345 { 346 struct am335x_lcd_softc *sc = arg; 347 uint32_t reg; 348 349 reg = LCD_READ4(sc, LCD_IRQSTATUS); 350 LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 351 352 if (reg & IRQ_SYNC_LOST) { 353 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 354 reg &= ~RASTER_CTRL_LCDEN; 355 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 356 357 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 358 reg |= RASTER_CTRL_LCDEN; 359 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 360 return; 361 } 362 363 if (reg & IRQ_PL) { 364 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 365 reg &= ~RASTER_CTRL_LCDEN; 366 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 367 368 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 369 reg |= RASTER_CTRL_LCDEN; 370 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 371 return; 372 } 373 374 if (reg & IRQ_EOF0) { 375 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 376 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 377 reg &= ~IRQ_EOF0; 378 } 379 380 if (reg & IRQ_EOF1) { 381 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 382 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 383 reg &= ~IRQ_EOF1; 384 } 385 386 if (reg & IRQ_FUF) { 387 /* TODO: Handle FUF */ 388 } 389 390 if (reg & IRQ_ACB) { 391 /* TODO: Handle ACB */ 392 } 393 } 394 395 static int 396 am335x_lcd_probe(device_t dev) 397 { 398 if (!ofw_bus_is_compatible(dev, "ti,am335x-lcd")) 399 return (ENXIO); 400 401 device_set_desc(dev, "AM335x LCD controller"); 402 403 return (0); 404 } 405 406 static int 407 am335x_lcd_attach(device_t dev) 408 { 409 struct am335x_lcd_softc *sc; 410 int rid; 411 int div; 412 struct panel_info panel; 413 uint32_t reg, timing0, timing1, timing2; 414 struct sysctl_ctx_list *ctx; 415 struct sysctl_oid *tree; 416 uint32_t burst_log; 417 int err; 418 size_t dma_size; 419 420 sc = device_get_softc(dev); 421 sc->sc_dev = dev; 422 423 if (am335x_read_panel_info(dev, &panel)) 424 return (ENXIO); 425 426 int ref_freq = 0; 427 ti_prcm_clk_enable(LCDC_CLK); 428 if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 429 device_printf(dev, "Can't get reference frequency\n"); 430 return (ENXIO); 431 } 432 433 rid = 0; 434 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 435 RF_ACTIVE); 436 if (!sc->sc_mem_res) { 437 device_printf(dev, "cannot allocate memory window\n"); 438 return (ENXIO); 439 } 440 441 rid = 0; 442 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 443 RF_ACTIVE); 444 if (!sc->sc_irq_res) { 445 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 446 device_printf(dev, "cannot allocate interrupt\n"); 447 return (ENXIO); 448 } 449 450 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 451 NULL, am335x_lcd_intr, sc, 452 &sc->sc_intr_hl) != 0) { 453 bus_release_resource(dev, SYS_RES_IRQ, rid, 454 sc->sc_irq_res); 455 bus_release_resource(dev, SYS_RES_MEMORY, rid, 456 sc->sc_mem_res); 457 device_printf(dev, "Unable to setup the irq handler.\n"); 458 return (ENXIO); 459 } 460 461 LCD_LOCK_INIT(sc); 462 463 /* Panle initialization */ 464 dma_size = round_page(panel.panel_width*panel.panel_height*panel.bpp/8); 465 466 /* 467 * Now allocate framebuffer memory 468 */ 469 err = bus_dma_tag_create( 470 bus_get_dma_tag(dev), 471 4, 0, /* alignment, boundary */ 472 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 473 BUS_SPACE_MAXADDR, /* highaddr */ 474 NULL, NULL, /* filter, filterarg */ 475 dma_size, 1, /* maxsize, nsegments */ 476 dma_size, 0, /* maxsegsize, flags */ 477 NULL, NULL, /* lockfunc, lockarg */ 478 &sc->sc_dma_tag); 479 if (err) 480 goto fail; 481 482 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 483 0, &sc->sc_dma_map); 484 485 if (err) { 486 device_printf(dev, "cannot allocate framebuffer\n"); 487 goto fail; 488 } 489 490 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 491 dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 492 493 if (err) { 494 device_printf(dev, "cannot load DMA map\n"); 495 goto fail; 496 } 497 498 /* Make sure it's blank */ 499 memset(sc->sc_fb_base, 0x00, dma_size); 500 501 /* Calculate actual FB Size */ 502 sc->sc_fb_size = panel.panel_width*panel.panel_height*panel.bpp/8; 503 504 /* Only raster mode is supported */ 505 reg = CTRL_RASTER_MODE; 506 div = am335x_lcd_calc_divisor(ref_freq, panel.panel_pxl_clk); 507 reg |= (div << CTRL_DIV_SHIFT); 508 LCD_WRITE4(sc, LCD_CTRL, reg); 509 510 /* Set timing */ 511 timing0 = timing1 = timing2 = 0; 512 513 /* Horizontal back porch */ 514 timing0 |= (panel.panel_hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 515 timing2 |= ((panel.panel_hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 516 /* Horizontal front porch */ 517 timing0 |= (panel.panel_hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 518 timing2 |= ((panel.panel_hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 519 /* Horizontal sync width */ 520 timing0 |= (panel.panel_hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 521 timing2 |= ((panel.panel_hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 522 523 /* Vertical back porch, front porch, sync width */ 524 timing1 |= (panel.panel_vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 525 timing1 |= (panel.panel_vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 526 timing1 |= (panel.panel_vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 527 528 /* Pixels per line */ 529 timing0 |= (((panel.panel_width - 1) >> 10) & 1) 530 << RASTER_TIMING_0_PPLMSB_SHIFT; 531 timing0 |= (((panel.panel_width - 1) >> 4) & 0x3f) 532 << RASTER_TIMING_0_PPLLSB_SHIFT; 533 534 /* Lines per panel */ 535 timing1 |= ((panel.panel_height - 1) & 0x3ff) 536 << RASTER_TIMING_1_LPP_SHIFT; 537 timing2 |= (((panel.panel_height - 1) >> 10 ) & 1) 538 << RASTER_TIMING_2_LPP_B10_SHIFT; 539 540 /* clock signal settings */ 541 if (panel.sync_ctrl) 542 timing2 |= RASTER_TIMING_2_PHSVS; 543 if (panel.sync_edge) 544 timing2 |= RASTER_TIMING_2_PHSVS_RISE; 545 else 546 timing2 |= RASTER_TIMING_2_PHSVS_FALL; 547 if (panel.invert_line_clock) 548 timing2 |= RASTER_TIMING_2_IHS; 549 if (panel.invert_frm_clock) 550 timing2 |= RASTER_TIMING_2_IVS; 551 if (panel.panel_invert_pxl_clk) 552 timing2 |= RASTER_TIMING_2_IPC; 553 554 /* AC bias */ 555 timing2 |= (panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 556 timing2 |= (panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 557 558 LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 559 LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 560 LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 561 562 /* DMA settings */ 563 reg = LCDDMA_CTRL_FB0_FB1; 564 /* Find power of 2 for current burst size */ 565 switch (panel.dma_burst_sz) { 566 case 1: 567 burst_log = 0; 568 break; 569 case 2: 570 burst_log = 1; 571 break; 572 case 4: 573 burst_log = 2; 574 break; 575 case 8: 576 burst_log = 3; 577 break; 578 case 16: 579 default: 580 burst_log = 4; 581 break; 582 } 583 reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 584 /* XXX: FIFO TH */ 585 reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 586 LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 587 588 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 589 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 590 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 591 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 592 593 /* Enable LCD */ 594 reg = RASTER_CTRL_LCDTFT; 595 reg |= (panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 596 reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 597 if (panel.bpp >= 24) 598 reg |= RASTER_CTRL_TFT24; 599 if (panel.bpp == 32) 600 reg |= RASTER_CTRL_TFT24_UNPACKED; 601 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 602 603 LCD_WRITE4(sc, LCD_CLKC_ENABLE, 604 CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 605 606 LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 607 DELAY(100); 608 LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 609 610 reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 611 IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 612 IRQ_FRAME_DONE; 613 LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 614 615 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 616 reg |= RASTER_CTRL_LCDEN; 617 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 618 619 LCD_WRITE4(sc, LCD_SYSCONFIG, 620 SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 621 622 /* Init backlight interface */ 623 ctx = device_get_sysctl_ctx(sc->sc_dev); 624 tree = device_get_sysctl_tree(sc->sc_dev); 625 sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 626 "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 627 am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 628 sc->sc_backlight = 0; 629 /* Check if eCAS interface is available at this point */ 630 if (am335x_pwm_config_ecas(PWM_UNIT, 631 PWM_PERIOD, PWM_PERIOD) == 0) 632 sc->sc_backlight = 100; 633 634 am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 635 636 return (0); 637 638 fail: 639 return (err); 640 } 641 642 static int 643 am335x_lcd_detach(device_t dev) 644 { 645 /* Do not let unload driver */ 646 return (EBUSY); 647 } 648 649 static device_method_t am335x_lcd_methods[] = { 650 DEVMETHOD(device_probe, am335x_lcd_probe), 651 DEVMETHOD(device_attach, am335x_lcd_attach), 652 DEVMETHOD(device_detach, am335x_lcd_detach), 653 654 DEVMETHOD_END 655 }; 656 657 static driver_t am335x_lcd_driver = { 658 "am335x_lcd", 659 am335x_lcd_methods, 660 sizeof(struct am335x_lcd_softc), 661 }; 662 663 static devclass_t am335x_lcd_devclass; 664 665 DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 666 MODULE_VERSION(am335x_lcd, 1); 667 MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 668