1 /*- 2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/limits.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "pwmbus_if.h" 49 50 #include "am335x_pwm.h" 51 52 /******************************************************************************* 53 * Enhanced resolution PWM driver. Many of the advanced featues of the hardware 54 * are not supported by this driver. What is implemented here is simple 55 * variable-duty-cycle PWM output. 56 * 57 * Note that this driver was historically configured using a set of sysctl 58 * variables/procs, and later gained support for the PWM(9) API. The sysctl 59 * code is still present to support existing apps, but that interface is 60 * considered deprecated. 61 * 62 * An important caveat is that the original sysctl interface and the new PWM API 63 * cannot both be used at once. If both interfaces are used to change 64 * configuration, it's quite likely you won't get the expected results. Also, 65 * reading the sysctl values after configuring via PWM will not return the right 66 * results. 67 ******************************************************************************/ 68 69 /* In ticks */ 70 #define DEFAULT_PWM_PERIOD 1000 71 #define PWM_CLOCK 100000000UL 72 73 #define NS_PER_SEC 1000000000 74 75 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 76 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 77 #define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 78 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 79 device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF) 80 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 81 82 #define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg) 83 #define EPWM_WRITE2(_sc, reg, value) \ 84 bus_write_2((_sc)->sc_mem_res, reg, value) 85 86 #define EPWM_TBCTL 0x00 87 #define TBCTL_FREERUN (2 << 14) 88 #define TBCTL_PHDIR_UP (1 << 13) 89 #define TBCTL_PHDIR_DOWN (0 << 13) 90 #define TBCTL_CLKDIV(x) ((x) << 10) 91 #define TBCTL_CLKDIV_MASK (3 << 10) 92 #define TBCTL_HSPCLKDIV(x) ((x) << 7) 93 #define TBCTL_HSPCLKDIV_MASK (3 << 7) 94 #define TBCTL_SYNCOSEL_DISABLED (3 << 4) 95 #define TBCTL_PRDLD_SHADOW (0 << 3) 96 #define TBCTL_PRDLD_IMMEDIATE (0 << 3) 97 #define TBCTL_PHSEN_ENABLED (1 << 2) 98 #define TBCTL_PHSEN_DISABLED (0 << 2) 99 #define TBCTL_CTRMODE_MASK (3) 100 #define TBCTL_CTRMODE_UP (0 << 0) 101 #define TBCTL_CTRMODE_DOWN (1 << 0) 102 #define TBCTL_CTRMODE_UPDOWN (2 << 0) 103 #define TBCTL_CTRMODE_FREEZE (3 << 0) 104 105 #define EPWM_TBSTS 0x02 106 #define EPWM_TBPHSHR 0x04 107 #define EPWM_TBPHS 0x06 108 #define EPWM_TBCNT 0x08 109 #define EPWM_TBPRD 0x0a 110 /* Counter-compare */ 111 #define EPWM_CMPCTL 0x0e 112 #define CMPCTL_SHDWBMODE_SHADOW (1 << 6) 113 #define CMPCTL_SHDWBMODE_IMMEDIATE (0 << 6) 114 #define CMPCTL_SHDWAMODE_SHADOW (1 << 4) 115 #define CMPCTL_SHDWAMODE_IMMEDIATE (0 << 4) 116 #define CMPCTL_LOADBMODE_ZERO (0 << 2) 117 #define CMPCTL_LOADBMODE_PRD (1 << 2) 118 #define CMPCTL_LOADBMODE_EITHER (2 << 2) 119 #define CMPCTL_LOADBMODE_FREEZE (3 << 2) 120 #define CMPCTL_LOADAMODE_ZERO (0 << 0) 121 #define CMPCTL_LOADAMODE_PRD (1 << 0) 122 #define CMPCTL_LOADAMODE_EITHER (2 << 0) 123 #define CMPCTL_LOADAMODE_FREEZE (3 << 0) 124 #define EPWM_CMPAHR 0x10 125 #define EPWM_CMPA 0x12 126 #define EPWM_CMPB 0x14 127 /* CMPCTL_LOADAMODE_ZERO */ 128 #define EPWM_AQCTLA 0x16 129 #define EPWM_AQCTLB 0x18 130 #define AQCTL_CBU_NONE (0 << 8) 131 #define AQCTL_CBU_CLEAR (1 << 8) 132 #define AQCTL_CBU_SET (2 << 8) 133 #define AQCTL_CBU_TOGGLE (3 << 8) 134 #define AQCTL_CAU_NONE (0 << 4) 135 #define AQCTL_CAU_CLEAR (1 << 4) 136 #define AQCTL_CAU_SET (2 << 4) 137 #define AQCTL_CAU_TOGGLE (3 << 4) 138 #define AQCTL_ZRO_NONE (0 << 0) 139 #define AQCTL_ZRO_CLEAR (1 << 0) 140 #define AQCTL_ZRO_SET (2 << 0) 141 #define AQCTL_ZRO_TOGGLE (3 << 0) 142 #define EPWM_AQSFRC 0x1a 143 #define EPWM_AQCSFRC 0x1c 144 #define AQCSFRC_OFF 0 145 #define AQCSFRC_LO 1 146 #define AQCSFRC_HI 2 147 #define AQCSFRC_MASK 3 148 #define AQCSFRC(chan, hilo) ((hilo) << (2 * chan)) 149 150 /* Trip-Zone module */ 151 #define EPWM_TZCTL 0x28 152 #define EPWM_TZFLG 0x2C 153 /* High-Resolution PWM */ 154 #define EPWM_HRCTL 0x40 155 #define HRCTL_DELMODE_BOTH 3 156 #define HRCTL_DELMODE_FALL 2 157 #define HRCTL_DELMODE_RISE 1 158 159 static device_probe_t am335x_ehrpwm_probe; 160 static device_attach_t am335x_ehrpwm_attach; 161 static device_detach_t am335x_ehrpwm_detach; 162 163 static int am335x_ehrpwm_clkdiv[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; 164 165 struct ehrpwm_channel { 166 u_int duty; /* on duration, in ns */ 167 bool enabled; /* channel enabled? */ 168 bool inverted; /* signal inverted? */ 169 }; 170 #define NUM_CHANNELS 2 171 172 struct am335x_ehrpwm_softc { 173 device_t sc_dev; 174 device_t sc_busdev; 175 struct mtx sc_mtx; 176 struct resource *sc_mem_res; 177 int sc_mem_rid; 178 179 /* Things used for configuration via sysctl [deprecated]. */ 180 int sc_pwm_clkdiv; 181 int sc_pwm_freq; 182 struct sysctl_oid *sc_clkdiv_oid; 183 struct sysctl_oid *sc_freq_oid; 184 struct sysctl_oid *sc_period_oid; 185 struct sysctl_oid *sc_chanA_oid; 186 struct sysctl_oid *sc_chanB_oid; 187 uint32_t sc_pwm_period; 188 uint32_t sc_pwm_dutyA; 189 uint32_t sc_pwm_dutyB; 190 191 /* Things used for configuration via pwm(9) api. */ 192 u_int sc_clkfreq; /* frequency in Hz */ 193 u_int sc_clktick; /* duration in ns */ 194 u_int sc_period; /* duration in ns */ 195 struct ehrpwm_channel sc_channels[NUM_CHANNELS]; 196 }; 197 198 static struct ofw_compat_data compat_data[] = { 199 {"ti,am33xx-ehrpwm", true}, 200 {NULL, false}, 201 }; 202 SIMPLEBUS_PNP_INFO(compat_data); 203 204 static void 205 am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc *sc, u_int chan, u_int duty) 206 { 207 u_int tbcmp; 208 209 if (duty == 0) 210 tbcmp = 0; 211 else 212 tbcmp = max(1, duty / sc->sc_clktick); 213 214 sc->sc_channels[chan].duty = tbcmp * sc->sc_clktick; 215 216 PWM_LOCK_ASSERT(sc); 217 EPWM_WRITE2(sc, (chan == 0) ? EPWM_CMPA : EPWM_CMPB, tbcmp); 218 } 219 220 static void 221 am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc *sc, u_int chan, bool enable) 222 { 223 uint16_t regval; 224 225 sc->sc_channels[chan].enabled = enable; 226 227 /* 228 * Turn off any existing software-force of the channel, then force 229 * it in the right direction (high or low) if it's not being enabled. 230 */ 231 PWM_LOCK_ASSERT(sc); 232 regval = EPWM_READ2(sc, EPWM_AQCSFRC); 233 regval &= ~AQCSFRC(chan, AQCSFRC_MASK); 234 if (!sc->sc_channels[chan].enabled) { 235 if (sc->sc_channels[chan].inverted) 236 regval |= AQCSFRC(chan, AQCSFRC_HI); 237 else 238 regval |= AQCSFRC(chan, AQCSFRC_LO); 239 } 240 EPWM_WRITE2(sc, EPWM_AQCSFRC, regval); 241 } 242 243 static bool 244 am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc *sc, u_int period) 245 { 246 uint16_t regval; 247 u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd; 248 249 /* Can't do a period shorter than 2 clock ticks. */ 250 if (period < 2 * NS_PER_SEC / PWM_CLOCK) { 251 sc->sc_clkfreq = 0; 252 sc->sc_clktick = 0; 253 sc->sc_period = 0; 254 return (false); 255 } 256 257 /* 258 * Figure out how much we have to divide down the base 100MHz clock so 259 * that we can express the requested period as a 16-bit tick count. 260 */ 261 tbprd = 0; 262 for (clkdiv = 0; clkdiv < 8; ++clkdiv) { 263 const u_int cd = 1 << clkdiv; 264 for (hspclkdiv = 0; hspclkdiv < 8; ++hspclkdiv) { 265 const u_int cdhs = max(1, hspclkdiv * 2); 266 pwmclk = PWM_CLOCK / (cd * cdhs); 267 pwmtick = NS_PER_SEC / pwmclk; 268 if (period / pwmtick < 65536) { 269 tbprd = period / pwmtick; 270 break; 271 } 272 } 273 if (tbprd != 0) 274 break; 275 } 276 277 /* Handle requested period too long for available clock divisors. */ 278 if (tbprd == 0) 279 return (false); 280 281 /* 282 * If anything has changed from the current settings, reprogram the 283 * clock divisors and period register. 284 */ 285 if (sc->sc_clkfreq != pwmclk || sc->sc_clktick != pwmtick || 286 sc->sc_period != tbprd * pwmtick) { 287 sc->sc_clkfreq = pwmclk; 288 sc->sc_clktick = pwmtick; 289 sc->sc_period = tbprd * pwmtick; 290 291 PWM_LOCK_ASSERT(sc); 292 regval = EPWM_READ2(sc, EPWM_TBCTL); 293 regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK); 294 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv); 295 EPWM_WRITE2(sc, EPWM_TBCTL, regval); 296 EPWM_WRITE2(sc, EPWM_TBPRD, tbprd - 1); 297 #if 0 298 device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u " 299 "clkfreq %u Hz clktick %u ns period got %u requested %u\n", 300 clkdiv, hspclkdiv, tbprd - 1, 301 sc->sc_clkfreq, sc->sc_clktick, sc->sc_period, period); 302 #endif 303 /* 304 * If the period changed, that invalidates the current CMP 305 * registers (duty values), just zero them out. 306 */ 307 am335x_ehrpwm_cfg_duty(sc, 0, 0); 308 am335x_ehrpwm_cfg_duty(sc, 1, 0); 309 } 310 311 return (true); 312 } 313 314 static void 315 am335x_ehrpwm_freq(struct am335x_ehrpwm_softc *sc) 316 { 317 int clkdiv; 318 319 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]; 320 sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period; 321 } 322 323 static int 324 am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS) 325 { 326 int clkdiv, error, freq, i, period; 327 struct am335x_ehrpwm_softc *sc; 328 uint32_t reg; 329 330 sc = (struct am335x_ehrpwm_softc *)arg1; 331 332 PWM_LOCK(sc); 333 freq = sc->sc_pwm_freq; 334 PWM_UNLOCK(sc); 335 336 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 337 if (error != 0 || req->newptr == NULL) 338 return (error); 339 340 if (freq > PWM_CLOCK) 341 freq = PWM_CLOCK; 342 343 PWM_LOCK(sc); 344 if (freq != sc->sc_pwm_freq) { 345 for (i = nitems(am335x_ehrpwm_clkdiv) - 1; i >= 0; i--) { 346 clkdiv = am335x_ehrpwm_clkdiv[i]; 347 period = PWM_CLOCK / clkdiv / freq; 348 if (period > USHRT_MAX) 349 break; 350 sc->sc_pwm_clkdiv = i; 351 sc->sc_pwm_period = period; 352 } 353 /* Reset the duty cycle settings. */ 354 sc->sc_pwm_dutyA = 0; 355 sc->sc_pwm_dutyB = 0; 356 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 357 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 358 /* Update the clkdiv settings. */ 359 reg = EPWM_READ2(sc, EPWM_TBCTL); 360 reg &= ~TBCTL_CLKDIV_MASK; 361 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv); 362 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 363 /* Update the period settings. */ 364 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1); 365 am335x_ehrpwm_freq(sc); 366 } 367 PWM_UNLOCK(sc); 368 369 return (0); 370 } 371 372 static int 373 am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS) 374 { 375 int error, i, clkdiv; 376 struct am335x_ehrpwm_softc *sc; 377 uint32_t reg; 378 379 sc = (struct am335x_ehrpwm_softc *)arg1; 380 381 PWM_LOCK(sc); 382 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]; 383 PWM_UNLOCK(sc); 384 385 error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req); 386 if (error != 0 || req->newptr == NULL) 387 return (error); 388 389 PWM_LOCK(sc); 390 if (clkdiv != am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]) { 391 for (i = 0; i < nitems(am335x_ehrpwm_clkdiv); i++) 392 if (clkdiv >= am335x_ehrpwm_clkdiv[i]) 393 sc->sc_pwm_clkdiv = i; 394 395 reg = EPWM_READ2(sc, EPWM_TBCTL); 396 reg &= ~TBCTL_CLKDIV_MASK; 397 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv); 398 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 399 am335x_ehrpwm_freq(sc); 400 } 401 PWM_UNLOCK(sc); 402 403 return (0); 404 } 405 406 static int 407 am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS) 408 { 409 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1; 410 int error; 411 uint32_t duty; 412 413 if (oidp == sc->sc_chanA_oid) 414 duty = sc->sc_pwm_dutyA; 415 else 416 duty = sc->sc_pwm_dutyB; 417 error = sysctl_handle_int(oidp, &duty, 0, req); 418 419 if (error != 0 || req->newptr == NULL) 420 return (error); 421 422 if (duty > sc->sc_pwm_period) { 423 device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n"); 424 return (EINVAL); 425 } 426 427 PWM_LOCK(sc); 428 if (oidp == sc->sc_chanA_oid) { 429 sc->sc_pwm_dutyA = duty; 430 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 431 } 432 else { 433 sc->sc_pwm_dutyB = duty; 434 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 435 } 436 PWM_UNLOCK(sc); 437 438 return (error); 439 } 440 441 static int 442 am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS) 443 { 444 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1; 445 int error; 446 uint32_t period; 447 448 period = sc->sc_pwm_period; 449 error = sysctl_handle_int(oidp, &period, 0, req); 450 451 if (error != 0 || req->newptr == NULL) 452 return (error); 453 454 if (period < 1) 455 return (EINVAL); 456 457 if (period > USHRT_MAX) 458 period = USHRT_MAX; 459 460 PWM_LOCK(sc); 461 /* Reset the duty cycle settings. */ 462 sc->sc_pwm_dutyA = 0; 463 sc->sc_pwm_dutyB = 0; 464 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 465 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 466 /* Update the period settings. */ 467 sc->sc_pwm_period = period; 468 EPWM_WRITE2(sc, EPWM_TBPRD, period - 1); 469 am335x_ehrpwm_freq(sc); 470 PWM_UNLOCK(sc); 471 472 return (error); 473 } 474 475 static int 476 am335x_ehrpwm_channel_count(device_t dev, u_int *nchannel) 477 { 478 479 *nchannel = NUM_CHANNELS; 480 481 return (0); 482 } 483 484 static int 485 am335x_ehrpwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty) 486 { 487 struct am335x_ehrpwm_softc *sc; 488 bool status; 489 490 if (channel >= NUM_CHANNELS) 491 return (EINVAL); 492 493 sc = device_get_softc(dev); 494 495 PWM_LOCK(sc); 496 status = am335x_ehrpwm_cfg_period(sc, period); 497 if (status) 498 am335x_ehrpwm_cfg_duty(sc, channel, duty); 499 PWM_UNLOCK(sc); 500 501 return (status ? 0 : EINVAL); 502 } 503 504 static int 505 am335x_ehrpwm_channel_get_config(device_t dev, u_int channel, 506 u_int *period, u_int *duty) 507 { 508 struct am335x_ehrpwm_softc *sc; 509 510 if (channel >= NUM_CHANNELS) 511 return (EINVAL); 512 513 sc = device_get_softc(dev); 514 *period = sc->sc_period; 515 *duty = sc->sc_channels[channel].duty; 516 return (0); 517 } 518 519 static int 520 am335x_ehrpwm_channel_enable(device_t dev, u_int channel, bool enable) 521 { 522 struct am335x_ehrpwm_softc *sc; 523 524 if (channel >= NUM_CHANNELS) 525 return (EINVAL); 526 527 sc = device_get_softc(dev); 528 529 PWM_LOCK(sc); 530 am335x_ehrpwm_cfg_enable(sc, channel, enable); 531 PWM_UNLOCK(sc); 532 533 return (0); 534 } 535 536 static int 537 am335x_ehrpwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled) 538 { 539 struct am335x_ehrpwm_softc *sc; 540 541 if (channel >= NUM_CHANNELS) 542 return (EINVAL); 543 544 sc = device_get_softc(dev); 545 546 *enabled = sc->sc_channels[channel].enabled; 547 548 return (0); 549 } 550 551 static int 552 am335x_ehrpwm_probe(device_t dev) 553 { 554 555 if (!ofw_bus_status_okay(dev)) 556 return (ENXIO); 557 558 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 559 return (ENXIO); 560 561 device_set_desc(dev, "AM335x EHRPWM"); 562 563 return (BUS_PROBE_DEFAULT); 564 } 565 566 static int 567 am335x_ehrpwm_attach(device_t dev) 568 { 569 struct am335x_ehrpwm_softc *sc; 570 uint32_t reg; 571 struct sysctl_ctx_list *ctx; 572 struct sysctl_oid *tree; 573 574 sc = device_get_softc(dev); 575 sc->sc_dev = dev; 576 577 PWM_LOCK_INIT(sc); 578 579 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 580 &sc->sc_mem_rid, RF_ACTIVE); 581 if (sc->sc_mem_res == NULL) { 582 device_printf(dev, "cannot allocate memory resources\n"); 583 goto fail; 584 } 585 586 /* Init sysctl interface */ 587 ctx = device_get_sysctl_ctx(sc->sc_dev); 588 tree = device_get_sysctl_tree(sc->sc_dev); 589 590 sc->sc_clkdiv_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 591 "clkdiv", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 592 am335x_ehrpwm_sysctl_clkdiv, "I", "PWM clock prescaler"); 593 594 sc->sc_freq_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 595 "freq", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 596 am335x_ehrpwm_sysctl_freq, "I", "PWM frequency"); 597 598 sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 599 "period", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 600 am335x_ehrpwm_sysctl_period, "I", "PWM period"); 601 602 sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 603 "dutyA", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 604 am335x_ehrpwm_sysctl_duty, "I", "Channel A duty cycles"); 605 606 sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 607 "dutyB", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 608 am335x_ehrpwm_sysctl_duty, "I", "Channel B duty cycles"); 609 610 /* CONFIGURE EPWM1 */ 611 reg = EPWM_READ2(sc, EPWM_TBCTL); 612 reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK); 613 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 614 615 sc->sc_pwm_period = DEFAULT_PWM_PERIOD; 616 sc->sc_pwm_dutyA = 0; 617 sc->sc_pwm_dutyB = 0; 618 am335x_ehrpwm_freq(sc); 619 620 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1); 621 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 622 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 623 624 EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR)); 625 EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR)); 626 627 /* START EPWM */ 628 reg &= ~TBCTL_CTRMODE_MASK; 629 reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN; 630 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 631 632 EPWM_WRITE2(sc, EPWM_TZCTL, 0xf); 633 reg = EPWM_READ2(sc, EPWM_TZFLG); 634 635 if ((sc->sc_busdev = device_add_child(dev, "pwmbus", -1)) == NULL) { 636 device_printf(dev, "Cannot add child pwmbus\n"); 637 // This driver can still do things even without the bus child. 638 } 639 640 bus_generic_probe(dev); 641 return (bus_generic_attach(dev)); 642 fail: 643 PWM_LOCK_DESTROY(sc); 644 if (sc->sc_mem_res) 645 bus_release_resource(dev, SYS_RES_MEMORY, 646 sc->sc_mem_rid, sc->sc_mem_res); 647 648 return(ENXIO); 649 } 650 651 static int 652 am335x_ehrpwm_detach(device_t dev) 653 { 654 struct am335x_ehrpwm_softc *sc; 655 int error; 656 657 sc = device_get_softc(dev); 658 659 if ((error = bus_generic_detach(sc->sc_dev)) != 0) 660 return (error); 661 662 PWM_LOCK(sc); 663 664 if (sc->sc_busdev != NULL) 665 device_delete_child(dev, sc->sc_busdev); 666 667 if (sc->sc_mem_res) 668 bus_release_resource(dev, SYS_RES_MEMORY, 669 sc->sc_mem_rid, sc->sc_mem_res); 670 671 PWM_UNLOCK(sc); 672 673 PWM_LOCK_DESTROY(sc); 674 675 return (0); 676 } 677 678 static phandle_t 679 am335x_ehrpwm_get_node(device_t bus, device_t dev) 680 { 681 682 /* 683 * Share our controller node with our pwmbus child; it instantiates 684 * devices by walking the children contained within our node. 685 */ 686 return ofw_bus_get_node(bus); 687 } 688 689 static device_method_t am335x_ehrpwm_methods[] = { 690 DEVMETHOD(device_probe, am335x_ehrpwm_probe), 691 DEVMETHOD(device_attach, am335x_ehrpwm_attach), 692 DEVMETHOD(device_detach, am335x_ehrpwm_detach), 693 694 /* ofw_bus_if */ 695 DEVMETHOD(ofw_bus_get_node, am335x_ehrpwm_get_node), 696 697 /* pwm interface */ 698 DEVMETHOD(pwmbus_channel_count, am335x_ehrpwm_channel_count), 699 DEVMETHOD(pwmbus_channel_config, am335x_ehrpwm_channel_config), 700 DEVMETHOD(pwmbus_channel_get_config, am335x_ehrpwm_channel_get_config), 701 DEVMETHOD(pwmbus_channel_enable, am335x_ehrpwm_channel_enable), 702 DEVMETHOD(pwmbus_channel_is_enabled, am335x_ehrpwm_channel_is_enabled), 703 704 DEVMETHOD_END 705 }; 706 707 static driver_t am335x_ehrpwm_driver = { 708 "pwm", 709 am335x_ehrpwm_methods, 710 sizeof(struct am335x_ehrpwm_softc), 711 }; 712 713 static devclass_t am335x_ehrpwm_devclass; 714 715 DRIVER_MODULE(am335x_ehrpwm, am335x_pwmss, am335x_ehrpwm_driver, am335x_ehrpwm_devclass, 0, 0); 716 MODULE_VERSION(am335x_ehrpwm, 1); 717 MODULE_DEPEND(am335x_ehrpwm, am335x_pwmss, 1, 1, 1); 718 MODULE_DEPEND(am335x_ehrpwm, pwmbus, 1, 1, 1); 719