1 /*- 2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/limits.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "pwmbus_if.h" 49 50 #include "am335x_pwm.h" 51 52 /******************************************************************************* 53 * Enhanced resolution PWM driver. Many of the advanced featues of the hardware 54 * are not supported by this driver. What is implemented here is simple 55 * variable-duty-cycle PWM output. 56 * 57 * Note that this driver was historically configured using a set of sysctl 58 * variables/procs, and later gained support for the PWM(9) API. The sysctl 59 * code is still present to support existing apps, but that interface is 60 * considered deprecated. 61 * 62 * An important caveat is that the original sysctl interface and the new PWM API 63 * cannot both be used at once. If both interfaces are used to change 64 * configuration, it's quite likely you won't get the expected results. Also, 65 * reading the sysctl values after configuring via PWM will not return the right 66 * results. 67 ******************************************************************************/ 68 69 /* In ticks */ 70 #define DEFAULT_PWM_PERIOD 1000 71 #define PWM_CLOCK 100000000UL 72 73 #define NS_PER_SEC 1000000000 74 75 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 76 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 77 #define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 78 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 79 device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF) 80 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 81 82 #define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg) 83 #define EPWM_WRITE2(_sc, reg, value) \ 84 bus_write_2((_sc)->sc_mem_res, reg, value) 85 86 #define EPWM_TBCTL 0x00 87 #define TBCTL_FREERUN (2 << 14) 88 #define TBCTL_PHDIR_UP (1 << 13) 89 #define TBCTL_PHDIR_DOWN (0 << 13) 90 #define TBCTL_CLKDIV(x) ((x) << 10) 91 #define TBCTL_CLKDIV_MASK (3 << 10) 92 #define TBCTL_HSPCLKDIV(x) ((x) << 7) 93 #define TBCTL_HSPCLKDIV_MASK (3 << 7) 94 #define TBCTL_SYNCOSEL_DISABLED (3 << 4) 95 #define TBCTL_PRDLD_SHADOW (0 << 3) 96 #define TBCTL_PRDLD_IMMEDIATE (0 << 3) 97 #define TBCTL_PHSEN_ENABLED (1 << 2) 98 #define TBCTL_PHSEN_DISABLED (0 << 2) 99 #define TBCTL_CTRMODE_MASK (3) 100 #define TBCTL_CTRMODE_UP (0 << 0) 101 #define TBCTL_CTRMODE_DOWN (1 << 0) 102 #define TBCTL_CTRMODE_UPDOWN (2 << 0) 103 #define TBCTL_CTRMODE_FREEZE (3 << 0) 104 105 #define EPWM_TBSTS 0x02 106 #define EPWM_TBPHSHR 0x04 107 #define EPWM_TBPHS 0x06 108 #define EPWM_TBCNT 0x08 109 #define EPWM_TBPRD 0x0a 110 /* Counter-compare */ 111 #define EPWM_CMPCTL 0x0e 112 #define CMPCTL_SHDWBMODE_SHADOW (1 << 6) 113 #define CMPCTL_SHDWBMODE_IMMEDIATE (0 << 6) 114 #define CMPCTL_SHDWAMODE_SHADOW (1 << 4) 115 #define CMPCTL_SHDWAMODE_IMMEDIATE (0 << 4) 116 #define CMPCTL_LOADBMODE_ZERO (0 << 2) 117 #define CMPCTL_LOADBMODE_PRD (1 << 2) 118 #define CMPCTL_LOADBMODE_EITHER (2 << 2) 119 #define CMPCTL_LOADBMODE_FREEZE (3 << 2) 120 #define CMPCTL_LOADAMODE_ZERO (0 << 0) 121 #define CMPCTL_LOADAMODE_PRD (1 << 0) 122 #define CMPCTL_LOADAMODE_EITHER (2 << 0) 123 #define CMPCTL_LOADAMODE_FREEZE (3 << 0) 124 #define EPWM_CMPAHR 0x10 125 #define EPWM_CMPA 0x12 126 #define EPWM_CMPB 0x14 127 /* CMPCTL_LOADAMODE_ZERO */ 128 #define EPWM_AQCTLA 0x16 129 #define EPWM_AQCTLB 0x18 130 #define AQCTL_CBU_NONE (0 << 8) 131 #define AQCTL_CBU_CLEAR (1 << 8) 132 #define AQCTL_CBU_SET (2 << 8) 133 #define AQCTL_CBU_TOGGLE (3 << 8) 134 #define AQCTL_CAU_NONE (0 << 4) 135 #define AQCTL_CAU_CLEAR (1 << 4) 136 #define AQCTL_CAU_SET (2 << 4) 137 #define AQCTL_CAU_TOGGLE (3 << 4) 138 #define AQCTL_ZRO_NONE (0 << 0) 139 #define AQCTL_ZRO_CLEAR (1 << 0) 140 #define AQCTL_ZRO_SET (2 << 0) 141 #define AQCTL_ZRO_TOGGLE (3 << 0) 142 #define EPWM_AQSFRC 0x1a 143 #define EPWM_AQCSFRC 0x1c 144 #define AQCSFRC_OFF 0 145 #define AQCSFRC_LO 1 146 #define AQCSFRC_HI 2 147 #define AQCSFRC_MASK 3 148 #define AQCSFRC(chan, hilo) ((hilo) << (2 * chan)) 149 150 /* Trip-Zone module */ 151 #define EPWM_TZCTL 0x28 152 #define EPWM_TZFLG 0x2C 153 /* High-Resolution PWM */ 154 #define EPWM_HRCTL 0x40 155 #define HRCTL_DELMODE_BOTH 3 156 #define HRCTL_DELMODE_FALL 2 157 #define HRCTL_DELMODE_RISE 1 158 159 static device_probe_t am335x_ehrpwm_probe; 160 static device_attach_t am335x_ehrpwm_attach; 161 static device_detach_t am335x_ehrpwm_detach; 162 163 static int am335x_ehrpwm_clkdiv[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; 164 165 struct ehrpwm_channel { 166 u_int duty; /* on duration, in ns */ 167 bool enabled; /* channel enabled? */ 168 bool inverted; /* signal inverted? */ 169 }; 170 #define NUM_CHANNELS 2 171 172 struct am335x_ehrpwm_softc { 173 device_t sc_dev; 174 device_t sc_busdev; 175 struct mtx sc_mtx; 176 struct resource *sc_mem_res; 177 int sc_mem_rid; 178 179 /* Things used for configuration via sysctl [deprecated]. */ 180 int sc_pwm_clkdiv; 181 int sc_pwm_freq; 182 struct sysctl_oid *sc_clkdiv_oid; 183 struct sysctl_oid *sc_freq_oid; 184 struct sysctl_oid *sc_period_oid; 185 struct sysctl_oid *sc_chanA_oid; 186 struct sysctl_oid *sc_chanB_oid; 187 uint32_t sc_pwm_period; 188 uint32_t sc_pwm_dutyA; 189 uint32_t sc_pwm_dutyB; 190 191 /* Things used for configuration via pwm(9) api. */ 192 u_int sc_clkfreq; /* frequency in Hz */ 193 u_int sc_clktick; /* duration in ns */ 194 u_int sc_period; /* duration in ns */ 195 struct ehrpwm_channel sc_channels[NUM_CHANNELS]; 196 }; 197 198 static struct ofw_compat_data compat_data[] = { 199 {"ti,am33xx-ehrpwm", true}, 200 {NULL, false}, 201 }; 202 203 static void 204 am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc *sc, u_int chan, u_int duty) 205 { 206 u_int tbcmp; 207 208 if (duty == 0) 209 tbcmp = 0; 210 else 211 tbcmp = max(1, duty / sc->sc_clktick); 212 213 sc->sc_channels[chan].duty = tbcmp * sc->sc_clktick; 214 215 PWM_LOCK_ASSERT(sc); 216 EPWM_WRITE2(sc, (chan == 0) ? EPWM_CMPA : EPWM_CMPB, tbcmp); 217 } 218 219 static void 220 am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc *sc, u_int chan, bool enable) 221 { 222 uint16_t regval; 223 224 sc->sc_channels[chan].enabled = enable; 225 226 /* 227 * Turn off any existing software-force of the channel, then force 228 * it in the right direction (high or low) if it's not being enabled. 229 */ 230 PWM_LOCK_ASSERT(sc); 231 regval = EPWM_READ2(sc, EPWM_AQCSFRC); 232 regval &= ~AQCSFRC(chan, AQCSFRC_MASK); 233 if (!sc->sc_channels[chan].enabled) { 234 if (sc->sc_channels[chan].inverted) 235 regval |= AQCSFRC(chan, AQCSFRC_HI); 236 else 237 regval |= AQCSFRC(chan, AQCSFRC_LO); 238 } 239 EPWM_WRITE2(sc, EPWM_AQCSFRC, regval); 240 } 241 242 static bool 243 am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc *sc, u_int period) 244 { 245 uint16_t regval; 246 u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd; 247 248 /* Can't do a period shorter than 2 clock ticks. */ 249 if (period < 2 * NS_PER_SEC / PWM_CLOCK) { 250 sc->sc_clkfreq = 0; 251 sc->sc_clktick = 0; 252 sc->sc_period = 0; 253 return (false); 254 } 255 256 /* 257 * Figure out how much we have to divide down the base 100MHz clock so 258 * that we can express the requested period as a 16-bit tick count. 259 */ 260 tbprd = 0; 261 for (clkdiv = 0; clkdiv < 8; ++clkdiv) { 262 const u_int cd = 1 << clkdiv; 263 for (hspclkdiv = 0; hspclkdiv < 8; ++hspclkdiv) { 264 const u_int cdhs = max(1, hspclkdiv * 2); 265 pwmclk = PWM_CLOCK / (cd * cdhs); 266 pwmtick = NS_PER_SEC / pwmclk; 267 if (period / pwmtick < 65536) { 268 tbprd = period / pwmtick; 269 break; 270 } 271 } 272 if (tbprd != 0) 273 break; 274 } 275 276 /* Handle requested period too long for available clock divisors. */ 277 if (tbprd == 0) 278 return (false); 279 280 /* 281 * If anything has changed from the current settings, reprogram the 282 * clock divisors and period register. 283 */ 284 if (sc->sc_clkfreq != pwmclk || sc->sc_clktick != pwmtick || 285 sc->sc_period != tbprd * pwmtick) { 286 sc->sc_clkfreq = pwmclk; 287 sc->sc_clktick = pwmtick; 288 sc->sc_period = tbprd * pwmtick; 289 290 PWM_LOCK_ASSERT(sc); 291 regval = EPWM_READ2(sc, EPWM_TBCTL); 292 regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK); 293 regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv); 294 EPWM_WRITE2(sc, EPWM_TBCTL, regval); 295 EPWM_WRITE2(sc, EPWM_TBPRD, tbprd - 1); 296 #if 0 297 device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u " 298 "clkfreq %u Hz clktick %u ns period got %u requested %u\n", 299 clkdiv, hspclkdiv, tbprd - 1, 300 sc->sc_clkfreq, sc->sc_clktick, sc->sc_period, period); 301 #endif 302 /* 303 * If the period changed, that invalidates the current CMP 304 * registers (duty values), just zero them out. 305 */ 306 am335x_ehrpwm_cfg_duty(sc, 0, 0); 307 am335x_ehrpwm_cfg_duty(sc, 1, 0); 308 } 309 310 return (true); 311 } 312 313 static void 314 am335x_ehrpwm_freq(struct am335x_ehrpwm_softc *sc) 315 { 316 int clkdiv; 317 318 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]; 319 sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period; 320 } 321 322 static int 323 am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS) 324 { 325 int clkdiv, error, freq, i, period; 326 struct am335x_ehrpwm_softc *sc; 327 uint32_t reg; 328 329 sc = (struct am335x_ehrpwm_softc *)arg1; 330 331 PWM_LOCK(sc); 332 freq = sc->sc_pwm_freq; 333 PWM_UNLOCK(sc); 334 335 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 336 if (error != 0 || req->newptr == NULL) 337 return (error); 338 339 if (freq > PWM_CLOCK) 340 freq = PWM_CLOCK; 341 342 PWM_LOCK(sc); 343 if (freq != sc->sc_pwm_freq) { 344 for (i = nitems(am335x_ehrpwm_clkdiv) - 1; i >= 0; i--) { 345 clkdiv = am335x_ehrpwm_clkdiv[i]; 346 period = PWM_CLOCK / clkdiv / freq; 347 if (period > USHRT_MAX) 348 break; 349 sc->sc_pwm_clkdiv = i; 350 sc->sc_pwm_period = period; 351 } 352 /* Reset the duty cycle settings. */ 353 sc->sc_pwm_dutyA = 0; 354 sc->sc_pwm_dutyB = 0; 355 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 356 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 357 /* Update the clkdiv settings. */ 358 reg = EPWM_READ2(sc, EPWM_TBCTL); 359 reg &= ~TBCTL_CLKDIV_MASK; 360 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv); 361 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 362 /* Update the period settings. */ 363 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1); 364 am335x_ehrpwm_freq(sc); 365 } 366 PWM_UNLOCK(sc); 367 368 return (0); 369 } 370 371 static int 372 am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS) 373 { 374 int error, i, clkdiv; 375 struct am335x_ehrpwm_softc *sc; 376 uint32_t reg; 377 378 sc = (struct am335x_ehrpwm_softc *)arg1; 379 380 PWM_LOCK(sc); 381 clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]; 382 PWM_UNLOCK(sc); 383 384 error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req); 385 if (error != 0 || req->newptr == NULL) 386 return (error); 387 388 PWM_LOCK(sc); 389 if (clkdiv != am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]) { 390 for (i = 0; i < nitems(am335x_ehrpwm_clkdiv); i++) 391 if (clkdiv >= am335x_ehrpwm_clkdiv[i]) 392 sc->sc_pwm_clkdiv = i; 393 394 reg = EPWM_READ2(sc, EPWM_TBCTL); 395 reg &= ~TBCTL_CLKDIV_MASK; 396 reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv); 397 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 398 am335x_ehrpwm_freq(sc); 399 } 400 PWM_UNLOCK(sc); 401 402 return (0); 403 } 404 405 static int 406 am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS) 407 { 408 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1; 409 int error; 410 uint32_t duty; 411 412 if (oidp == sc->sc_chanA_oid) 413 duty = sc->sc_pwm_dutyA; 414 else 415 duty = sc->sc_pwm_dutyB; 416 error = sysctl_handle_int(oidp, &duty, 0, req); 417 418 if (error != 0 || req->newptr == NULL) 419 return (error); 420 421 if (duty > sc->sc_pwm_period) { 422 device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n"); 423 return (EINVAL); 424 } 425 426 PWM_LOCK(sc); 427 if (oidp == sc->sc_chanA_oid) { 428 sc->sc_pwm_dutyA = duty; 429 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 430 } 431 else { 432 sc->sc_pwm_dutyB = duty; 433 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 434 } 435 PWM_UNLOCK(sc); 436 437 return (error); 438 } 439 440 static int 441 am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS) 442 { 443 struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1; 444 int error; 445 uint32_t period; 446 447 period = sc->sc_pwm_period; 448 error = sysctl_handle_int(oidp, &period, 0, req); 449 450 if (error != 0 || req->newptr == NULL) 451 return (error); 452 453 if (period < 1) 454 return (EINVAL); 455 456 if (period > USHRT_MAX) 457 period = USHRT_MAX; 458 459 PWM_LOCK(sc); 460 /* Reset the duty cycle settings. */ 461 sc->sc_pwm_dutyA = 0; 462 sc->sc_pwm_dutyB = 0; 463 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 464 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 465 /* Update the period settings. */ 466 sc->sc_pwm_period = period; 467 EPWM_WRITE2(sc, EPWM_TBPRD, period - 1); 468 am335x_ehrpwm_freq(sc); 469 PWM_UNLOCK(sc); 470 471 return (error); 472 } 473 474 static int 475 am335x_ehrpwm_channel_count(device_t dev, u_int *nchannel) 476 { 477 478 *nchannel = NUM_CHANNELS; 479 480 return (0); 481 } 482 483 static int 484 am335x_ehrpwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty) 485 { 486 struct am335x_ehrpwm_softc *sc; 487 bool status; 488 489 if (channel >= NUM_CHANNELS) 490 return (EINVAL); 491 492 sc = device_get_softc(dev); 493 494 PWM_LOCK(sc); 495 status = am335x_ehrpwm_cfg_period(sc, period); 496 if (status) 497 am335x_ehrpwm_cfg_duty(sc, channel, duty); 498 PWM_UNLOCK(sc); 499 500 return (status ? 0 : EINVAL); 501 } 502 503 static int 504 am335x_ehrpwm_channel_get_config(device_t dev, u_int channel, 505 u_int *period, u_int *duty) 506 { 507 struct am335x_ehrpwm_softc *sc; 508 509 if (channel >= NUM_CHANNELS) 510 return (EINVAL); 511 512 sc = device_get_softc(dev); 513 *period = sc->sc_period; 514 *duty = sc->sc_channels[channel].duty; 515 return (0); 516 } 517 518 static int 519 am335x_ehrpwm_channel_enable(device_t dev, u_int channel, bool enable) 520 { 521 struct am335x_ehrpwm_softc *sc; 522 523 if (channel >= NUM_CHANNELS) 524 return (EINVAL); 525 526 sc = device_get_softc(dev); 527 528 PWM_LOCK(sc); 529 am335x_ehrpwm_cfg_enable(sc, channel, enable); 530 PWM_UNLOCK(sc); 531 532 return (0); 533 } 534 535 static int 536 am335x_ehrpwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled) 537 { 538 struct am335x_ehrpwm_softc *sc; 539 540 if (channel >= NUM_CHANNELS) 541 return (EINVAL); 542 543 sc = device_get_softc(dev); 544 545 *enabled = sc->sc_channels[channel].enabled; 546 547 return (0); 548 } 549 550 static int 551 am335x_ehrpwm_probe(device_t dev) 552 { 553 554 if (!ofw_bus_status_okay(dev)) 555 return (ENXIO); 556 557 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 558 return (ENXIO); 559 560 device_set_desc(dev, "AM335x EHRPWM"); 561 562 return (BUS_PROBE_DEFAULT); 563 } 564 565 static int 566 am335x_ehrpwm_attach(device_t dev) 567 { 568 struct am335x_ehrpwm_softc *sc; 569 uint32_t reg; 570 struct sysctl_ctx_list *ctx; 571 struct sysctl_oid *tree; 572 573 sc = device_get_softc(dev); 574 sc->sc_dev = dev; 575 576 PWM_LOCK_INIT(sc); 577 578 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 579 &sc->sc_mem_rid, RF_ACTIVE); 580 if (sc->sc_mem_res == NULL) { 581 device_printf(dev, "cannot allocate memory resources\n"); 582 goto fail; 583 } 584 585 /* Init sysctl interface */ 586 ctx = device_get_sysctl_ctx(sc->sc_dev); 587 tree = device_get_sysctl_tree(sc->sc_dev); 588 589 sc->sc_clkdiv_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 590 "clkdiv", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 591 am335x_ehrpwm_sysctl_clkdiv, "I", "PWM clock prescaler"); 592 593 sc->sc_freq_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 594 "freq", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 595 am335x_ehrpwm_sysctl_freq, "I", "PWM frequency"); 596 597 sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 598 "period", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 599 am335x_ehrpwm_sysctl_period, "I", "PWM period"); 600 601 sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 602 "dutyA", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 603 am335x_ehrpwm_sysctl_duty, "I", "Channel A duty cycles"); 604 605 sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 606 "dutyB", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 607 am335x_ehrpwm_sysctl_duty, "I", "Channel B duty cycles"); 608 609 /* CONFIGURE EPWM1 */ 610 reg = EPWM_READ2(sc, EPWM_TBCTL); 611 reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK); 612 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 613 614 sc->sc_pwm_period = DEFAULT_PWM_PERIOD; 615 sc->sc_pwm_dutyA = 0; 616 sc->sc_pwm_dutyB = 0; 617 am335x_ehrpwm_freq(sc); 618 619 EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1); 620 EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA); 621 EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB); 622 623 EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR)); 624 EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR)); 625 626 /* START EPWM */ 627 reg &= ~TBCTL_CTRMODE_MASK; 628 reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN; 629 EPWM_WRITE2(sc, EPWM_TBCTL, reg); 630 631 EPWM_WRITE2(sc, EPWM_TZCTL, 0xf); 632 reg = EPWM_READ2(sc, EPWM_TZFLG); 633 634 if ((sc->sc_busdev = device_add_child(dev, "pwmbus", -1)) == NULL) { 635 device_printf(dev, "Cannot add child pwmbus\n"); 636 // This driver can still do things even without the bus child. 637 } 638 639 bus_generic_probe(dev); 640 return (bus_generic_attach(dev)); 641 fail: 642 PWM_LOCK_DESTROY(sc); 643 if (sc->sc_mem_res) 644 bus_release_resource(dev, SYS_RES_MEMORY, 645 sc->sc_mem_rid, sc->sc_mem_res); 646 647 return(ENXIO); 648 } 649 650 static int 651 am335x_ehrpwm_detach(device_t dev) 652 { 653 struct am335x_ehrpwm_softc *sc; 654 int error; 655 656 sc = device_get_softc(dev); 657 658 if ((error = bus_generic_detach(sc->sc_dev)) != 0) 659 return (error); 660 661 PWM_LOCK(sc); 662 663 if (sc->sc_busdev != NULL) 664 device_delete_child(dev, sc->sc_busdev); 665 666 if (sc->sc_mem_res) 667 bus_release_resource(dev, SYS_RES_MEMORY, 668 sc->sc_mem_rid, sc->sc_mem_res); 669 670 PWM_UNLOCK(sc); 671 672 PWM_LOCK_DESTROY(sc); 673 674 return (0); 675 } 676 677 static phandle_t 678 am335x_ehrpwm_get_node(device_t bus, device_t dev) 679 { 680 681 /* 682 * Share our controller node with our pwmbus child; it instantiates 683 * devices by walking the children contained within our node. 684 */ 685 return ofw_bus_get_node(bus); 686 } 687 688 static device_method_t am335x_ehrpwm_methods[] = { 689 DEVMETHOD(device_probe, am335x_ehrpwm_probe), 690 DEVMETHOD(device_attach, am335x_ehrpwm_attach), 691 DEVMETHOD(device_detach, am335x_ehrpwm_detach), 692 693 /* ofw_bus_if */ 694 DEVMETHOD(ofw_bus_get_node, am335x_ehrpwm_get_node), 695 696 /* pwm interface */ 697 DEVMETHOD(pwmbus_channel_count, am335x_ehrpwm_channel_count), 698 DEVMETHOD(pwmbus_channel_config, am335x_ehrpwm_channel_config), 699 DEVMETHOD(pwmbus_channel_get_config, am335x_ehrpwm_channel_get_config), 700 DEVMETHOD(pwmbus_channel_enable, am335x_ehrpwm_channel_enable), 701 DEVMETHOD(pwmbus_channel_is_enabled, am335x_ehrpwm_channel_is_enabled), 702 703 DEVMETHOD_END 704 }; 705 706 static driver_t am335x_ehrpwm_driver = { 707 "pwm", 708 am335x_ehrpwm_methods, 709 sizeof(struct am335x_ehrpwm_softc), 710 }; 711 712 static devclass_t am335x_ehrpwm_devclass; 713 714 DRIVER_MODULE(am335x_ehrpwm, am335x_pwmss, am335x_ehrpwm_driver, am335x_ehrpwm_devclass, 0, 0); 715 SIMPLEBUS_PNP_INFO(compat_data); 716 MODULE_VERSION(am335x_ehrpwm, 1); 717 MODULE_DEPEND(am335x_ehrpwm, am335x_pwmss, 1, 1, 1); 718 MODULE_DEPEND(am335x_ehrpwm, pwmbus, 1, 1, 1); 719