1 /*- 2 * Copyright (c) 2015 Ian lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * AM335x PPS driver using DMTimer capture. 29 * 30 * Note that this PPS driver does not use an interrupt. Instead it uses the 31 * hardware's ability to latch the timer's count register in response to a 32 * signal on an IO pin. Each of timers 4-7 have an associated pin, and this 33 * code allows any one of those to be used. 34 * 35 * The timecounter routines in kern_tc.c call the pps poll routine periodically 36 * to see if a new counter value has been latched. When a new value has been 37 * latched, the only processing done in the poll routine is to capture the 38 * current set of timecounter timehands (done with pps_capture()) and the 39 * latched value from the timer. The remaining work (done by pps_event() while 40 * holding a mutex) is scheduled to be done later in a non-interrupt context. 41 */ 42 43 #include <sys/cdefs.h> 44 __FBSDID("$FreeBSD$"); 45 46 #include "opt_platform.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/conf.h> 52 #include <sys/kernel.h> 53 #include <sys/lock.h> 54 #include <sys/module.h> 55 #include <sys/malloc.h> 56 #include <sys/mutex.h> 57 #include <sys/rman.h> 58 #include <sys/timepps.h> 59 #include <sys/timetc.h> 60 #include <machine/bus.h> 61 62 #include <dev/ofw/openfirm.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/extres/clk/clk.h> 66 67 #include <arm/ti/ti_sysc.h> 68 #include <arm/ti/ti_pinmux.h> 69 #include <arm/ti/am335x/am335x_scm_padconf.h> 70 71 #include "am335x_dmtreg.h" 72 73 #define PPS_CDEV_NAME "dmtpps" 74 75 struct dmtpps_softc { 76 device_t dev; 77 int mem_rid; 78 struct resource * mem_res; 79 int tmr_num; /* N from hwmod str "timerN" */ 80 char tmr_name[12]; /* "DMTimerN" */ 81 uint32_t tclr; /* Cached TCLR register. */ 82 struct timecounter tc; 83 int pps_curmode; /* Edge mode now set in hw. */ 84 struct cdev * pps_cdev; 85 struct pps_state pps_state; 86 struct mtx pps_mtx; 87 clk_t clk_fck; 88 uint64_t sysclk_freq; 89 }; 90 91 static int dmtpps_tmr_num; /* Set by probe() */ 92 93 /* List of compatible strings for FDT tree */ 94 static struct ofw_compat_data compat_data[] = { 95 {"ti,am335x-timer", 1}, 96 {"ti,am335x-timer-1ms", 1}, 97 {NULL, 0}, 98 }; 99 100 /* 101 * A table relating pad names to the hardware timer number they can be mux'd to. 102 */ 103 struct padinfo { 104 char * ballname; 105 int tmr_num; 106 }; 107 static struct padinfo dmtpps_padinfo[] = { 108 {"GPMC_ADVn_ALE", 4}, 109 {"I2C0_SDA", 4}, 110 {"MII1_TX_EN", 4}, 111 {"XDMA_EVENT_INTR0", 4}, 112 {"GPMC_BEn0_CLE", 5}, 113 {"MDC", 5}, 114 {"MMC0_DAT3", 5}, 115 {"UART1_RTSn", 5}, 116 {"GPMC_WEn", 6}, 117 {"MDIO", 6}, 118 {"MMC0_DAT2", 6}, 119 {"UART1_CTSn", 6}, 120 {"GPMC_OEn_REn", 7}, 121 {"I2C0_SCL", 7}, 122 {"UART0_CTSn", 7}, 123 {"XDMA_EVENT_INTR1", 7}, 124 {NULL, 0} 125 }; 126 127 /* 128 * This is either brilliantly user-friendly, or utterly lame... 129 * 130 * The am335x chip is used on the popular Beaglebone boards. Those boards have 131 * pins for all four capture-capable timers available on the P8 header. Allow 132 * users to configure the input pin by giving the name of the header pin. 133 */ 134 struct nicknames { 135 const char * nick; 136 const char * name; 137 }; 138 static struct nicknames dmtpps_pin_nicks[] = { 139 {"P8-7", "GPMC_ADVn_ALE"}, 140 {"P8-9", "GPMC_BEn0_CLE"}, 141 {"P8-10", "GPMC_WEn"}, 142 {"P8-8", "GPMC_OEn_REn",}, 143 {NULL, NULL} 144 }; 145 146 #define DMTIMER_READ4(sc, reg) bus_read_4((sc)->mem_res, (reg)) 147 #define DMTIMER_WRITE4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val)) 148 149 /* 150 * Translate a short friendly case-insensitive name to its canonical name. 151 */ 152 static const char * 153 dmtpps_translate_nickname(const char *nick) 154 { 155 struct nicknames *nn; 156 157 for (nn = dmtpps_pin_nicks; nn->nick != NULL; nn++) 158 if (strcasecmp(nick, nn->nick) == 0) 159 return nn->name; 160 return (nick); 161 } 162 163 /* 164 * See if our tunable is set to the name of the input pin. If not, that's NOT 165 * an error, return 0. If so, try to configure that pin as a timer capture 166 * input pin, and if that works, then we have our timer unit number and if it 167 * fails that IS an error, return -1. 168 */ 169 static int 170 dmtpps_find_tmr_num_by_tunable(void) 171 { 172 struct padinfo *pi; 173 char iname[20]; 174 char muxmode[12]; 175 const char * ballname; 176 int err; 177 178 if (!TUNABLE_STR_FETCH("hw.am335x_dmtpps.input", iname, sizeof(iname))) 179 return (0); 180 ballname = dmtpps_translate_nickname(iname); 181 for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) { 182 if (strcmp(ballname, pi->ballname) != 0) 183 continue; 184 snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num); 185 err = ti_pinmux_padconf_set(pi->ballname, muxmode, 186 PADCONF_INPUT); 187 if (err != 0) { 188 printf("am335x_dmtpps: unable to configure capture pin " 189 "for %s to input mode\n", muxmode); 190 return (-1); 191 } else if (bootverbose) { 192 printf("am335x_dmtpps: configured pin %s as input " 193 "for %s\n", iname, muxmode); 194 } 195 return (pi->tmr_num); 196 } 197 198 /* Invalid name in the tunable, that's an error. */ 199 printf("am335x_dmtpps: unknown pin name '%s'\n", iname); 200 return (-1); 201 } 202 203 /* 204 * Ask the pinmux driver whether any pin has been configured as a TIMER4..TIMER7 205 * input pin. If so, return the timer number, if not return 0. 206 */ 207 static int 208 dmtpps_find_tmr_num_by_padconf(void) 209 { 210 int err; 211 unsigned int padstate; 212 const char * padmux; 213 struct padinfo *pi; 214 char muxmode[12]; 215 216 for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) { 217 err = ti_pinmux_padconf_get(pi->ballname, &padmux, &padstate); 218 snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num); 219 if (err == 0 && (padstate & RXACTIVE) != 0 && 220 strcmp(muxmode, padmux) == 0) 221 return (pi->tmr_num); 222 } 223 /* Nothing found, not an error. */ 224 return (0); 225 } 226 227 /* 228 * Figure out which hardware timer number to use based on input pin 229 * configuration. This is done just once, the first time probe() runs. 230 */ 231 static int 232 dmtpps_find_tmr_num(void) 233 { 234 int tmr_num; 235 236 if ((tmr_num = dmtpps_find_tmr_num_by_tunable()) == 0) 237 tmr_num = dmtpps_find_tmr_num_by_padconf(); 238 239 if (tmr_num <= 0) { 240 printf("am335x_dmtpps: PPS driver not enabled: unable to find " 241 "or configure a capture input pin\n"); 242 tmr_num = -1; /* Must return non-zero to prevent re-probing. */ 243 } 244 return (tmr_num); 245 } 246 247 static void 248 dmtpps_set_hw_capture(struct dmtpps_softc *sc, bool force_off) 249 { 250 int newmode; 251 252 if (force_off) 253 newmode = 0; 254 else 255 newmode = sc->pps_state.ppsparam.mode & PPS_CAPTUREASSERT; 256 257 if (newmode == sc->pps_curmode) 258 return; 259 sc->pps_curmode = newmode; 260 261 if (newmode == PPS_CAPTUREASSERT) 262 sc->tclr |= DMT_TCLR_CAPTRAN_LOHI; 263 else 264 sc->tclr &= ~DMT_TCLR_CAPTRAN_MASK; 265 DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); 266 } 267 268 static unsigned 269 dmtpps_get_timecount(struct timecounter *tc) 270 { 271 struct dmtpps_softc *sc; 272 273 sc = tc->tc_priv; 274 275 return (DMTIMER_READ4(sc, DMT_TCRR)); 276 } 277 278 static void 279 dmtpps_poll(struct timecounter *tc) 280 { 281 struct dmtpps_softc *sc; 282 283 sc = tc->tc_priv; 284 285 /* 286 * If a new value has been latched we've got a PPS event. Capture the 287 * timecounter data, then override the capcount field (pps_capture() 288 * populates it from the current DMT_TCRR register) with the latched 289 * value from the TCAR1 register. 290 * 291 * Note that we don't have the TCAR interrupt enabled, but the hardware 292 * still provides the status bits in the "RAW" status register even when 293 * they're masked from generating an irq. However, when clearing the 294 * TCAR status to re-arm the capture for the next second, we have to 295 * write to the IRQ status register, not the RAW register. Quirky. 296 * 297 * We do not need to hold a lock while capturing the pps data, because 298 * it is captured into an area of the pps_state struct which is read 299 * only by pps_event(). We do need to hold a lock while calling 300 * pps_event(), because it manipulates data which is also accessed from 301 * the ioctl(2) context by userland processes. 302 */ 303 if (DMTIMER_READ4(sc, DMT_IRQSTATUS_RAW) & DMT_IRQ_TCAR) { 304 pps_capture(&sc->pps_state); 305 sc->pps_state.capcount = DMTIMER_READ4(sc, DMT_TCAR1); 306 DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR); 307 308 mtx_lock_spin(&sc->pps_mtx); 309 pps_event(&sc->pps_state, PPS_CAPTUREASSERT); 310 mtx_unlock_spin(&sc->pps_mtx); 311 } 312 } 313 314 static int 315 dmtpps_open(struct cdev *dev, int flags, int fmt, 316 struct thread *td) 317 { 318 struct dmtpps_softc *sc; 319 320 sc = dev->si_drv1; 321 322 /* 323 * Begin polling for pps and enable capture in the hardware whenever the 324 * device is open. Doing this stuff again is harmless if this isn't the 325 * first open. 326 */ 327 sc->tc.tc_poll_pps = dmtpps_poll; 328 dmtpps_set_hw_capture(sc, false); 329 330 return 0; 331 } 332 333 static int 334 dmtpps_close(struct cdev *dev, int flags, int fmt, 335 struct thread *td) 336 { 337 struct dmtpps_softc *sc; 338 339 sc = dev->si_drv1; 340 341 /* 342 * Stop polling and disable capture on last close. Use the force-off 343 * flag to override the configured mode and turn off the hardware. 344 */ 345 sc->tc.tc_poll_pps = NULL; 346 dmtpps_set_hw_capture(sc, true); 347 348 return 0; 349 } 350 351 static int 352 dmtpps_ioctl(struct cdev *dev, u_long cmd, caddr_t data, 353 int flags, struct thread *td) 354 { 355 struct dmtpps_softc *sc; 356 int err; 357 358 sc = dev->si_drv1; 359 360 /* Let the kernel do the heavy lifting for ioctl. */ 361 mtx_lock_spin(&sc->pps_mtx); 362 err = pps_ioctl(cmd, data, &sc->pps_state); 363 mtx_unlock_spin(&sc->pps_mtx); 364 if (err != 0) 365 return (err); 366 367 /* 368 * The capture mode could have changed, set the hardware to whatever 369 * mode is now current. Effectively a no-op if nothing changed. 370 */ 371 dmtpps_set_hw_capture(sc, false); 372 373 return (err); 374 } 375 376 static struct cdevsw dmtpps_cdevsw = { 377 .d_version = D_VERSION, 378 .d_open = dmtpps_open, 379 .d_close = dmtpps_close, 380 .d_ioctl = dmtpps_ioctl, 381 .d_name = PPS_CDEV_NAME, 382 }; 383 384 static int 385 dmtpps_probe(device_t dev) 386 { 387 char strbuf[64]; 388 int tmr_num; 389 uint64_t rev_address; 390 391 if (!ofw_bus_status_okay(dev)) 392 return (ENXIO); 393 394 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 395 return (ENXIO); 396 397 /* 398 * If we haven't chosen which hardware timer to use yet, go do that now. 399 * We need to know that to decide whether to return success for this 400 * hardware timer instance or not. 401 */ 402 if (dmtpps_tmr_num == 0) 403 dmtpps_tmr_num = dmtpps_find_tmr_num(); 404 405 /* 406 * Figure out which hardware timer is being probed and see if it matches 407 * the configured timer number determined earlier. 408 */ 409 rev_address = ti_sysc_get_rev_address(device_get_parent(dev)); 410 switch (rev_address) { 411 case DMTIMER1_1MS_REV: 412 tmr_num = 1; 413 break; 414 case DMTIMER2_REV: 415 tmr_num = 2; 416 break; 417 case DMTIMER3_REV: 418 tmr_num = 3; 419 break; 420 case DMTIMER4_REV: 421 tmr_num = 4; 422 break; 423 case DMTIMER5_REV: 424 tmr_num = 5; 425 break; 426 case DMTIMER6_REV: 427 tmr_num = 6; 428 break; 429 case DMTIMER7_REV: 430 tmr_num = 7; 431 break; 432 default: 433 return (ENXIO); 434 } 435 436 if (dmtpps_tmr_num != tmr_num) 437 return (ENXIO); 438 439 snprintf(strbuf, sizeof(strbuf), "AM335x PPS-Capture DMTimer%d", 440 tmr_num); 441 device_set_desc_copy(dev, strbuf); 442 443 return(BUS_PROBE_DEFAULT); 444 } 445 446 static int 447 dmtpps_attach(device_t dev) 448 { 449 struct dmtpps_softc *sc; 450 struct make_dev_args mda; 451 int err; 452 clk_t sys_clkin; 453 uint64_t rev_address; 454 455 sc = device_get_softc(dev); 456 sc->dev = dev; 457 458 /* Figure out which hardware timer this is and set the name string. */ 459 rev_address = ti_sysc_get_rev_address(device_get_parent(dev)); 460 switch (rev_address) { 461 case DMTIMER1_1MS_REV: 462 sc->tmr_num = 1; 463 break; 464 case DMTIMER2_REV: 465 sc->tmr_num = 2; 466 break; 467 case DMTIMER3_REV: 468 sc->tmr_num = 3; 469 break; 470 case DMTIMER4_REV: 471 sc->tmr_num = 4; 472 break; 473 case DMTIMER5_REV: 474 sc->tmr_num = 5; 475 break; 476 case DMTIMER6_REV: 477 sc->tmr_num = 6; 478 break; 479 case DMTIMER7_REV: 480 sc->tmr_num = 7; 481 break; 482 } 483 snprintf(sc->tmr_name, sizeof(sc->tmr_name), "DMTimer%d", sc->tmr_num); 484 485 /* expect one clock */ 486 err = clk_get_by_ofw_index(dev, 0, 0, &sc->clk_fck); 487 if (err != 0) { 488 device_printf(dev, "Cant find clock index 0. err: %d\n", err); 489 return (ENXIO); 490 } 491 492 err = clk_get_by_name(dev, "sys_clkin_ck@40", &sys_clkin); 493 if (err != 0) { 494 device_printf(dev, "Cant find sys_clkin_ck@40 err: %d\n", err); 495 return (ENXIO); 496 } 497 498 /* Select M_OSC as DPLL parent */ 499 err = clk_set_parent_by_clk(sc->clk_fck, sys_clkin); 500 if (err != 0) { 501 device_printf(dev, "Cant set mux to CLK_M_OSC\n"); 502 return (ENXIO); 503 } 504 505 /* Enable clocks and power on the device. */ 506 err = ti_sysc_clock_enable(device_get_parent(dev)); 507 if (err != 0) { 508 device_printf(dev, "Cant enable sysc clkctrl, err %d\n", err); 509 return (ENXIO); 510 } 511 512 /* Get the base clock frequency. */ 513 err = clk_get_freq(sc->clk_fck, &sc->sysclk_freq); 514 if (err != 0) { 515 device_printf(dev, "Cant get sysclk frequency, err %d\n", err); 516 return (ENXIO); 517 } 518 /* Request the memory resources. */ 519 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 520 &sc->mem_rid, RF_ACTIVE); 521 if (sc->mem_res == NULL) { 522 return (ENXIO); 523 } 524 525 /* 526 * Configure the timer pulse/capture pin to input/capture mode. This is 527 * required in addition to configuring the pin as input with the pinmux 528 * controller (which was done via fdt data or tunable at probe time). 529 */ 530 sc->tclr = DMT_TCLR_GPO_CFG; 531 DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); 532 533 /* Set up timecounter hardware, start it. */ 534 DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET); 535 while (DMTIMER_READ4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET) 536 continue; 537 538 sc->tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD; 539 DMTIMER_WRITE4(sc, DMT_TLDR, 0); 540 DMTIMER_WRITE4(sc, DMT_TCRR, 0); 541 DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); 542 543 /* Register the timecounter. */ 544 sc->tc.tc_name = sc->tmr_name; 545 sc->tc.tc_get_timecount = dmtpps_get_timecount; 546 sc->tc.tc_counter_mask = ~0u; 547 sc->tc.tc_frequency = sc->sysclk_freq; 548 sc->tc.tc_quality = 1000; 549 sc->tc.tc_priv = sc; 550 551 tc_init(&sc->tc); 552 553 /* 554 * Indicate our PPS capabilities. Have the kernel init its part of the 555 * pps_state struct and add its capabilities. 556 * 557 * While the hardware has a mode to capture each edge, it's not clear we 558 * can use it that way, because there's only a single interrupt/status 559 * bit to say something was captured, but not which edge it was. For 560 * now, just say we can only capture assert events (the positive-going 561 * edge of the pulse). 562 */ 563 mtx_init(&sc->pps_mtx, "dmtpps", NULL, MTX_SPIN); 564 sc->pps_state.flags = PPSFLAG_MTX_SPIN; 565 sc->pps_state.ppscap = PPS_CAPTUREASSERT; 566 sc->pps_state.driver_abi = PPS_ABI_VERSION; 567 sc->pps_state.driver_mtx = &sc->pps_mtx; 568 pps_init_abi(&sc->pps_state); 569 570 /* Create the PPS cdev. */ 571 make_dev_args_init(&mda); 572 mda.mda_flags = MAKEDEV_WAITOK; 573 mda.mda_devsw = &dmtpps_cdevsw; 574 mda.mda_cr = NULL; 575 mda.mda_uid = UID_ROOT; 576 mda.mda_gid = GID_WHEEL; 577 mda.mda_mode = 0600; 578 mda.mda_unit = device_get_unit(dev); 579 mda.mda_si_drv1 = sc; 580 if ((err = make_dev_s(&mda, &sc->pps_cdev, PPS_CDEV_NAME)) != 0) { 581 device_printf(dev, "Failed to create cdev %s\n", PPS_CDEV_NAME); 582 return (err); 583 } 584 585 if (bootverbose) 586 device_printf(sc->dev, "Using %s for PPS device /dev/%s\n", 587 sc->tmr_name, PPS_CDEV_NAME); 588 589 return (0); 590 } 591 592 static int 593 dmtpps_detach(device_t dev) 594 { 595 596 /* 597 * There is no way to remove a timecounter once it has been registered, 598 * even if it's not in use, so we can never detach. If we were 599 * dynamically loaded as a module this will prevent unloading. 600 */ 601 return (EBUSY); 602 } 603 604 static device_method_t dmtpps_methods[] = { 605 DEVMETHOD(device_probe, dmtpps_probe), 606 DEVMETHOD(device_attach, dmtpps_attach), 607 DEVMETHOD(device_detach, dmtpps_detach), 608 { 0, 0 } 609 }; 610 611 static driver_t dmtpps_driver = { 612 "am335x_dmtpps", 613 dmtpps_methods, 614 sizeof(struct dmtpps_softc), 615 }; 616 617 static devclass_t dmtpps_devclass; 618 619 DRIVER_MODULE(am335x_dmtpps, simplebus, dmtpps_driver, dmtpps_devclass, 0, 0); 620 SIMPLEBUS_PNP_INFO(compat_data); 621 MODULE_DEPEND(am335x_dmtpps, ti_sysc, 1, 1, 1); 622