xref: /freebsd/sys/arm/ti/am335x/am335x_dmtimer.c (revision 98e0ffaefb0f241cda3a72395d3be04192ae0d47)
1 /*-
2  * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
37 #include <sys/rman.h>
38 #include <sys/taskqueue.h>
39 #include <sys/timeet.h>
40 #include <sys/timepps.h>
41 #include <sys/timetc.h>
42 #include <sys/watchdog.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/intr.h>
46 
47 #include "opt_ntp.h"
48 
49 #include <dev/fdt/fdt_common.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 
54 #include <machine/bus.h>
55 
56 #include <arm/ti/ti_prcm.h>
57 #include <arm/ti/ti_hwmods.h>
58 #include <arm/ti/ti_pinmux.h>
59 
60 #define	AM335X_NUM_TIMERS	8
61 
62 #define	DMT_TIDR		0x00		/* Identification Register */
63 #define	DMT_TIOCP_CFG		0x10		/* OCP Configuration Reg */
64 #define	  DMT_TIOCP_RESET	  (1 << 0)	/* TIOCP perform soft reset */
65 #define	DMT_IQR_EOI		0x20		/* IRQ End-Of-Interrupt Reg */
66 #define	DMT_IRQSTATUS_RAW	0x24		/* IRQSTATUS Raw Reg */
67 #define	DMT_IRQSTATUS		0x28		/* IRQSTATUS Reg */
68 #define	DMT_IRQENABLE_SET	0x2c		/* IRQSTATUS Set Reg */
69 #define	DMT_IRQENABLE_CLR	0x30		/* IRQSTATUS Clear Reg */
70 #define	DMT_IRQWAKEEN		0x34		/* IRQ Wakeup Enable Reg */
71 #define	  DMT_IRQ_MAT		  (1 << 0)	/* IRQ: Match */
72 #define	  DMT_IRQ_OVF		  (1 << 1)	/* IRQ: Overflow */
73 #define	  DMT_IRQ_TCAR		  (1 << 2)	/* IRQ: Capture */
74 #define	  DMT_IRQ_MASK		  (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT)
75 #define	DMT_TCLR		0x38		/* Control Register */
76 #define	  DMT_TCLR_START	  (1 << 0)	/* Start timer */
77 #define	  DMT_TCLR_AUTOLOAD	  (1 << 1)	/* Auto-reload on overflow */
78 #define	  DMT_TCLR_PRES_MASK	  (7 << 2)	/* Prescaler mask */
79 #define	  DMT_TCLR_PRES_ENABLE	  (1 << 5)	/* Prescaler enable */
80 #define	  DMT_TCLR_COMP_ENABLE	  (1 << 6)	/* Compare enable */
81 #define	  DMT_TCLR_PWM_HIGH	  (1 << 7)	/* PWM default output high */
82 #define	  DMT_TCLR_CAPTRAN_MASK	  (3 << 8)	/* Capture transition mask */
83 #define	  DMT_TCLR_CAPTRAN_NONE	  (0 << 8)	/* Capture: none */
84 #define	  DMT_TCLR_CAPTRAN_LOHI	  (1 << 8)	/* Capture lo->hi transition */
85 #define	  DMT_TCLR_CAPTRAN_HILO	  (2 << 8)	/* Capture hi->lo transition */
86 #define	  DMT_TCLR_CAPTRAN_BOTH	  (3 << 8)	/* Capture both transitions */
87 #define	  DMT_TCLR_TRGMODE_MASK	  (3 << 10)	/* Trigger output mode mask */
88 #define	  DMT_TCLR_TRGMODE_NONE	  (0 << 10)	/* Trigger off */
89 #define	  DMT_TCLR_TRGMODE_OVFL	  (1 << 10)	/* Trigger on overflow */
90 #define	  DMT_TCLR_TRGMODE_BOTH	  (2 << 10)	/* Trigger on match + ovflow */
91 #define	  DMT_TCLR_PWM_PTOGGLE	  (1 << 12)	/* PWM toggles */
92 #define	  DMT_TCLR_CAP_MODE_2ND	  (1 << 13)	/* Capture second event mode */
93 #define	  DMT_TCLR_GPO_CFG	  (1 << 14)	/* (no descr in datasheet) */
94 #define	DMT_TCRR		0x3C		/* Counter Register */
95 #define	DMT_TLDR		0x40		/* Load Reg */
96 #define	DMT_TTGR		0x44		/* Trigger Reg */
97 #define	DMT_TWPS		0x48		/* Write Posted Status Reg */
98 #define	DMT_TMAR		0x4C		/* Match Reg */
99 #define	DMT_TCAR1		0x50		/* Capture Reg */
100 #define	DMT_TSICR		0x54		/* Synchr. Interface Ctrl Reg */
101 #define	  DMT_TSICR_RESET	  (1 << 1)	/* TSICR perform soft reset */
102 #define	DMT_TCAR2		0x48		/* Capture Reg */
103 
104 /*
105  * Use timer 2 for the eventtimer.  When PPS support is not compiled in, there's
106  * no need to use a timer that has an associated capture-input pin, so use timer
107  * 3 for timecounter.  When PPS is compiled in we ignore the default and use
108  * whichever of timers 4-7 have the capture pin configured.
109  */
110 #define	DEFAULT_ET_TIMER	2
111 #define	DEFAULT_TC_TIMER	3
112 
113 #define	DMTIMER_READ4(sc, reg)	(bus_read_4((sc)->tmr_mem_res, (reg)))
114 #define	DMTIMER_WRITE4(sc, reg, val)	(bus_write_4((sc)->tmr_mem_res, (reg), (val)))
115 
116 struct am335x_dmtimer_softc {
117 	device_t		dev;
118 	int			tmr_mem_rid;
119 	struct resource *	tmr_mem_res;
120 	int			tmr_irq_rid;
121 	struct resource *	tmr_irq_res;
122 	void			*tmr_irq_handler;
123 	uint32_t		sysclk_freq;
124 	uint32_t		tclr;		/* Cached TCLR register. */
125 	int			pps_curmode;	/* Edge mode now set in hw. */
126 	struct task 		pps_task;	/* For pps_event handling. */
127 	struct cdev *		pps_cdev;
128 	struct pps_state 	pps;
129 
130 	union {
131 		struct timecounter tc;
132 		struct eventtimer et;
133 	} func;
134 };
135 
136 static struct am335x_dmtimer_softc *am335x_dmtimer_et_sc = NULL;
137 static struct am335x_dmtimer_softc *am335x_dmtimer_tc_sc = NULL;
138 
139 
140 #ifdef PPS_SYNC
141 /* -1 - not detected, 0 - not found, > 0 - timerX module */
142 static int am335x_dmtimer_pps_module = -1;
143 static const char *am335x_dmtimer_pps_hwmod = NULL;
144 #endif
145 
146 /*
147  * PPS driver routines, included when the kernel is built with option PPS_SYNC.
148  *
149  * Note that this PPS driver does not use an interrupt.  Instead it uses the
150  * hardware's ability to latch the timer's count register in response to a
151  * signal on an IO pin.  Each of timers 4-7 have an associated pin, and this
152  * code allows any one of those to be used.
153  *
154  * The timecounter routines in kern_tc.c call the pps poll routine periodically
155  * to see if a new counter value has been latched.  When a new value has been
156  * latched, the only processing done in the poll routine is to capture the
157  * current set of timecounter timehands (done with pps_capture()) and the
158  * latched value from the timer.  The remaining work (done by pps_event()) is
159  * scheduled to be done later in a non-interrupt context.
160  */
161 #ifdef PPS_SYNC
162 
163 #define	PPS_CDEV_NAME	"dmtpps"
164 
165 static void
166 am335x_dmtimer_set_capture_mode(struct am335x_dmtimer_softc *sc, bool force_off)
167 {
168 	int newmode;
169 
170 	if (force_off)
171 		newmode = 0;
172 	else
173 		newmode = sc->pps.ppsparam.mode & PPS_CAPTUREBOTH;
174 
175 	if (newmode == sc->pps_curmode)
176 		return;
177 
178 	sc->pps_curmode = newmode;
179 	sc->tclr &= ~DMT_TCLR_CAPTRAN_MASK;
180 	switch (newmode) {
181 	case PPS_CAPTUREASSERT:
182 		sc->tclr |= DMT_TCLR_CAPTRAN_LOHI;
183 		break;
184 	case PPS_CAPTURECLEAR:
185 		sc->tclr |= DMT_TCLR_CAPTRAN_HILO;
186 		break;
187 	default:
188 		/* It can't be BOTH, so it's disabled. */
189 		break;
190 	}
191 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
192 }
193 
194 static void
195 am335x_dmtimer_tc_poll_pps(struct timecounter *tc)
196 {
197 	struct am335x_dmtimer_softc *sc;
198 
199 	sc = tc->tc_priv;
200 
201 	/*
202 	 * Note that we don't have the TCAR interrupt enabled, but the hardware
203 	 * still provides the status bits in the "RAW" status register even when
204 	 * they're masked from generating an irq.  However, when clearing the
205 	 * TCAR status to re-arm the capture for the next second, we have to
206 	 * write to the IRQ status register, not the RAW register.  Quirky.
207 	 */
208 	if (DMTIMER_READ4(sc, DMT_IRQSTATUS_RAW) & DMT_IRQ_TCAR) {
209 		pps_capture(&sc->pps);
210 		sc->pps.capcount = DMTIMER_READ4(sc, DMT_TCAR1);
211 		DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR);
212 		taskqueue_enqueue_fast(taskqueue_fast, &sc->pps_task);
213 	}
214 }
215 
216 static void
217 am335x_dmtimer_process_pps_event(void *arg, int pending)
218 {
219 	struct am335x_dmtimer_softc *sc;
220 
221 	sc = arg;
222 
223 	/* This is the task function that gets enqueued by poll_pps.  Once the
224 	 * time has been captured in the hw interrupt context, the remaining
225 	 * (more expensive) work to process the event is done later in a
226 	 * non-fast-interrupt context.
227 	 *
228 	 * We only support capture of the rising or falling edge, not both at
229 	 * once; tell the kernel to process whichever mode is currently active.
230 	 */
231 	pps_event(&sc->pps, sc->pps.ppsparam.mode & PPS_CAPTUREBOTH);
232 }
233 
234 static int
235 am335x_dmtimer_pps_open(struct cdev *dev, int flags, int fmt,
236     struct thread *td)
237 {
238 	struct am335x_dmtimer_softc *sc;
239 
240 	sc = dev->si_drv1;
241 
242 	/* Enable capture on open.  Harmless if already open. */
243 	am335x_dmtimer_set_capture_mode(sc, 0);
244 
245 	return 0;
246 }
247 
248 static	int
249 am335x_dmtimer_pps_close(struct cdev *dev, int flags, int fmt,
250     struct thread *td)
251 {
252 	struct am335x_dmtimer_softc *sc;
253 
254 	sc = dev->si_drv1;
255 
256 	/*
257 	 * Disable capture on last close.  Use the force-off flag to override
258 	 * the configured mode and turn off the hardware capture.
259 	 */
260 	am335x_dmtimer_set_capture_mode(sc, 1);
261 
262 	return 0;
263 }
264 
265 static int
266 am335x_dmtimer_pps_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
267     int flags, struct thread *td)
268 {
269 	struct am335x_dmtimer_softc *sc;
270 	int err;
271 
272 	sc = dev->si_drv1;
273 
274 	/*
275 	 * The hardware has a "capture both edges" mode, but we can't do
276 	 * anything useful with it in terms of PPS capture, so don't even try.
277 	 */
278 	if ((sc->pps.ppsparam.mode & PPS_CAPTUREBOTH) == PPS_CAPTUREBOTH)
279 		return (EINVAL);
280 
281 	/* Let the kernel do the heavy lifting for ioctl. */
282 	err = pps_ioctl(cmd, data, &sc->pps);
283 	if (err != 0)
284 		return (err);
285 
286 	/*
287 	 * The capture mode could have changed, set the hardware to whatever
288 	 * mode is now current.  Effectively a no-op if nothing changed.
289 	 */
290 	am335x_dmtimer_set_capture_mode(sc, 0);
291 
292 	return (err);
293 }
294 
295 static struct cdevsw am335x_dmtimer_pps_cdevsw = {
296 	.d_version =    D_VERSION,
297 	.d_open =       am335x_dmtimer_pps_open,
298 	.d_close =      am335x_dmtimer_pps_close,
299 	.d_ioctl =      am335x_dmtimer_pps_ioctl,
300 	.d_name =       PPS_CDEV_NAME,
301 };
302 
303 static void
304 am335x_dmtimer_pps_find()
305 {
306 	int i;
307 	unsigned int padstate;
308 	const char * padmux;
309 	struct padinfo {
310 		char * ballname;
311 		const char * muxname;
312 		int    timer_num;
313 	} padinfo[] = {
314 		{"GPMC_ADVn_ALE", "timer4", 4},
315 		{"GPMC_BEn0_CLE", "timer5", 5},
316 		{"GPMC_WEn",      "timer6", 6},
317 		{"GPMC_OEn_REn",  "timer7", 7},
318 	};
319 
320 	/*
321 	 * Figure out which pin the user has set up for pps.  We'll use the
322 	 * first timer that has an external caputure pin configured as input.
323 	 *
324 	 * XXX The hieroglyphic "(padstate & (0x01 << 5)))" checks that the pin
325 	 * is configured for input.  The right symbolic values aren't exported
326 	 * yet from ti_scm.h.
327 	 */
328 	am335x_dmtimer_pps_module = 0;
329 	for (i = 0; i < nitems(padinfo) && am335x_dmtimer_pps_module == 0; ++i) {
330 		if (ti_pinmux_padconf_get(padinfo[i].ballname, &padmux,
331 		    &padstate) == 0) {
332 			if (strcasecmp(padinfo[i].muxname, padmux) == 0 &&
333 			    (padstate & (0x01 << 5))) {
334 				am335x_dmtimer_pps_module = padinfo[i].timer_num;
335 				am335x_dmtimer_pps_hwmod = padinfo[i].muxname;
336 			}
337 		}
338 	}
339 
340 
341 	if (am335x_dmtimer_pps_module == 0) {
342 		printf("am335x_dmtimer: No DMTimer found with capture pin "
343 		    "configured as input; PPS driver disabled.\n");
344 	}
345 }
346 
347 /*
348  * Set up the PPS cdev and the the kernel timepps stuff.
349  *
350  * Note that this routine cannot touch the hardware, because bus space resources
351  * are not fully set up yet when this is called.
352  */
353 static void
354 am335x_dmtimer_pps_init(device_t dev, struct am335x_dmtimer_softc *sc)
355 {
356 	int unit;
357 
358 	if (am335x_dmtimer_pps_module == -1)
359 		am335x_dmtimer_pps_find();
360 
361 	/* No PPS input */
362 	if (am335x_dmtimer_pps_module == 0)
363 		return;
364 
365 	/* Not PPS-enabled input */
366 	if ((am335x_dmtimer_pps_module > 0) &&
367 	    (!ti_hwmods_contains(dev, am335x_dmtimer_pps_hwmod)))
368 	 	return;
369 
370 	/*
371 	 * Indicate our capabilities (pretty much just capture of either edge).
372 	 * Have the kernel init its part of the pps_state struct and add its
373 	 * capabilities.
374 	 */
375 	sc->pps.ppscap = PPS_CAPTUREBOTH;
376 	pps_init(&sc->pps);
377 
378 	/*
379 	 * Set up to capture the PPS via timecounter polling, and init the task
380 	 * that does deferred pps_event() processing after capture.
381 	 */
382 	sc->func.tc.tc_poll_pps = am335x_dmtimer_tc_poll_pps;
383 	TASK_INIT(&sc->pps_task, 0, am335x_dmtimer_process_pps_event, sc);
384 
385 	/* Create the PPS cdev.  */
386 	sc->pps_cdev = make_dev(&am335x_dmtimer_pps_cdevsw, unit,
387 	    UID_ROOT, GID_WHEEL, 0600, PPS_CDEV_NAME);
388 	sc->pps_cdev->si_drv1 = sc;
389 	unit = device_get_unit(sc->pps_cdev);
390 
391 	device_printf(dev, "Using DMTimer%d for PPS device /dev/%s%d\n",
392 	    am335x_dmtimer_pps_module, PPS_CDEV_NAME, unit);
393 }
394 
395 #endif
396 
397 /*
398  * End of PPS driver code.
399  */
400 
401 static unsigned
402 am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
403 {
404 	struct am335x_dmtimer_softc *sc;
405 
406 	sc = tc->tc_priv;
407 
408 	return (DMTIMER_READ4(sc, DMT_TCRR));
409 }
410 
411 static int
412 am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
413 {
414 	struct am335x_dmtimer_softc *sc;
415 	uint32_t initial_count, reload_count;
416 
417 	sc = et->et_priv;
418 
419 	/*
420 	 * Stop the timer before changing it.  This routine will often be called
421 	 * while the timer is still running, to either lengthen or shorten the
422 	 * current event time.  We need to ensure the timer doesn't expire while
423 	 * we're working with it.
424 	 *
425 	 * Also clear any pending interrupt status, because it's at least
426 	 * theoretically possible that we're running in a primary interrupt
427 	 * context now, and a timer interrupt could be pending even before we
428 	 * stopped the timer.  The more likely case is that we're being called
429 	 * from the et_event_cb() routine dispatched from our own handler, but
430 	 * it's not clear to me that that's the only case possible.
431 	 */
432 	sc->tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
433 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
434 	DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
435 
436 	if (period != 0) {
437 		reload_count = ((uint32_t)et->et_frequency * period) >> 32;
438 		sc->tclr |= DMT_TCLR_AUTOLOAD;
439 	} else {
440 		reload_count = 0;
441 	}
442 
443 	if (first != 0)
444 		initial_count = ((uint32_t)et->et_frequency * first) >> 32;
445 	else
446 		initial_count = reload_count;
447 
448 	/*
449 	 * Set auto-reload and current-count values.  This timer hardware counts
450 	 * up from the initial/reload value and interrupts on the zero rollover.
451 	 */
452 	DMTIMER_WRITE4(sc, DMT_TLDR, 0xFFFFFFFF - reload_count);
453 	DMTIMER_WRITE4(sc, DMT_TCRR, 0xFFFFFFFF - initial_count);
454 
455 	/* Enable overflow interrupt, and start the timer. */
456 	DMTIMER_WRITE4(sc, DMT_IRQENABLE_SET, DMT_IRQ_OVF);
457 	sc->tclr |= DMT_TCLR_START;
458 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
459 
460 	return (0);
461 }
462 
463 static int
464 am335x_dmtimer_stop(struct eventtimer *et)
465 {
466 	struct am335x_dmtimer_softc *sc;
467 
468 	sc = et->et_priv;
469 
470 	/* Stop timer, disable and clear interrupt. */
471 	sc->tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
472 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
473 	DMTIMER_WRITE4(sc, DMT_IRQENABLE_CLR, DMT_IRQ_OVF);
474 	DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
475 	return (0);
476 }
477 
478 static int
479 am335x_dmtimer_intr(void *arg)
480 {
481 	struct am335x_dmtimer_softc *sc;
482 
483 	sc = arg;
484 
485 	/* Ack the interrupt, and invoke the callback if it's still enabled. */
486 	DMTIMER_WRITE4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
487 	if (sc->func.et.et_active)
488 		sc->func.et.et_event_cb(&sc->func.et, sc->func.et.et_arg);
489 
490 	return (FILTER_HANDLED);
491 }
492 
493 /*
494  * Checks if timer is suitable to be system timer
495  */
496 static int
497 am335x_dmtimer_system_compatible(device_t dev)
498 {
499 	phandle_t node;
500 
501 	node = ofw_bus_get_node(dev);
502 	if (OF_hasprop(node, "ti,timer-alwon"))
503 		return (0);
504 
505 	return (1);
506 }
507 
508 static int
509 am335x_dmtimer_init_et(struct am335x_dmtimer_softc *sc)
510 {
511 	if (am335x_dmtimer_et_sc != NULL)
512 		return (EEXIST);
513 
514 #ifdef PPS_SYNC
515 	if ((am335x_dmtimer_pps_module > 0) &&
516 	    (!ti_hwmods_contains(sc->dev, am335x_dmtimer_pps_hwmod))) {
517 	    	device_printf(sc->dev, "not PPS enabled\n");
518 	 	return (ENXIO);
519 	}
520 #endif
521 
522 	/* Setup eventtimer interrupt handler. */
523 	if (bus_setup_intr(sc->dev, sc->tmr_irq_res, INTR_TYPE_CLK,
524 			am335x_dmtimer_intr, NULL, sc, &sc->tmr_irq_handler) != 0) {
525 		device_printf(sc->dev, "Unable to setup the clock irq handler.\n");
526 		return (ENXIO);
527 	}
528 
529 	sc->func.et.et_name = "AM335x Eventtimer";
530 	sc->func.et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
531 	sc->func.et.et_quality = 1000;
532 	sc->func.et.et_frequency = sc->sysclk_freq;
533 	sc->func.et.et_min_period =
534 	    ((0x00000005LLU << 32) / sc->func.et.et_frequency);
535 	sc->func.et.et_max_period =
536 	    (0xfffffffeLLU << 32) / sc->func.et.et_frequency;
537 	sc->func.et.et_start = am335x_dmtimer_start;
538 	sc->func.et.et_stop = am335x_dmtimer_stop;
539 	sc->func.et.et_priv = sc;
540 	et_register(&sc->func.et);
541 
542 	am335x_dmtimer_et_sc = sc;
543 
544 	return (0);
545 }
546 
547 static int
548 am335x_dmtimer_init_tc(struct am335x_dmtimer_softc *sc)
549 {
550 	if (am335x_dmtimer_tc_sc != NULL)
551 		return (EEXIST);
552 
553 	/* Set up timecounter, start it, register it. */
554 	DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET);
555 	while (DMTIMER_READ4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET)
556 		continue;
557 
558 	sc->tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD;
559 	DMTIMER_WRITE4(sc, DMT_TLDR, 0);
560 	DMTIMER_WRITE4(sc, DMT_TCRR, 0);
561 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);
562 
563 	sc->func.tc.tc_name           = "AM335x Timecounter";
564 	sc->func.tc.tc_get_timecount  = am335x_dmtimer_tc_get_timecount;
565 	sc->func.tc.tc_counter_mask   = ~0u;
566 	sc->func.tc.tc_frequency      = sc->sysclk_freq;
567 	sc->func.tc.tc_quality        = 1000;
568 	sc->func.tc.tc_priv           = sc;
569 	tc_init(&sc->func.tc);
570 
571 	am335x_dmtimer_tc_sc = sc;
572 
573 	return (0);
574 }
575 
576 static int
577 am335x_dmtimer_probe(device_t dev)
578 {
579 
580 	if (!ofw_bus_status_okay(dev))
581 		return (ENXIO);
582 
583 	if (ofw_bus_is_compatible(dev, "ti,am335x-timer-1ms") ||
584 	    ofw_bus_is_compatible(dev, "ti,am335x-timer")) {
585 		device_set_desc(dev, "AM335x DMTimer");
586 		return(BUS_PROBE_DEFAULT);
587 	}
588 
589 	return (ENXIO);
590 }
591 
592 static int
593 am335x_dmtimer_attach(device_t dev)
594 {
595 	struct am335x_dmtimer_softc *sc;
596 	int err;
597 	clk_ident_t timer_id;
598 	int enable;
599 
600 	/*
601 	 * Note that if this routine returns an error status rather than running
602 	 * to completion it makes no attempt to clean up allocated resources;
603 	 * the system is essentially dead anyway without functional timers.
604 	 */
605 
606 	sc = device_get_softc(dev);
607 	sc->dev = dev;
608 
609 	/* Get the base clock frequency. */
610 	err = ti_prcm_clk_get_source_freq(SYS_CLK, &sc->sysclk_freq);
611 	if (err) {
612 		device_printf(dev, "Error: could not get sysclk frequency\n");
613 		return (ENXIO);
614 	}
615 
616 	/* Request the memory resources. */
617 	sc->tmr_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
618 	    &sc->tmr_mem_rid, RF_ACTIVE);
619 	if (sc->tmr_mem_res == NULL) {
620 		device_printf(dev, "Error: could not allocate mem resources\n");
621 		return (ENXIO);
622 	}
623 
624 	/* Request the IRQ resources. */
625 	sc->tmr_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
626 	    &sc->tmr_irq_rid, RF_ACTIVE);
627 	if (err) {
628 		bus_release_resource(dev, SYS_RES_MEMORY, sc->tmr_mem_rid,
629 		    sc->tmr_mem_res);
630 		device_printf(dev, "Error: could not allocate irq resources\n");
631 		return (ENXIO);
632 	}
633 
634 #ifdef PPS_SYNC
635 	am335x_dmtimer_pps_init(dev, sc);
636 #endif
637 
638 	enable = 0;
639 	/* Try to use as a timecounter or event timer */
640 	if (am335x_dmtimer_system_compatible(dev)) {
641 		if (am335x_dmtimer_init_tc(sc) == 0)
642 			enable = 1;
643 		else if (am335x_dmtimer_init_et(sc) == 0)
644 			enable = 1;
645 	}
646 
647 	if (enable) {
648 		/* Enable clocks and power on the chosen devices. */
649 		timer_id = ti_hwmods_get_clock(dev);
650 		if (timer_id == INVALID_CLK_IDENT) {
651 			bus_release_resource(dev, SYS_RES_MEMORY, sc->tmr_mem_rid,
652 			    sc->tmr_mem_res);
653 			bus_release_resource(dev, SYS_RES_IRQ, sc->tmr_irq_rid,
654 			    sc->tmr_irq_res);
655 			device_printf(dev, "failed to get device id using ti,hwmods\n");
656 			return (ENXIO);
657 		}
658 
659 		err  = ti_prcm_clk_set_source(timer_id, SYSCLK_CLK);
660 		err |= ti_prcm_clk_enable(timer_id);
661 
662 		if (err) {
663 			bus_release_resource(dev, SYS_RES_MEMORY, sc->tmr_mem_rid,
664 			    sc->tmr_mem_res);
665 			bus_release_resource(dev, SYS_RES_IRQ, sc->tmr_irq_rid,
666 			    sc->tmr_irq_res);
667 			device_printf(dev, "Error: could not enable timer clock\n");
668 			return (ENXIO);
669 		}
670 	}
671 
672 	return (0);
673 }
674 
675 static device_method_t am335x_dmtimer_methods[] = {
676 	DEVMETHOD(device_probe,		am335x_dmtimer_probe),
677 	DEVMETHOD(device_attach,	am335x_dmtimer_attach),
678 	{ 0, 0 }
679 };
680 
681 static driver_t am335x_dmtimer_driver = {
682 	"am335x_dmtimer",
683 	am335x_dmtimer_methods,
684 	sizeof(struct am335x_dmtimer_softc),
685 };
686 
687 static devclass_t am335x_dmtimer_devclass;
688 
689 DRIVER_MODULE(am335x_dmtimer, simplebus, am335x_dmtimer_driver, am335x_dmtimer_devclass, 0, 0);
690 MODULE_DEPEND(am335x_dmtimer, am335x_prcm, 1, 1, 1);
691 
692 void
693 DELAY(int usec)
694 {
695 	struct am335x_dmtimer_softc *sc;
696 	int32_t counts;
697 	uint32_t first, last;
698 
699 	sc = am335x_dmtimer_tc_sc;
700 
701 	if (sc == NULL) {
702 		for (; usec > 0; usec--)
703 			for (counts = 200; counts > 0; counts--)
704 				/* Prevent gcc from optimizing  out the loop */
705 				cpufunc_nullop();
706 		return;
707 	}
708 
709 	/* Get the number of times to count */
710 	counts = (usec + 1) * (sc->sysclk_freq / 1000000);
711 
712 	first = DMTIMER_READ4(sc, DMT_TCRR);
713 
714 	while (counts > 0) {
715 		last = DMTIMER_READ4(sc, DMT_TCRR);
716 		if (last > first) {
717 			counts -= (int32_t)(last - first);
718 		} else {
719 			counts -= (int32_t)((0xFFFFFFFF - first) + last);
720 		}
721 		first = last;
722 	}
723 }
724 
725