1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Based on OMAP3 INTC code by Ben Gray 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/ktr.h> 40 #include <sys/module.h> 41 #include <sys/proc.h> 42 #include <sys/rman.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #ifdef INTRNG 52 #include "pic_if.h" 53 #endif 54 55 #define INTC_REVISION 0x00 56 #define INTC_SYSCONFIG 0x10 57 #define INTC_SYSSTATUS 0x14 58 #define INTC_SIR_IRQ 0x40 59 #define INTC_CONTROL 0x48 60 #define INTC_THRESHOLD 0x68 61 #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) 62 #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) 63 #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) 64 #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) 65 66 #define INTC_SIR_SPURIOUS_MASK 0xffffff80 67 #define INTC_SIR_ACTIVE_MASK 0x7f 68 69 #define INTC_NIRQS 128 70 71 #ifdef INTRNG 72 struct ti_aintc_irqsrc { 73 struct intr_irqsrc tai_isrc; 74 u_int tai_irq; 75 }; 76 #endif 77 78 struct ti_aintc_softc { 79 device_t sc_dev; 80 struct resource * aintc_res[3]; 81 bus_space_tag_t aintc_bst; 82 bus_space_handle_t aintc_bsh; 83 uint8_t ver; 84 #ifdef INTRNG 85 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS]; 86 #endif 87 }; 88 89 static struct resource_spec ti_aintc_spec[] = { 90 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 91 { -1, 0 } 92 }; 93 94 static struct ti_aintc_softc *ti_aintc_sc = NULL; 95 96 #define aintc_read_4(_sc, reg) \ 97 bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg)) 98 #define aintc_write_4(_sc, reg, val) \ 99 bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val)) 100 101 /* List of compatible strings for FDT tree */ 102 static struct ofw_compat_data compat_data[] = { 103 {"ti,am33xx-intc", 1}, 104 {"ti,omap2-intc", 1}, 105 {NULL, 0}, 106 }; 107 108 #ifdef INTRNG 109 static inline void 110 ti_aintc_irq_eoi(struct ti_aintc_softc *sc) 111 { 112 113 aintc_write_4(sc, INTC_CONTROL, 1); 114 } 115 116 static inline void 117 ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq) 118 { 119 120 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); 121 } 122 123 static inline void 124 ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq) 125 { 126 127 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); 128 } 129 130 static int 131 ti_aintc_intr(void *arg) 132 { 133 uint32_t irq; 134 struct ti_aintc_softc *sc = arg; 135 136 /* Get active interrupt */ 137 irq = aintc_read_4(sc, INTC_SIR_IRQ); 138 if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) { 139 device_printf(sc->sc_dev, 140 "Spurious interrupt detected (0x%08x)\n", irq); 141 ti_aintc_irq_eoi(sc); 142 return (FILTER_HANDLED); 143 } 144 145 /* Only level-sensitive interrupts detection is supported. */ 146 irq &= INTC_SIR_ACTIVE_MASK; 147 if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc, 148 curthread->td_intr_frame) != 0) { 149 ti_aintc_irq_mask(sc, irq); 150 ti_aintc_irq_eoi(sc); 151 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); 152 } 153 154 arm_irq_memory_barrier(irq); /* XXX */ 155 return (FILTER_HANDLED); 156 } 157 158 static void 159 ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 160 { 161 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 162 struct ti_aintc_softc *sc = device_get_softc(dev); 163 164 arm_irq_memory_barrier(irq); 165 ti_aintc_irq_unmask(sc, irq); 166 } 167 168 static void 169 ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 170 { 171 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 172 struct ti_aintc_softc *sc = device_get_softc(dev); 173 174 ti_aintc_irq_mask(sc, irq); 175 } 176 177 static int 178 ti_aintc_map_intr(device_t dev, struct intr_map_data *data, 179 struct intr_irqsrc **isrcp) 180 { 181 struct ti_aintc_softc *sc; 182 183 if (data->type != INTR_MAP_DATA_FDT || data->fdt.ncells != 1 || 184 data->fdt.cells[0] >= INTC_NIRQS) 185 return (EINVAL); 186 187 sc = device_get_softc(dev); 188 *isrcp = &sc->aintc_isrcs[data->fdt.cells[0]].tai_isrc; 189 return (0); 190 } 191 192 static void 193 ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 194 { 195 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 196 struct ti_aintc_softc *sc = device_get_softc(dev); 197 198 ti_aintc_irq_mask(sc, irq); 199 ti_aintc_irq_eoi(sc); 200 } 201 202 static void 203 ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 204 { 205 206 ti_aintc_enable_intr(dev, isrc); 207 } 208 209 static void 210 ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc) 211 { 212 213 ti_aintc_irq_eoi(device_get_softc(dev)); 214 } 215 216 static int 217 ti_aintc_pic_attach(struct ti_aintc_softc *sc) 218 { 219 int error; 220 uint32_t irq; 221 const char *name; 222 intptr_t xref; 223 224 name = device_get_nameunit(sc->sc_dev); 225 for (irq = 0; irq < INTC_NIRQS; irq++) { 226 sc->aintc_isrcs[irq].tai_irq = irq; 227 228 error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc, 229 sc->sc_dev, 0, "%s,%u", name, irq); 230 if (error != 0) 231 return (error); 232 } 233 234 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 235 error = intr_pic_register(sc->sc_dev, xref); 236 if (error != 0) 237 return (error); 238 239 return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0)); 240 } 241 242 #else 243 static void 244 aintc_post_filter(void *arg) 245 { 246 247 arm_irq_memory_barrier(0); 248 aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */ 249 } 250 #endif 251 252 static int 253 ti_aintc_probe(device_t dev) 254 { 255 if (!ofw_bus_status_okay(dev)) 256 return (ENXIO); 257 258 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 259 return (ENXIO); 260 261 device_set_desc(dev, "TI AINTC Interrupt Controller"); 262 return (BUS_PROBE_DEFAULT); 263 } 264 265 static int 266 ti_aintc_attach(device_t dev) 267 { 268 struct ti_aintc_softc *sc = device_get_softc(dev); 269 uint32_t x; 270 271 sc->sc_dev = dev; 272 273 if (ti_aintc_sc) 274 return (ENXIO); 275 276 if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { 277 device_printf(dev, "could not allocate resources\n"); 278 return (ENXIO); 279 } 280 281 sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); 282 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); 283 284 ti_aintc_sc = sc; 285 286 x = aintc_read_4(sc, INTC_REVISION); 287 device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); 288 289 /* SoftReset */ 290 aintc_write_4(sc, INTC_SYSCONFIG, 2); 291 292 /* Wait for reset to complete */ 293 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1)); 294 295 /*Set Priority Threshold */ 296 aintc_write_4(sc, INTC_THRESHOLD, 0xFF); 297 298 #ifndef INTRNG 299 arm_post_filter = aintc_post_filter; 300 #else 301 if (ti_aintc_pic_attach(sc) != 0) { 302 device_printf(dev, "could not attach PIC\n"); 303 return (ENXIO); 304 } 305 #endif 306 return (0); 307 } 308 309 static device_method_t ti_aintc_methods[] = { 310 DEVMETHOD(device_probe, ti_aintc_probe), 311 DEVMETHOD(device_attach, ti_aintc_attach), 312 313 #ifdef INTRNG 314 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr), 315 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr), 316 DEVMETHOD(pic_map_intr, ti_aintc_map_intr), 317 DEVMETHOD(pic_post_filter, ti_aintc_post_filter), 318 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread), 319 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread), 320 #endif 321 322 { 0, 0 } 323 }; 324 325 static driver_t ti_aintc_driver = { 326 "aintc", 327 ti_aintc_methods, 328 sizeof(struct ti_aintc_softc), 329 }; 330 331 static devclass_t ti_aintc_devclass; 332 333 EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 334 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 335 SIMPLEBUS_PNP_INFO(compat_data); 336 337 #ifndef INTRNG 338 int 339 arm_get_next_irq(int last_irq) 340 { 341 struct ti_aintc_softc *sc = ti_aintc_sc; 342 uint32_t active_irq; 343 344 /* Get the next active interrupt */ 345 active_irq = aintc_read_4(sc, INTC_SIR_IRQ); 346 347 /* Check for spurious interrupt */ 348 if ((active_irq & 0xffffff80)) { 349 device_printf(sc->sc_dev, 350 "Spurious interrupt detected (0x%08x)\n", active_irq); 351 aintc_write_4(sc, INTC_SIR_IRQ, 0); 352 return -1; 353 } 354 355 if (active_irq != last_irq) 356 return active_irq; 357 else 358 return -1; 359 } 360 361 void 362 arm_mask_irq(uintptr_t nb) 363 { 364 struct ti_aintc_softc *sc = ti_aintc_sc; 365 366 aintc_write_4(sc, INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F))); 367 aintc_write_4(sc, INTC_CONTROL, 1); /* EOI */ 368 } 369 370 void 371 arm_unmask_irq(uintptr_t nb) 372 { 373 struct ti_aintc_softc *sc = ti_aintc_sc; 374 375 arm_irq_memory_barrier(nb); 376 aintc_write_4(sc, INTC_MIR_CLEAR(nb >> 5), (1UL << (nb & 0x1F))); 377 } 378 #endif 379