1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Based on OMAP3 INTC code by Ben Gray 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_platform.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/ktr.h> 40 #include <sys/module.h> 41 #include <sys/proc.h> 42 #include <sys/rman.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include "pic_if.h" 51 52 #define INTC_REVISION 0x00 53 #define INTC_SYSCONFIG 0x10 54 #define INTC_SYSSTATUS 0x14 55 #define INTC_SIR_IRQ 0x40 56 #define INTC_CONTROL 0x48 57 #define INTC_THRESHOLD 0x68 58 #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) 59 #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) 60 #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) 61 #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) 62 63 #define INTC_SIR_SPURIOUS_MASK 0xffffff80 64 #define INTC_SIR_ACTIVE_MASK 0x7f 65 66 #define INTC_NIRQS 128 67 68 struct ti_aintc_irqsrc { 69 struct intr_irqsrc tai_isrc; 70 u_int tai_irq; 71 }; 72 73 struct ti_aintc_softc { 74 device_t sc_dev; 75 struct resource * aintc_res[3]; 76 bus_space_tag_t aintc_bst; 77 bus_space_handle_t aintc_bsh; 78 uint8_t ver; 79 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS]; 80 }; 81 82 static struct resource_spec ti_aintc_spec[] = { 83 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 84 { -1, 0 } 85 }; 86 87 #define aintc_read_4(_sc, reg) \ 88 bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg)) 89 #define aintc_write_4(_sc, reg, val) \ 90 bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val)) 91 92 /* List of compatible strings for FDT tree */ 93 static struct ofw_compat_data compat_data[] = { 94 {"ti,am33xx-intc", 1}, 95 {"ti,omap2-intc", 1}, 96 {NULL, 0}, 97 }; 98 99 static inline void 100 ti_aintc_irq_eoi(struct ti_aintc_softc *sc) 101 { 102 103 aintc_write_4(sc, INTC_CONTROL, 1); 104 } 105 106 static inline void 107 ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq) 108 { 109 110 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); 111 } 112 113 static inline void 114 ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq) 115 { 116 117 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); 118 } 119 120 static int 121 ti_aintc_intr(void *arg) 122 { 123 uint32_t irq; 124 struct ti_aintc_softc *sc = arg; 125 126 /* Get active interrupt */ 127 irq = aintc_read_4(sc, INTC_SIR_IRQ); 128 if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) { 129 device_printf(sc->sc_dev, 130 "Spurious interrupt detected (0x%08x)\n", irq); 131 ti_aintc_irq_eoi(sc); 132 return (FILTER_HANDLED); 133 } 134 135 /* Only level-sensitive interrupts detection is supported. */ 136 irq &= INTC_SIR_ACTIVE_MASK; 137 if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc, 138 curthread->td_intr_frame) != 0) { 139 ti_aintc_irq_mask(sc, irq); 140 ti_aintc_irq_eoi(sc); 141 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); 142 } 143 144 arm_irq_memory_barrier(irq); /* XXX */ 145 return (FILTER_HANDLED); 146 } 147 148 static void 149 ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 150 { 151 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 152 struct ti_aintc_softc *sc = device_get_softc(dev); 153 154 arm_irq_memory_barrier(irq); 155 ti_aintc_irq_unmask(sc, irq); 156 } 157 158 static void 159 ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 160 { 161 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 162 struct ti_aintc_softc *sc = device_get_softc(dev); 163 164 ti_aintc_irq_mask(sc, irq); 165 } 166 167 static int 168 ti_aintc_map_intr(device_t dev, struct intr_map_data *data, 169 struct intr_irqsrc **isrcp) 170 { 171 struct intr_map_data_fdt *daf; 172 struct ti_aintc_softc *sc; 173 174 if (data->type != INTR_MAP_DATA_FDT) 175 return (ENOTSUP); 176 177 daf = (struct intr_map_data_fdt *)data; 178 if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS) 179 return (EINVAL); 180 181 sc = device_get_softc(dev); 182 *isrcp = &sc->aintc_isrcs[daf->cells[0]].tai_isrc; 183 return (0); 184 } 185 186 static void 187 ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 188 { 189 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 190 struct ti_aintc_softc *sc = device_get_softc(dev); 191 192 ti_aintc_irq_mask(sc, irq); 193 ti_aintc_irq_eoi(sc); 194 } 195 196 static void 197 ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 198 { 199 200 ti_aintc_enable_intr(dev, isrc); 201 } 202 203 static void 204 ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc) 205 { 206 207 ti_aintc_irq_eoi(device_get_softc(dev)); 208 } 209 210 static int 211 ti_aintc_pic_attach(struct ti_aintc_softc *sc) 212 { 213 struct intr_pic *pic; 214 int error; 215 uint32_t irq; 216 const char *name; 217 intptr_t xref; 218 219 name = device_get_nameunit(sc->sc_dev); 220 for (irq = 0; irq < INTC_NIRQS; irq++) { 221 sc->aintc_isrcs[irq].tai_irq = irq; 222 223 error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc, 224 sc->sc_dev, 0, "%s,%u", name, irq); 225 if (error != 0) 226 return (error); 227 } 228 229 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 230 pic = intr_pic_register(sc->sc_dev, xref); 231 if (pic == NULL) 232 return (ENXIO); 233 234 return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0)); 235 } 236 237 static int 238 ti_aintc_probe(device_t dev) 239 { 240 if (!ofw_bus_status_okay(dev)) 241 return (ENXIO); 242 243 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 244 return (ENXIO); 245 246 device_set_desc(dev, "TI AINTC Interrupt Controller"); 247 return (BUS_PROBE_DEFAULT); 248 } 249 250 static int 251 ti_aintc_attach(device_t dev) 252 { 253 struct ti_aintc_softc *sc = device_get_softc(dev); 254 uint32_t x; 255 256 sc->sc_dev = dev; 257 258 if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { 259 device_printf(dev, "could not allocate resources\n"); 260 return (ENXIO); 261 } 262 263 sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); 264 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); 265 266 x = aintc_read_4(sc, INTC_REVISION); 267 device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); 268 269 /* SoftReset */ 270 aintc_write_4(sc, INTC_SYSCONFIG, 2); 271 272 /* Wait for reset to complete */ 273 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1)); 274 275 /*Set Priority Threshold */ 276 aintc_write_4(sc, INTC_THRESHOLD, 0xFF); 277 278 if (ti_aintc_pic_attach(sc) != 0) { 279 device_printf(dev, "could not attach PIC\n"); 280 return (ENXIO); 281 } 282 return (0); 283 } 284 285 static device_method_t ti_aintc_methods[] = { 286 DEVMETHOD(device_probe, ti_aintc_probe), 287 DEVMETHOD(device_attach, ti_aintc_attach), 288 289 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr), 290 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr), 291 DEVMETHOD(pic_map_intr, ti_aintc_map_intr), 292 DEVMETHOD(pic_post_filter, ti_aintc_post_filter), 293 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread), 294 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread), 295 296 { 0, 0 } 297 }; 298 299 static driver_t ti_aintc_driver = { 300 "ti_aintc", 301 ti_aintc_methods, 302 sizeof(struct ti_aintc_softc), 303 }; 304 305 static devclass_t ti_aintc_devclass; 306 307 EARLY_DRIVER_MODULE(ti_aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 308 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 309 SIMPLEBUS_PNP_INFO(compat_data); 310