1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Based on OMAP3 INTC code by Ben Gray 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/module.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "pic_if.h" 53 54 #define INTC_REVISION 0x00 55 #define INTC_SYSCONFIG 0x10 56 #define INTC_SYSSTATUS 0x14 57 #define INTC_SIR_IRQ 0x40 58 #define INTC_CONTROL 0x48 59 #define INTC_THRESHOLD 0x68 60 #define INTC_MIR_CLEAR(x) (0x88 + ((x) * 0x20)) 61 #define INTC_MIR_SET(x) (0x8C + ((x) * 0x20)) 62 #define INTC_ISR_SET(x) (0x90 + ((x) * 0x20)) 63 #define INTC_ISR_CLEAR(x) (0x94 + ((x) * 0x20)) 64 65 #define INTC_SIR_SPURIOUS_MASK 0xffffff80 66 #define INTC_SIR_ACTIVE_MASK 0x7f 67 68 #define INTC_NIRQS 128 69 70 struct ti_aintc_irqsrc { 71 struct intr_irqsrc tai_isrc; 72 u_int tai_irq; 73 }; 74 75 struct ti_aintc_softc { 76 device_t sc_dev; 77 struct resource * aintc_res[3]; 78 bus_space_tag_t aintc_bst; 79 bus_space_handle_t aintc_bsh; 80 uint8_t ver; 81 struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS]; 82 }; 83 84 static struct resource_spec ti_aintc_spec[] = { 85 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 86 { -1, 0 } 87 }; 88 89 #define aintc_read_4(_sc, reg) \ 90 bus_space_read_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg)) 91 #define aintc_write_4(_sc, reg, val) \ 92 bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val)) 93 94 /* List of compatible strings for FDT tree */ 95 static struct ofw_compat_data compat_data[] = { 96 {"ti,am33xx-intc", 1}, 97 {"ti,omap2-intc", 1}, 98 {NULL, 0}, 99 }; 100 101 static inline void 102 ti_aintc_irq_eoi(struct ti_aintc_softc *sc) 103 { 104 105 aintc_write_4(sc, INTC_CONTROL, 1); 106 } 107 108 static inline void 109 ti_aintc_irq_mask(struct ti_aintc_softc *sc, u_int irq) 110 { 111 112 aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F))); 113 } 114 115 static inline void 116 ti_aintc_irq_unmask(struct ti_aintc_softc *sc, u_int irq) 117 { 118 119 aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F))); 120 } 121 122 static int 123 ti_aintc_intr(void *arg) 124 { 125 uint32_t irq; 126 struct ti_aintc_softc *sc = arg; 127 128 /* Get active interrupt */ 129 irq = aintc_read_4(sc, INTC_SIR_IRQ); 130 if ((irq & INTC_SIR_SPURIOUS_MASK) != 0) { 131 device_printf(sc->sc_dev, 132 "Spurious interrupt detected (0x%08x)\n", irq); 133 ti_aintc_irq_eoi(sc); 134 return (FILTER_HANDLED); 135 } 136 137 /* Only level-sensitive interrupts detection is supported. */ 138 irq &= INTC_SIR_ACTIVE_MASK; 139 if (intr_isrc_dispatch(&sc->aintc_isrcs[irq].tai_isrc, 140 curthread->td_intr_frame) != 0) { 141 ti_aintc_irq_mask(sc, irq); 142 ti_aintc_irq_eoi(sc); 143 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); 144 } 145 146 arm_irq_memory_barrier(irq); /* XXX */ 147 return (FILTER_HANDLED); 148 } 149 150 static void 151 ti_aintc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 152 { 153 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 154 struct ti_aintc_softc *sc = device_get_softc(dev); 155 156 arm_irq_memory_barrier(irq); 157 ti_aintc_irq_unmask(sc, irq); 158 } 159 160 static void 161 ti_aintc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 162 { 163 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 164 struct ti_aintc_softc *sc = device_get_softc(dev); 165 166 ti_aintc_irq_mask(sc, irq); 167 } 168 169 static int 170 ti_aintc_map_intr(device_t dev, struct intr_map_data *data, 171 struct intr_irqsrc **isrcp) 172 { 173 struct intr_map_data_fdt *daf; 174 struct ti_aintc_softc *sc; 175 176 if (data->type != INTR_MAP_DATA_FDT) 177 return (ENOTSUP); 178 179 daf = (struct intr_map_data_fdt *)data; 180 if (daf->ncells != 1 || daf->cells[0] >= INTC_NIRQS) 181 return (EINVAL); 182 183 sc = device_get_softc(dev); 184 *isrcp = &sc->aintc_isrcs[daf->cells[0]].tai_isrc; 185 return (0); 186 } 187 188 static void 189 ti_aintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 190 { 191 u_int irq = ((struct ti_aintc_irqsrc *)isrc)->tai_irq; 192 struct ti_aintc_softc *sc = device_get_softc(dev); 193 194 ti_aintc_irq_mask(sc, irq); 195 ti_aintc_irq_eoi(sc); 196 } 197 198 static void 199 ti_aintc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 200 { 201 202 ti_aintc_enable_intr(dev, isrc); 203 } 204 205 static void 206 ti_aintc_post_filter(device_t dev, struct intr_irqsrc *isrc) 207 { 208 209 ti_aintc_irq_eoi(device_get_softc(dev)); 210 } 211 212 static int 213 ti_aintc_pic_attach(struct ti_aintc_softc *sc) 214 { 215 struct intr_pic *pic; 216 int error; 217 uint32_t irq; 218 const char *name; 219 intptr_t xref; 220 221 name = device_get_nameunit(sc->sc_dev); 222 for (irq = 0; irq < INTC_NIRQS; irq++) { 223 sc->aintc_isrcs[irq].tai_irq = irq; 224 225 error = intr_isrc_register(&sc->aintc_isrcs[irq].tai_isrc, 226 sc->sc_dev, 0, "%s,%u", name, irq); 227 if (error != 0) 228 return (error); 229 } 230 231 xref = OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)); 232 pic = intr_pic_register(sc->sc_dev, xref); 233 if (pic == NULL) 234 return (ENXIO); 235 236 return (intr_pic_claim_root(sc->sc_dev, xref, ti_aintc_intr, sc, 0)); 237 } 238 239 static int 240 ti_aintc_probe(device_t dev) 241 { 242 if (!ofw_bus_status_okay(dev)) 243 return (ENXIO); 244 245 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 246 return (ENXIO); 247 248 device_set_desc(dev, "TI AINTC Interrupt Controller"); 249 return (BUS_PROBE_DEFAULT); 250 } 251 252 static int 253 ti_aintc_attach(device_t dev) 254 { 255 struct ti_aintc_softc *sc = device_get_softc(dev); 256 uint32_t x; 257 258 sc->sc_dev = dev; 259 260 if (bus_alloc_resources(dev, ti_aintc_spec, sc->aintc_res)) { 261 device_printf(dev, "could not allocate resources\n"); 262 return (ENXIO); 263 } 264 265 sc->aintc_bst = rman_get_bustag(sc->aintc_res[0]); 266 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res[0]); 267 268 x = aintc_read_4(sc, INTC_REVISION); 269 device_printf(dev, "Revision %u.%u\n",(x >> 4) & 0xF, x & 0xF); 270 271 /* SoftReset */ 272 aintc_write_4(sc, INTC_SYSCONFIG, 2); 273 274 /* Wait for reset to complete */ 275 while(!(aintc_read_4(sc, INTC_SYSSTATUS) & 1)); 276 277 /*Set Priority Threshold */ 278 aintc_write_4(sc, INTC_THRESHOLD, 0xFF); 279 280 if (ti_aintc_pic_attach(sc) != 0) { 281 device_printf(dev, "could not attach PIC\n"); 282 return (ENXIO); 283 } 284 return (0); 285 } 286 287 static device_method_t ti_aintc_methods[] = { 288 DEVMETHOD(device_probe, ti_aintc_probe), 289 DEVMETHOD(device_attach, ti_aintc_attach), 290 291 DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr), 292 DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr), 293 DEVMETHOD(pic_map_intr, ti_aintc_map_intr), 294 DEVMETHOD(pic_post_filter, ti_aintc_post_filter), 295 DEVMETHOD(pic_post_ithread, ti_aintc_post_ithread), 296 DEVMETHOD(pic_pre_ithread, ti_aintc_pre_ithread), 297 298 { 0, 0 } 299 }; 300 301 static driver_t ti_aintc_driver = { 302 "ti_aintc", 303 ti_aintc_methods, 304 sizeof(struct ti_aintc_softc), 305 }; 306 307 static devclass_t ti_aintc_devclass; 308 309 EARLY_DRIVER_MODULE(ti_aintc, simplebus, ti_aintc_driver, ti_aintc_devclass, 310 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 311 SIMPLEBUS_PNP_INFO(compat_data); 312