1*b0352107SMichal Meloun /*- 2*b0352107SMichal Meloun * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3*b0352107SMichal Meloun * 4*b0352107SMichal Meloun * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5*b0352107SMichal Meloun * 6*b0352107SMichal Meloun * Redistribution and use in source and binary forms, with or without 7*b0352107SMichal Meloun * modification, are permitted provided that the following conditions 8*b0352107SMichal Meloun * are met: 9*b0352107SMichal Meloun * 1. Redistributions of source code must retain the above copyright 10*b0352107SMichal Meloun * notice, this list of conditions and the following disclaimer. 11*b0352107SMichal Meloun * 2. Redistributions in binary form must reproduce the above copyright 12*b0352107SMichal Meloun * notice, this list of conditions and the following disclaimer in the 13*b0352107SMichal Meloun * documentation and/or other materials provided with the distribution. 14*b0352107SMichal Meloun * 15*b0352107SMichal Meloun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*b0352107SMichal Meloun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*b0352107SMichal Meloun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*b0352107SMichal Meloun * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*b0352107SMichal Meloun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*b0352107SMichal Meloun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*b0352107SMichal Meloun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*b0352107SMichal Meloun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*b0352107SMichal Meloun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*b0352107SMichal Meloun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*b0352107SMichal Meloun * SUCH DAMAGE. 26*b0352107SMichal Meloun */ 27*b0352107SMichal Meloun 28*b0352107SMichal Meloun #include <sys/cdefs.h> 29*b0352107SMichal Meloun __FBSDID("$FreeBSD$"); 30*b0352107SMichal Meloun 31*b0352107SMichal Meloun #include <sys/param.h> 32*b0352107SMichal Meloun #include <sys/systm.h> 33*b0352107SMichal Meloun #include <sys/bus.h> 34*b0352107SMichal Meloun #include <sys/kernel.h> 35*b0352107SMichal Meloun #include <sys/lock.h> 36*b0352107SMichal Meloun #include <sys/mutex.h> 37*b0352107SMichal Meloun #include <sys/smp.h> 38*b0352107SMichal Meloun 39*b0352107SMichal Meloun #include <vm/vm.h> 40*b0352107SMichal Meloun #include <vm/pmap.h> 41*b0352107SMichal Meloun 42*b0352107SMichal Meloun #include <machine/cpu.h> 43*b0352107SMichal Meloun #include <machine/fdt.h> 44*b0352107SMichal Meloun #include <machine/smp.h> 45*b0352107SMichal Meloun #include <machine/platformvar.h> 46*b0352107SMichal Meloun 47*b0352107SMichal Meloun #include <dev/ofw/openfirm.h> 48*b0352107SMichal Meloun #include <dev/ofw/ofw_cpu.h> 49*b0352107SMichal Meloun #include <dev/ofw/ofw_bus_subr.h> 50*b0352107SMichal Meloun #include <dev/psci/psci.h> 51*b0352107SMichal Meloun 52*b0352107SMichal Meloun #include <arm/rockchip/rk32xx_mp.h> 53*b0352107SMichal Meloun 54*b0352107SMichal Meloun #define IMEM_PHYSBASE 0xFF700000 55*b0352107SMichal Meloun #define IMEM_SIZE 0x00018000 56*b0352107SMichal Meloun 57*b0352107SMichal Meloun #define PMU_PHYSBASE 0xFF730000 58*b0352107SMichal Meloun #define PMU_SIZE 0x00010000 59*b0352107SMichal Meloun #define PMU_PWRDN_CON 0x08 60*b0352107SMichal Meloun 61*b0352107SMichal Meloun static int running_cpus; 62*b0352107SMichal Meloun static uint32_t psci_mask, pmu_mask; 63*b0352107SMichal Meloun void 64*b0352107SMichal Meloun rk32xx_mp_setmaxid(platform_t plat) 65*b0352107SMichal Meloun { 66*b0352107SMichal Meloun int ncpu; 67*b0352107SMichal Meloun 68*b0352107SMichal Meloun /* If we've already set the global vars don't bother to do it again. */ 69*b0352107SMichal Meloun if (mp_ncpus != 0) 70*b0352107SMichal Meloun return; 71*b0352107SMichal Meloun 72*b0352107SMichal Meloun /* Read current CP15 Cache Size ID Register */ 73*b0352107SMichal Meloun ncpu = cp15_l2ctlr_get(); 74*b0352107SMichal Meloun ncpu = CPUV7_L2CTLR_NPROC(ncpu); 75*b0352107SMichal Meloun 76*b0352107SMichal Meloun mp_ncpus = ncpu; 77*b0352107SMichal Meloun mp_maxid = ncpu - 1; 78*b0352107SMichal Meloun } 79*b0352107SMichal Meloun 80*b0352107SMichal Meloun static void 81*b0352107SMichal Meloun rk32xx_mp_start_pmu(uint32_t mask) 82*b0352107SMichal Meloun { 83*b0352107SMichal Meloun bus_space_handle_t imem; 84*b0352107SMichal Meloun bus_space_handle_t pmu; 85*b0352107SMichal Meloun uint32_t val; 86*b0352107SMichal Meloun int i, rv; 87*b0352107SMichal Meloun 88*b0352107SMichal Meloun rv = bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE, IMEM_SIZE, 0, &imem); 89*b0352107SMichal Meloun if (rv != 0) 90*b0352107SMichal Meloun panic("Couldn't map the IMEM\n"); 91*b0352107SMichal Meloun rv = bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu); 92*b0352107SMichal Meloun if (rv != 0) 93*b0352107SMichal Meloun panic("Couldn't map the PMU\n"); 94*b0352107SMichal Meloun 95*b0352107SMichal Meloun /* Power off all secondary cores first */ 96*b0352107SMichal Meloun val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON); 97*b0352107SMichal Meloun for (i = 1; i < mp_ncpus; i++) 98*b0352107SMichal Meloun val |= 1 << i; 99*b0352107SMichal Meloun bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val); 100*b0352107SMichal Meloun DELAY(5000); 101*b0352107SMichal Meloun 102*b0352107SMichal Meloun /* Power up all secondary cores */ 103*b0352107SMichal Meloun val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON); 104*b0352107SMichal Meloun for (i = 1; i < mp_ncpus; i++) 105*b0352107SMichal Meloun val &= ~(1 << i); 106*b0352107SMichal Meloun bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val); 107*b0352107SMichal Meloun DELAY(5000); 108*b0352107SMichal Meloun 109*b0352107SMichal Meloun /* Copy mpentry address then magic to sram */ 110*b0352107SMichal Meloun val = pmap_kextract((vm_offset_t)mpentry); 111*b0352107SMichal Meloun bus_space_write_4(fdtbus_bs_tag, imem, 8, val); 112*b0352107SMichal Meloun dsb(); 113*b0352107SMichal Meloun bus_space_write_4(fdtbus_bs_tag, imem, 4, 0xDEADBEAF); 114*b0352107SMichal Meloun dsb(); 115*b0352107SMichal Meloun 116*b0352107SMichal Meloun sev(); 117*b0352107SMichal Meloun 118*b0352107SMichal Meloun bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE); 119*b0352107SMichal Meloun bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE); 120*b0352107SMichal Meloun } 121*b0352107SMichal Meloun 122*b0352107SMichal Meloun static boolean_t 123*b0352107SMichal Meloun rk32xx_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg) 124*b0352107SMichal Meloun { 125*b0352107SMichal Meloun int rv; 126*b0352107SMichal Meloun char method[16]; 127*b0352107SMichal Meloun uint32_t mask; 128*b0352107SMichal Meloun 129*b0352107SMichal Meloun if (!ofw_bus_node_status_okay(node)) 130*b0352107SMichal Meloun return(false); 131*b0352107SMichal Meloun 132*b0352107SMichal Meloun /* Skip boot CPU. */ 133*b0352107SMichal Meloun if (id == 0) 134*b0352107SMichal Meloun return (true); 135*b0352107SMichal Meloun 136*b0352107SMichal Meloun if (running_cpus >= mp_ncpus) 137*b0352107SMichal Meloun return (false); 138*b0352107SMichal Meloun running_cpus++; 139*b0352107SMichal Meloun 140*b0352107SMichal Meloun mask = 1 << (*reg & 0x0f); 141*b0352107SMichal Meloun 142*b0352107SMichal Meloun #ifdef INVARIANTS 143*b0352107SMichal Meloun if ((mask & pmu_mask) || (mask & psci_mask)) 144*b0352107SMichal Meloun printf("CPU: Duplicated register value: 0x%X for CPU(%d)\n", 145*b0352107SMichal Meloun *reg, id); 146*b0352107SMichal Meloun #endif 147*b0352107SMichal Meloun rv = OF_getprop(node, "enable-method", method, sizeof(method)); 148*b0352107SMichal Meloun if (rv > 0 && strcmp(method, "psci") == 0) { 149*b0352107SMichal Meloun psci_mask |= mask; 150*b0352107SMichal Meloun rv = psci_cpu_on(*reg, pmap_kextract((vm_offset_t)mpentry), id); 151*b0352107SMichal Meloun if (rv != PSCI_RETVAL_SUCCESS) { 152*b0352107SMichal Meloun printf("Failed to start CPU(%d)\n", id); 153*b0352107SMichal Meloun return (false); 154*b0352107SMichal Meloun } 155*b0352107SMichal Meloun return (true); 156*b0352107SMichal Meloun } 157*b0352107SMichal Meloun 158*b0352107SMichal Meloun pmu_mask |= mask; 159*b0352107SMichal Meloun return (true); 160*b0352107SMichal Meloun } 161*b0352107SMichal Meloun 162*b0352107SMichal Meloun void 163*b0352107SMichal Meloun rk32xx_mp_start_ap(platform_t plat) 164*b0352107SMichal Meloun { 165*b0352107SMichal Meloun 166*b0352107SMichal Meloun ofw_cpu_early_foreach(rk32xx_start_ap, true); 167*b0352107SMichal Meloun if (pmu_mask != 0 && psci_mask != 0) { 168*b0352107SMichal Meloun printf("Inconsistent CPUs startup methods detected.\n"); 169*b0352107SMichal Meloun printf("Only PSCI enabled cores will be started.\n"); 170*b0352107SMichal Meloun return; 171*b0352107SMichal Meloun } 172*b0352107SMichal Meloun if (pmu_mask != 0) 173*b0352107SMichal Meloun rk32xx_mp_start_pmu(pmu_mask); 174*b0352107SMichal Meloun } 175