xref: /freebsd/sys/arm/rockchip/rk32xx_mp.c (revision fdafd315ad0d0f28a11b9fb4476a9ab059c62b92)
1b0352107SMichal Meloun /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3b0352107SMichal Meloun  *
4b0352107SMichal Meloun  * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5b0352107SMichal Meloun  *
6b0352107SMichal Meloun  * Redistribution and use in source and binary forms, with or without
7b0352107SMichal Meloun  * modification, are permitted provided that the following conditions
8b0352107SMichal Meloun  * are met:
9b0352107SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
10b0352107SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
11b0352107SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
12b0352107SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
13b0352107SMichal Meloun  *    documentation and/or other materials provided with the distribution.
14b0352107SMichal Meloun  *
15b0352107SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16b0352107SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17b0352107SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18b0352107SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19b0352107SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20b0352107SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21b0352107SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22b0352107SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23b0352107SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24b0352107SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25b0352107SMichal Meloun  * SUCH DAMAGE.
26b0352107SMichal Meloun  */
27b0352107SMichal Meloun 
28b0352107SMichal Meloun #include <sys/param.h>
29b0352107SMichal Meloun #include <sys/systm.h>
30b0352107SMichal Meloun #include <sys/bus.h>
31b0352107SMichal Meloun #include <sys/kernel.h>
32b0352107SMichal Meloun #include <sys/lock.h>
33b0352107SMichal Meloun #include <sys/mutex.h>
34b0352107SMichal Meloun #include <sys/smp.h>
35b0352107SMichal Meloun 
36b0352107SMichal Meloun #include <vm/vm.h>
37b0352107SMichal Meloun #include <vm/pmap.h>
38b0352107SMichal Meloun 
39b0352107SMichal Meloun #include <machine/cpu.h>
40b0352107SMichal Meloun #include <machine/fdt.h>
41b0352107SMichal Meloun #include <machine/smp.h>
42b0352107SMichal Meloun #include <machine/platformvar.h>
43b0352107SMichal Meloun 
44b0352107SMichal Meloun #include <dev/ofw/openfirm.h>
45b0352107SMichal Meloun #include <dev/ofw/ofw_cpu.h>
46b0352107SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
47b0352107SMichal Meloun #include <dev/psci/psci.h>
48b0352107SMichal Meloun 
49b0352107SMichal Meloun #include <arm/rockchip/rk32xx_mp.h>
50b0352107SMichal Meloun 
51b0352107SMichal Meloun #define	IMEM_PHYSBASE			0xFF700000
52b0352107SMichal Meloun #define	IMEM_SIZE			0x00018000
53b0352107SMichal Meloun 
54b0352107SMichal Meloun #define	PMU_PHYSBASE			0xFF730000
55b0352107SMichal Meloun #define	PMU_SIZE			0x00010000
56b0352107SMichal Meloun #define	PMU_PWRDN_CON			0x08
57b0352107SMichal Meloun 
58b0352107SMichal Meloun static int running_cpus;
59b0352107SMichal Meloun static uint32_t psci_mask, pmu_mask;
60b0352107SMichal Meloun void
rk32xx_mp_setmaxid(platform_t plat)61b0352107SMichal Meloun rk32xx_mp_setmaxid(platform_t plat)
62b0352107SMichal Meloun {
63b0352107SMichal Meloun 	int ncpu;
64b0352107SMichal Meloun 
65b0352107SMichal Meloun 	/* If we've already set the global vars don't bother to do it again. */
66b0352107SMichal Meloun 	if (mp_ncpus != 0)
67b0352107SMichal Meloun 		return;
68b0352107SMichal Meloun 
69b0352107SMichal Meloun 	/* Read current CP15 Cache Size ID Register */
70b0352107SMichal Meloun 	ncpu = cp15_l2ctlr_get();
71b0352107SMichal Meloun 	ncpu = CPUV7_L2CTLR_NPROC(ncpu);
72b0352107SMichal Meloun 
73b0352107SMichal Meloun 	mp_ncpus = ncpu;
74b0352107SMichal Meloun 	mp_maxid = ncpu - 1;
75b0352107SMichal Meloun }
76b0352107SMichal Meloun 
77b0352107SMichal Meloun static void
rk32xx_mp_start_pmu(uint32_t mask)78b0352107SMichal Meloun rk32xx_mp_start_pmu(uint32_t mask)
79b0352107SMichal Meloun {
80b0352107SMichal Meloun 	bus_space_handle_t imem;
81b0352107SMichal Meloun 	bus_space_handle_t pmu;
82b0352107SMichal Meloun 	uint32_t val;
83b0352107SMichal Meloun 	int i, rv;
84b0352107SMichal Meloun 
85b0352107SMichal Meloun 	rv = bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE, IMEM_SIZE, 0, &imem);
86b0352107SMichal Meloun 	if (rv != 0)
87b0352107SMichal Meloun 		panic("Couldn't map the IMEM\n");
88b0352107SMichal Meloun 	rv = bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu);
89b0352107SMichal Meloun 	if (rv != 0)
90b0352107SMichal Meloun 		panic("Couldn't map the PMU\n");
91b0352107SMichal Meloun 
92b0352107SMichal Meloun 	/* Power off all secondary cores first */
93b0352107SMichal Meloun 	val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
94b0352107SMichal Meloun 	for (i = 1; i < mp_ncpus; i++)
95b0352107SMichal Meloun 		val |= 1 << i;
96b0352107SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
97b0352107SMichal Meloun 	DELAY(5000);
98b0352107SMichal Meloun 
99b0352107SMichal Meloun 	/* Power up all secondary cores */
100b0352107SMichal Meloun 	val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
101b0352107SMichal Meloun 	for (i = 1; i < mp_ncpus; i++)
102b0352107SMichal Meloun 		val &= ~(1 << i);
103b0352107SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
104b0352107SMichal Meloun 	DELAY(5000);
105b0352107SMichal Meloun 
106b0352107SMichal Meloun 	/* Copy mpentry address then magic to sram */
107b0352107SMichal Meloun 	val = pmap_kextract((vm_offset_t)mpentry);
108b0352107SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, imem, 8, val);
109b0352107SMichal Meloun 	dsb();
110b0352107SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, imem, 4, 0xDEADBEAF);
111b0352107SMichal Meloun 	dsb();
112b0352107SMichal Meloun 
113b0352107SMichal Meloun 	sev();
114b0352107SMichal Meloun 
115b0352107SMichal Meloun 	bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
116b0352107SMichal Meloun 	bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE);
117b0352107SMichal Meloun }
118b0352107SMichal Meloun 
119afdb4298SJohn Baldwin static bool
rk32xx_start_ap(u_int id,phandle_t node,u_int addr_cells,pcell_t * reg)120b0352107SMichal Meloun rk32xx_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *reg)
121b0352107SMichal Meloun {
122b0352107SMichal Meloun 	int rv;
123b0352107SMichal Meloun 	char method[16];
124b0352107SMichal Meloun 	uint32_t mask;
125b0352107SMichal Meloun 
126b0352107SMichal Meloun 	if (!ofw_bus_node_status_okay(node))
127b0352107SMichal Meloun 		return(false);
128b0352107SMichal Meloun 
129b0352107SMichal Meloun 	/* Skip boot CPU. */
130b0352107SMichal Meloun 	if (id == 0)
131b0352107SMichal Meloun 		return (true);
132b0352107SMichal Meloun 
133b0352107SMichal Meloun 	if (running_cpus >= mp_ncpus)
134b0352107SMichal Meloun 		return (false);
135b0352107SMichal Meloun 	running_cpus++;
136b0352107SMichal Meloun 
137b0352107SMichal Meloun 	mask = 1 << (*reg & 0x0f);
138b0352107SMichal Meloun 
139b0352107SMichal Meloun #ifdef INVARIANTS
140b0352107SMichal Meloun 	if ((mask & pmu_mask) || (mask & psci_mask))
141b0352107SMichal Meloun 		printf("CPU: Duplicated register value: 0x%X for CPU(%d)\n",
142b0352107SMichal Meloun 		    *reg, id);
143b0352107SMichal Meloun #endif
144b0352107SMichal Meloun 	rv = OF_getprop(node, "enable-method", method, sizeof(method));
145b0352107SMichal Meloun 	if (rv > 0 && strcmp(method, "psci") == 0) {
146b0352107SMichal Meloun 		psci_mask |= mask;
147b0352107SMichal Meloun 		rv = psci_cpu_on(*reg, pmap_kextract((vm_offset_t)mpentry), id);
148b0352107SMichal Meloun 		if (rv != PSCI_RETVAL_SUCCESS) {
149b0352107SMichal Meloun 			printf("Failed to start CPU(%d)\n", id);
150b0352107SMichal Meloun 			return (false);
151b0352107SMichal Meloun 		}
152b0352107SMichal Meloun 		return (true);
153b0352107SMichal Meloun 	}
154b0352107SMichal Meloun 
155b0352107SMichal Meloun 	pmu_mask |= mask;
156b0352107SMichal Meloun 	return (true);
157b0352107SMichal Meloun }
158b0352107SMichal Meloun 
159b0352107SMichal Meloun void
rk32xx_mp_start_ap(platform_t plat)160b0352107SMichal Meloun rk32xx_mp_start_ap(platform_t plat)
161b0352107SMichal Meloun {
162b0352107SMichal Meloun 
163b0352107SMichal Meloun 	ofw_cpu_early_foreach(rk32xx_start_ap, true);
164b0352107SMichal Meloun 	if (pmu_mask != 0 && psci_mask != 0) {
165b0352107SMichal Meloun 		printf("Inconsistent CPUs startup methods detected.\n");
166b0352107SMichal Meloun 		printf("Only PSCI enabled cores will be started.\n");
167b0352107SMichal Meloun 		return;
168b0352107SMichal Meloun 	}
169b0352107SMichal Meloun 	if (pmu_mask != 0)
170b0352107SMichal Meloun 		rk32xx_mp_start_pmu(pmu_mask);
171b0352107SMichal Meloun }
172