xref: /freebsd/sys/arm/qualcomm/qcom_scm_legacy.c (revision b9cd72b06d795a8c7b39df1f520e866ad7f11aa8)
1960e65d2SAdrian Chadd /*-
24d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3960e65d2SAdrian Chadd  *
4960e65d2SAdrian Chadd  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
5960e65d2SAdrian Chadd  *
6960e65d2SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
7960e65d2SAdrian Chadd  * modification, are permitted provided that the following conditions
8960e65d2SAdrian Chadd  * are met:
9960e65d2SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
10960e65d2SAdrian Chadd  *    notice, this list of conditions and the following disclaimer.
11960e65d2SAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
12960e65d2SAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
13960e65d2SAdrian Chadd  *    documentation and/or other materials provided with the distribution.
14960e65d2SAdrian Chadd  *
15960e65d2SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16960e65d2SAdrian Chadd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17960e65d2SAdrian Chadd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18960e65d2SAdrian Chadd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19960e65d2SAdrian Chadd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20960e65d2SAdrian Chadd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21960e65d2SAdrian Chadd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22960e65d2SAdrian Chadd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23960e65d2SAdrian Chadd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24960e65d2SAdrian Chadd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25960e65d2SAdrian Chadd  * SUCH DAMAGE.
26960e65d2SAdrian Chadd  */
27960e65d2SAdrian Chadd 
28960e65d2SAdrian Chadd #include "opt_platform.h"
29960e65d2SAdrian Chadd 
30960e65d2SAdrian Chadd #include <sys/param.h>
31960e65d2SAdrian Chadd #include <sys/systm.h>
32960e65d2SAdrian Chadd #include <sys/bus.h>
33960e65d2SAdrian Chadd #include <sys/reboot.h>
34960e65d2SAdrian Chadd #include <sys/devmap.h>
35960e65d2SAdrian Chadd #include <sys/smp.h>
36960e65d2SAdrian Chadd 
37960e65d2SAdrian Chadd #include <vm/vm.h>
38960e65d2SAdrian Chadd #include <vm/pmap.h>
39960e65d2SAdrian Chadd 
40960e65d2SAdrian Chadd #include <machine/cpu.h>
41960e65d2SAdrian Chadd #include <machine/bus.h>
42960e65d2SAdrian Chadd #include <machine/intr.h>
43960e65d2SAdrian Chadd #include <machine/machdep.h>
44960e65d2SAdrian Chadd #include <machine/smp.h>
45960e65d2SAdrian Chadd 
46960e65d2SAdrian Chadd #include <arm/qualcomm/qcom_scm_defs.h>
47960e65d2SAdrian Chadd #include <arm/qualcomm/qcom_scm_legacy_defs.h>
48960e65d2SAdrian Chadd #include <arm/qualcomm/qcom_scm_legacy.h>
49960e65d2SAdrian Chadd 
50960e65d2SAdrian Chadd #include <dev/psci/smccc.h>
51960e65d2SAdrian Chadd 
52960e65d2SAdrian Chadd /*
53960e65d2SAdrian Chadd  * Set the cold boot address for (later) a mask of CPUs.
54960e65d2SAdrian Chadd  *
55960e65d2SAdrian Chadd  * Don't set it for CPU0, that CPU is the boot CPU and is already alive.
56960e65d2SAdrian Chadd  *
57960e65d2SAdrian Chadd  * For now it sets it on CPU1..3.
58960e65d2SAdrian Chadd  *
59960e65d2SAdrian Chadd  * This works on the IPQ4019 as tested; the retval is 0x0.
60960e65d2SAdrian Chadd  */
61960e65d2SAdrian Chadd uint32_t
qcom_scm_legacy_mp_set_cold_boot_address(vm_offset_t mp_entry_func)62960e65d2SAdrian Chadd qcom_scm_legacy_mp_set_cold_boot_address(vm_offset_t mp_entry_func)
63960e65d2SAdrian Chadd {
64960e65d2SAdrian Chadd 	struct arm_smccc_res res;
65960e65d2SAdrian Chadd 	int ret;
66960e65d2SAdrian Chadd 	int context_id;
67960e65d2SAdrian Chadd 
68960e65d2SAdrian Chadd 	uint32_t scm_arg0 = QCOM_SCM_LEGACY_ATOMIC_ID(QCOM_SCM_SVC_BOOT,
69960e65d2SAdrian Chadd 	    QCOM_SCM_BOOT_SET_ADDR, 2);
70960e65d2SAdrian Chadd 
71960e65d2SAdrian Chadd 	uint32_t scm_arg1 = QCOM_SCM_FLAG_COLDBOOT_CPU1
72960e65d2SAdrian Chadd 	    | QCOM_SCM_FLAG_COLDBOOT_CPU2
73960e65d2SAdrian Chadd 	    | QCOM_SCM_FLAG_COLDBOOT_CPU3;
74960e65d2SAdrian Chadd 	uint32_t scm_arg2 = pmap_kextract((vm_offset_t)mp_entry_func);
75960e65d2SAdrian Chadd 
76*b9cd72b0SAndrew Turner 	ret = arm_smccc_invoke_smc(scm_arg0, (uint32_t) &context_id, scm_arg1,
77*b9cd72b0SAndrew Turner 	    scm_arg2, &res);
78960e65d2SAdrian Chadd 
79960e65d2SAdrian Chadd 	if (ret == 0 && res.a0 == 0)
80960e65d2SAdrian Chadd 		return (0);
81960e65d2SAdrian Chadd 	printf("%s: called; error; ret=0x%08x; retval[0]=0x%08x\n",
82960e65d2SAdrian Chadd 	    __func__, ret, res.a0);
83960e65d2SAdrian Chadd 
84960e65d2SAdrian Chadd 	return (0);
85960e65d2SAdrian Chadd }
86