1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef __QCOM_CPU_KPSSV2_REG_H__ 29 #define __QCOM_CPU_KPSSV2_REG_H__ 30 31 32 /* 33 * APCS CPU core regulator registers. 34 */ 35 #define QCOM_APCS_CPU_PWR_CTL 0x04 36 #define QCOM_APCS_CPU_PWR_CTL_PLL_CLAMP (1U << 8) 37 #define QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP (1U << 7) 38 #define QCOM_APCS_CPU_PWR_CTL_COREPOR_RST (1U << 5) 39 #define QCOM_APCS_CPU_PWR_CTL_CORE_RST (1U << 4) 40 #define QCOM_APCS_CPU_PWR_CTL_L2DT_SLP (1U << 3) 41 #define QCOM_APCS_CPU_PWR_CTL_CLAMP (1U << 0) 42 43 #define QCOM_APC_PWR_GATE_CTL 0x14 44 #define QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT 24 45 #define QCOM_APC_PWR_GATE_CTL_LDO_PWR_DWN_SHIFT 16 46 #define QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT 8 47 #define QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT 1 48 #define QCOM_APC_PWR_GATE_CTL_BHS_EN (1U << 0) 49 50 51 /* 52 * L2 cache regulator registers. 53 */ 54 #define QCOM_APCS_SAW2_2_VCTL 0x1c 55 56 #endif /* __QCOM_CPU_KPSSV2_REG_H__ */ 57