1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/reboot.h> 34 #include <sys/devmap.h> 35 #include <sys/smp.h> 36 37 #include <vm/vm.h> 38 39 #include <machine/cpu.h> 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 #include <machine/machdep.h> 43 #include <machine/platformvar.h> 44 #include <machine/smp.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_cpu.h> 49 50 #include <arm/qualcomm/qcom_cpu_kpssv2_reg.h> 51 #include <arm/qualcomm/qcom_cpu_kpssv2.h> 52 53 #include "platform_if.h" 54 55 /* 56 * Since DELAY() hangs this early, we need some way to 57 * delay things to settle. 58 */ 59 static inline void 60 loop_delay(int usec) 61 { 62 int lcount = usec * 100000; 63 64 for (volatile int i = 0; i < lcount; i++) 65 ; 66 } 67 68 /* 69 * This is the KPSSv2 (eg IPQ4018) regulator path for CPU 70 * and shared L2 cache power-on. 71 */ 72 bool 73 qcom_cpu_kpssv2_regulator_start(u_int id, phandle_t node) 74 { 75 phandle_t acc_phandle, l2_phandle, saw_phandle; 76 bus_space_tag_t acc_tag, saw_tag; 77 bus_space_handle_t acc_handle, saw_handle; 78 bus_size_t acc_sz, saw_sz; 79 ssize_t sret; 80 int ret; 81 uint32_t reg_val; 82 83 /* 84 * We don't need to power up CPU 0! This will power it 85 * down first and ... then everything hangs. 86 */ 87 if (id == 0) 88 return true; 89 90 /* 91 * Walk the qcom,acc and next-level-cache entries to find their 92 * child phandles and thus regulators. 93 * 94 * The qcom,acc is a phandle to a node. 95 * 96 * The next-level-cache actually is a phandle through to a qcom,saw 97 * entry. 98 */ 99 sret = OF_getencprop(node, "qcom,acc", (void *) &acc_phandle, 100 sizeof(acc_phandle)); 101 if (sret != sizeof(acc_phandle)) 102 panic("***couldn't get phandle for qcom,acc"); 103 acc_phandle = OF_node_from_xref(acc_phandle); 104 105 sret = OF_getencprop(node, "next-level-cache", (void *) &l2_phandle, 106 sizeof(l2_phandle)); 107 if (sret != sizeof(l2_phandle)) 108 panic("***couldn't get phandle for next-level-cache"); 109 l2_phandle = OF_node_from_xref(l2_phandle); 110 111 sret = OF_getencprop(l2_phandle, "qcom,saw", (void *) &saw_phandle, 112 sizeof(saw_phandle)); 113 if (sret != sizeof(saw_phandle)) 114 panic("***couldn't get phandle for qcom,saw"); 115 l2_phandle = OF_node_from_xref(l2_phandle); 116 117 /* 118 * Now that we have the phandles referencing the correct locations, 119 * do some KVA mappings so we can go access the registers. 120 */ 121 ret = OF_decode_addr(acc_phandle, 0, &acc_tag, &acc_handle, &acc_sz); 122 if (ret != 0) 123 panic("*** couldn't map qcom,acc space (%d)", ret); 124 ret = OF_decode_addr(saw_phandle, 0, &saw_tag, &saw_handle, &saw_sz); 125 if (ret != 0) 126 panic("*** couldn't map next-level-cache -> " 127 "qcom,saw space (%d)", ret); 128 129 /* 130 * Power sequencing to ensure the cores are off, then power them on 131 * and bring them out of reset. 132 */ 133 134 /* 135 * BHS: off 136 * LDO: bypassed, powered off 137 */ 138 reg_val = (64 << QCOM_APC_PWR_GATE_CTL_BHS_CNT_SHIFT) 139 | (0x3f << QCOM_APC_PWR_GATE_CTL_LDO_PWR_DWN_SHIFT) 140 | QCOM_APC_PWR_GATE_CTL_BHS_EN; 141 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); 142 mb(); 143 /* Settle time */ 144 loop_delay(1); 145 146 /* 147 * Start up BHS segments. 148 */ 149 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_BHS_SEG_SHIFT; 150 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); 151 mb(); 152 /* Settle time */ 153 loop_delay(1); 154 155 /* 156 * Switch on the LDO bypass; BHS will now supply power. 157 */ 158 reg_val |= 0x3f << QCOM_APC_PWR_GATE_CTL_LDO_BYP_SHIFT; 159 bus_space_write_4(acc_tag, acc_handle, QCOM_APC_PWR_GATE_CTL, reg_val); 160 161 /* 162 * Shared L2 regulator control. 163 */ 164 bus_space_write_4(saw_tag, saw_handle, QCOM_APCS_SAW2_2_VCTL, 0x10003); 165 mb(); 166 /* Settle time */ 167 loop_delay(50); 168 169 /* 170 * Put the core in reset. 171 */ 172 reg_val = QCOM_APCS_CPU_PWR_CTL_COREPOR_RST 173 | QCOM_APCS_CPU_PWR_CTL_CLAMP; 174 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val); 175 mb(); 176 loop_delay(2); 177 178 /* 179 * Remove power-down clamp. 180 */ 181 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_CLAMP; 182 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val); 183 mb(); 184 loop_delay(2); 185 186 /* 187 * Clear core power reset. 188 */ 189 reg_val &= ~QCOM_APCS_CPU_PWR_CTL_COREPOR_RST; 190 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val); 191 mb(); 192 193 /* 194 * The power is ready, the core is out of reset, signal the core 195 * to power up. 196 */ 197 reg_val |= QCOM_APCS_CPU_PWR_CTL_CORE_PWRD_UP; 198 bus_space_write_4(acc_tag, acc_handle, QCOM_APCS_CPU_PWR_CTL, reg_val); 199 mb(); 200 201 /* 202 * Finished with these KVA mappings, so release them. 203 */ 204 bus_space_unmap(acc_tag, acc_handle, acc_sz); 205 bus_space_unmap(saw_tag, saw_handle, saw_sz); 206 207 return true; 208 } 209