xref: /freebsd/sys/arm/qualcomm/ipq4018_mp.c (revision fdafd315ad0d0f28a11b9fb4476a9ab059c62b92)
102438ce5SAdrian Chadd /*-
2*4d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
302438ce5SAdrian Chadd  *
402438ce5SAdrian Chadd  * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
502438ce5SAdrian Chadd  *
602438ce5SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
702438ce5SAdrian Chadd  * modification, are permitted provided that the following conditions
802438ce5SAdrian Chadd  * are met:
902438ce5SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
1002438ce5SAdrian Chadd  *    notice, this list of conditions and the following disclaimer.
1102438ce5SAdrian Chadd  * 2. Redistributions in binary form must reproduce the above copyright
1202438ce5SAdrian Chadd  *    notice, this list of conditions and the following disclaimer in the
1302438ce5SAdrian Chadd  *    documentation and/or other materials provided with the distribution.
1402438ce5SAdrian Chadd  *
1502438ce5SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1602438ce5SAdrian Chadd  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1702438ce5SAdrian Chadd  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1802438ce5SAdrian Chadd  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1902438ce5SAdrian Chadd  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2002438ce5SAdrian Chadd  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2102438ce5SAdrian Chadd  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2202438ce5SAdrian Chadd  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2302438ce5SAdrian Chadd  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2402438ce5SAdrian Chadd  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2502438ce5SAdrian Chadd  * SUCH DAMAGE.
2602438ce5SAdrian Chadd  */
2702438ce5SAdrian Chadd 
2802438ce5SAdrian Chadd #include "opt_platform.h"
2902438ce5SAdrian Chadd 
3002438ce5SAdrian Chadd #include <sys/param.h>
3102438ce5SAdrian Chadd #include <sys/systm.h>
3202438ce5SAdrian Chadd #include <sys/bus.h>
3302438ce5SAdrian Chadd #include <sys/reboot.h>
3402438ce5SAdrian Chadd #include <sys/devmap.h>
35d3514c29SAdrian Chadd #include <sys/smp.h>
3602438ce5SAdrian Chadd 
3702438ce5SAdrian Chadd #include <vm/vm.h>
3802438ce5SAdrian Chadd 
39d3514c29SAdrian Chadd #include <machine/cpu.h>
4002438ce5SAdrian Chadd #include <machine/bus.h>
4102438ce5SAdrian Chadd #include <machine/intr.h>
4202438ce5SAdrian Chadd #include <machine/machdep.h>
4302438ce5SAdrian Chadd #include <machine/platformvar.h>
44d3514c29SAdrian Chadd #include <machine/smp.h>
4502438ce5SAdrian Chadd 
4602438ce5SAdrian Chadd #include <dev/fdt/fdt_common.h>
4702438ce5SAdrian Chadd #include <dev/ofw/openfirm.h>
48d3514c29SAdrian Chadd #include <dev/ofw/ofw_cpu.h>
4902438ce5SAdrian Chadd 
5002438ce5SAdrian Chadd #include <arm/qualcomm/ipq4018_machdep.h>
51d3514c29SAdrian Chadd #include <arm/qualcomm/qcom_scm_legacy.h>
52d3514c29SAdrian Chadd #include <arm/qualcomm/qcom_cpu_kpssv2.h>
5302438ce5SAdrian Chadd 
5402438ce5SAdrian Chadd #include "platform_if.h"
5502438ce5SAdrian Chadd 
5602438ce5SAdrian Chadd void
ipq4018_mp_setmaxid(platform_t plat)5702438ce5SAdrian Chadd ipq4018_mp_setmaxid(platform_t plat)
5802438ce5SAdrian Chadd {
59d3514c29SAdrian Chadd 	int ncpu;
60d3514c29SAdrian Chadd 
61d3514c29SAdrian Chadd 	/* If we've already set the global vars don't bother to do it again. */
62d3514c29SAdrian Chadd 	if (mp_ncpus != 0)
63d3514c29SAdrian Chadd 		return;
64d3514c29SAdrian Chadd 
65d3514c29SAdrian Chadd 	/* Read current CP15 Cache Size ID Register */
66d3514c29SAdrian Chadd 	ncpu = cp15_l2ctlr_get();
67d3514c29SAdrian Chadd 	ncpu = CPUV7_L2CTLR_NPROC(ncpu);
68d3514c29SAdrian Chadd 
69d3514c29SAdrian Chadd 	mp_ncpus = ncpu;
70d3514c29SAdrian Chadd 	mp_maxid = ncpu - 1;
71d3514c29SAdrian Chadd 
72d3514c29SAdrian Chadd 	printf("SMP: ncpu=%d\n", ncpu);
73d3514c29SAdrian Chadd }
74d3514c29SAdrian Chadd 
75afdb4298SJohn Baldwin static bool
ipq4018_start_ap(u_int id,phandle_t node,u_int addr_cells,pcell_t * arg)76d3514c29SAdrian Chadd ipq4018_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *arg)
77d3514c29SAdrian Chadd {
78d3514c29SAdrian Chadd 
79d3514c29SAdrian Chadd 	/*
80d3514c29SAdrian Chadd 	 * For the IPQ401x we assume the enable method is
81d3514c29SAdrian Chadd 	 * "qcom,kpss-acc-v2".  If this path gets turned into
82d3514c29SAdrian Chadd 	 * something more generic for other 32 bit qualcomm
83d3514c29SAdrian Chadd 	 * SoCs then we'll likely want to turn this into a
84d3514c29SAdrian Chadd 	 * switch based on "enable-method".
85d3514c29SAdrian Chadd 	 */
86d3514c29SAdrian Chadd 	return qcom_cpu_kpssv2_regulator_start(id, node);
8702438ce5SAdrian Chadd }
8802438ce5SAdrian Chadd 
8902438ce5SAdrian Chadd void
ipq4018_mp_start_ap(platform_t plat)9002438ce5SAdrian Chadd ipq4018_mp_start_ap(platform_t plat)
9102438ce5SAdrian Chadd {
92d3514c29SAdrian Chadd 	int ret;
93d3514c29SAdrian Chadd 
94d3514c29SAdrian Chadd 	/*
95d3514c29SAdrian Chadd 	 * First step - SCM call to set the cold boot address to mpentry, so
96d3514c29SAdrian Chadd 	 * CPUs hopefully start in the MP path.
97d3514c29SAdrian Chadd 	 */
98d3514c29SAdrian Chadd 	ret = qcom_scm_legacy_mp_set_cold_boot_address((vm_offset_t) mpentry);
99d3514c29SAdrian Chadd 	if (ret != 0)
100d3514c29SAdrian Chadd 		panic("%s: Couldn't set cold boot address via SCM "
101d3514c29SAdrian Chadd 		    "(error 0x%08x)", __func__, ret);
102d3514c29SAdrian Chadd 
103d3514c29SAdrian Chadd 	/*
104d3514c29SAdrian Chadd 	 * Next step - loop over the CPU nodes and do the per-CPU setup
105d3514c29SAdrian Chadd 	 * required to power on the CPUs themselves.
106d3514c29SAdrian Chadd 	 */
107d3514c29SAdrian Chadd 	ofw_cpu_early_foreach(ipq4018_start_ap, true);
108d3514c29SAdrian Chadd 
109d3514c29SAdrian Chadd 	/*
110d3514c29SAdrian Chadd 	 * The next set of IPIs to the CPUs will wake them up and enter
111d3514c29SAdrian Chadd 	 * mpentry.
112d3514c29SAdrian Chadd 	 */
11302438ce5SAdrian Chadd }
114