1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/reboot.h> 35 #include <sys/devmap.h> 36 #include <sys/physmem.h> 37 #include <sys/lock.h> 38 39 #include <vm/vm.h> 40 41 #include <machine/bus.h> 42 #include <machine/fdt.h> 43 #include <machine/intr.h> 44 #include <machine/machdep.h> 45 #include <machine/platformvar.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/openfirm.h> 49 50 #include <arm/qualcomm/ipq4018_machdep.h> 51 #include <arm/qualcomm/ipq4018_reg.h> 52 53 #include "platform_if.h" 54 55 static int 56 ipq4018_attach(platform_t plat) 57 { 58 return (0); 59 } 60 61 static void 62 ipq4018_late_init(platform_t plat) 63 { 64 /* 65 * XXX FIXME This is needed because we're not parsing 66 * the fdt reserved memory regions in a consistent way 67 * between arm/arm64. Once the reserved region parsing 68 * is fixed up this will become unneccessary. 69 * 70 * These cover the SRAM/TZ regions that are not fully 71 * accessible from the OS. They're in the ipq4018.dtsi 72 * tree. 73 * 74 * Without these, the system fails to boot because we 75 * aren't parsing the regions correctly. 76 * 77 * These will be unnecessary once the parser and setup 78 * code is fixed. 79 */ 80 physmem_exclude_region(IPQ4018_MEM_SMEM_START, 81 IPQ4018_MEM_SMEM_SIZE, 82 EXFLAG_NODUMP | EXFLAG_NOALLOC); 83 physmem_exclude_region(IPQ4018_MEM_TZ_START, 84 IPQ4018_MEM_TZ_SIZE, 85 EXFLAG_NODUMP | EXFLAG_NOALLOC); 86 } 87 88 static int 89 ipq4018_devmap_init(platform_t plat) 90 { 91 /* 92 * This covers the boot UART. Without it we can't boot successfully: 93 * there's a mutex uninit panic in subr_vmem.c that occurs when doing 94 * a call to pmap_mapdev() when the bus space code is doing its thing. 95 */ 96 devmap_add_entry(IPQ4018_MEM_UART1_START, IPQ4018_MEM_UART1_SIZE); 97 98 /* 99 * This covers a bunch of the reset block, which includes the PS-HOLD 100 * register for dropping power. 101 */ 102 devmap_add_entry(IPQ4018_MEM_PSHOLD_START, IPQ4018_MEM_PSHOLD_SIZE); 103 104 return (0); 105 } 106 107 /* 108 * This toggles the PS-HOLD register which on most IPQ devices will toggle 109 * the power control block and reset the SoC. 110 * 111 * However, there are apparently some units out there where this is not 112 * appropriate and instead the watchdog needs to be used. 113 * 114 * For now since there's only going to be one or two initial supported boards 115 * this will be fine. But if this doesn't reboot cleanly, now you know. 116 */ 117 static void 118 ipq4018_cpu_reset_pshold(void) 119 { 120 bus_space_handle_t pshold; 121 122 printf("%s: called\n", __func__); 123 124 bus_space_map(fdtbus_bs_tag, IPQ4018_MEM_PSHOLD_START, 125 IPQ4018_MEM_PSHOLD_SIZE, 0, &pshold); 126 bus_space_write_4(fdtbus_bs_tag, pshold, 0, 0); 127 bus_space_barrier(fdtbus_bs_tag, pshold, 0, 0x4, 128 BUS_SPACE_BARRIER_WRITE); 129 } 130 131 static void 132 ipq4018_cpu_reset(platform_t plat) 133 { 134 spinlock_enter(); 135 dsb(); 136 137 ipq4018_cpu_reset_pshold(); 138 139 /* Spin */ 140 printf("%s: spinning\n", __func__); 141 while(1) 142 ; 143 } 144 145 /* 146 * Early putc routine for EARLY_PRINTF support. To use, add to kernel config: 147 * option SOCDEV_PA=0x07800000 148 * option SOCDEV_VA=0x07800000 149 * option EARLY_PRINTF 150 * Resist the temptation to change the #if 0 to #ifdef EARLY_PRINTF here. It 151 * makes sense now, but if multiple SOCs do that it will make early_putc another 152 * duplicate symbol to be eliminated on the path to a generic kernel. 153 */ 154 #if 0 155 void 156 qca_msm_early_putc(int c) 157 { 158 static int is_init = 0; 159 160 int limit; 161 /* 162 * This must match what's put into SOCDEV_VA. You have to change them 163 * both together. 164 * 165 * XXX TODO I should really go and just make UART_BASE here depend upon 166 * SOCDEV_VA so they move together. 167 */ 168 #define UART_BASE IPQ4018_MEM_UART1_START 169 volatile uint32_t * UART_DM_TF0 = (uint32_t *)(UART_BASE + 0x70); 170 volatile uint32_t * UART_DM_SR = (uint32_t *)(UART_BASE + 0x08); 171 #define UART_DM_SR_TXEMT (1 << 3) 172 #define UART_DM_SR_TXRDY (1 << 2) 173 volatile uint32_t * UART_DM_ISR = (uint32_t *)(UART_BASE + 0x14); 174 volatile uint32_t * UART_DM_CR = (uint32_t *)(UART_BASE + 0x10); 175 #define UART_DM_TX_READY (1 << 7) 176 #define UART_DM_CLEAR_TX_READY 0x300 177 volatile uint32_t * UART_DM_NO_CHARS_FOR_TX = (uint32_t *)(UART_BASE + 0x40); 178 volatile uint32_t * UART_DM_TFWR = (uint32_t *)(UART_BASE + 0x1c); 179 #define UART_DM_TFW_VALUE 0 180 volatile uint32_t * UART_DM_IPR = (uint32_t *)(UART_BASE + 0x18); 181 #define UART_DM_STALE_TIMEOUT_LSB 0xf 182 183 if (is_init == 0) { 184 is_init = 1; 185 *UART_DM_TFWR = UART_DM_TFW_VALUE; 186 wmb(); 187 *UART_DM_IPR = UART_DM_STALE_TIMEOUT_LSB; 188 wmb(); 189 } 190 191 /* Wait until TXFIFO is empty via ISR */ 192 limit = 100000; 193 if ((*UART_DM_SR & UART_DM_SR_TXEMT) == 0) { 194 while (((*UART_DM_ISR & UART_DM_TX_READY) == 0) && --limit) { 195 /* Note - can't use DELAY here yet, too early */ 196 rmb(); 197 } 198 *UART_DM_CR = UART_DM_CLEAR_TX_READY; 199 wmb(); 200 } 201 202 /* FIFO is ready. Say we're going to write one byte */ 203 *UART_DM_NO_CHARS_FOR_TX = 1; 204 wmb(); 205 206 limit = 100000; 207 while (((*UART_DM_SR & UART_DM_SR_TXRDY) == 0) && --limit) { 208 /* Note - can't use DELAY here yet, too early */ 209 rmb(); 210 } 211 212 /* Put character in first fifo slot */ 213 *UART_DM_TF0 = c; 214 wmb(); 215 } 216 early_putc_t *early_putc = qca_msm_early_putc; 217 #endif 218 219 static platform_method_t ipq4018_methods[] = { 220 PLATFORMMETHOD(platform_attach, ipq4018_attach), 221 PLATFORMMETHOD(platform_devmap_init, ipq4018_devmap_init), 222 PLATFORMMETHOD(platform_late_init, ipq4018_late_init), 223 PLATFORMMETHOD(platform_cpu_reset, ipq4018_cpu_reset), 224 225 #ifdef SMP 226 PLATFORMMETHOD(platform_mp_start_ap, ipq4018_mp_start_ap), 227 PLATFORMMETHOD(platform_mp_setmaxid, ipq4018_mp_setmaxid), 228 #endif 229 230 PLATFORMMETHOD_END, 231 }; 232 233 FDT_PLATFORM_DEF2(ipq4018, ipq4018_ac58u, "ASUS RT-AC58U", 0, 234 "asus,rt-ac58u", 80); 235