1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * XHCI driver for Tegra SoCs. 30 */ 31 #include "opt_bus.h" 32 #include "opt_platform.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/clock.h> 37 #include <sys/condvar.h> 38 #include <sys/firmware.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/systm.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 #include <vm/pmap.h> 51 52 #include <machine/bus.h> 53 #include <machine/resource.h> 54 55 #include <dev/clk/clk.h> 56 #include <dev/hwreset/hwreset.h> 57 #include <dev/phy/phy.h> 58 #include <dev/regulator/regulator.h> 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usb_busdma.h> 64 #include <dev/usb/usb_process.h> 65 #include <dev/usb/usb_controller.h> 66 #include <dev/usb/usb_bus.h> 67 #include <dev/usb/controller/xhci.h> 68 #include <dev/usb/controller/xhcireg.h> 69 70 #include <arm/nvidia/tegra_pmc.h> 71 72 #include "usbdevs.h" 73 74 /* FPCI address space */ 75 #define T_XUSB_CFG_0 0x000 76 #define T_XUSB_CFG_1 0x004 77 #define CFG_1_BUS_MASTER (1 << 2) 78 #define CFG_1_MEMORY_SPACE (1 << 1) 79 #define CFG_1_IO_SPACE (1 << 0) 80 81 #define T_XUSB_CFG_2 0x008 82 #define T_XUSB_CFG_3 0x00C 83 #define T_XUSB_CFG_4 0x010 84 #define CFG_4_BASE_ADDRESS(x) (((x) & 0x1FFFF) << 15) 85 86 #define T_XUSB_CFG_5 0x014 87 #define T_XUSB_CFG_ARU_MAILBOX_CMD 0x0E4 88 #define ARU_MAILBOX_CMD_INT_EN (1U << 31) 89 #define ARU_MAILBOX_CMD_DEST_XHCI (1 << 30) 90 #define ARU_MAILBOX_CMD_DEST_SMI (1 << 29) 91 #define ARU_MAILBOX_CMD_DEST_PME (1 << 28) 92 #define ARU_MAILBOX_CMD_DEST_FALC (1 << 27) 93 94 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN 0x0E8 95 #define ARU_MAILBOX_DATA_IN_DATA(x) (((x) & 0xFFFFFF) << 0) 96 #define ARU_MAILBOX_DATA_IN_TYPE(x) (((x) & 0x0000FF) << 24) 97 98 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT 0x0EC 99 #define ARU_MAILBOX_DATA_OUT_DATA(x) (((x) >> 0) & 0xFFFFFF) 100 #define ARU_MAILBOX_DATA_OUT_TYPE(x) (((x) >> 24) & 0x0000FF) 101 102 #define T_XUSB_CFG_ARU_MAILBOX_OWNER 0x0F0 103 #define ARU_MAILBOX_OWNER_SW 2 104 #define ARU_MAILBOX_OWNER_FW 1 105 #define ARU_MAILBOX_OWNER_NONE 0 106 107 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41C /* ! UNDOCUMENTED ! */ 108 #define ARU_C11_CSBRANGE_PAGE(x) ((x) >> 9) 109 #define ARU_C11_CSBRANGE_ADDR(x) (0x800 + ((x) & 0x1FF)) 110 #define XUSB_CFG_ARU_SMI_INTR 0x428 /* ! UNDOCUMENTED ! */ 111 #define ARU_SMI_INTR_EN (1 << 3) 112 #define ARU_SMI_INTR_FW_HANG (1 << 1) 113 #define XUSB_CFG_ARU_RST 0x42C /* ! UNDOCUMENTED ! */ 114 #define ARU_RST_RESET (1 << 0) 115 116 #define XUSB_HOST_CONFIGURATION 0x180 117 #define CONFIGURATION_CLKEN_OVERRIDE (1U<< 31) 118 #define CONFIGURATION_PW_NO_DEVSEL_ERR_CYA (1 << 19) 119 #define CONFIGURATION_INITIATOR_READ_IDLE (1 << 18) 120 #define CONFIGURATION_INITIATOR_WRITE_IDLE (1 << 17) 121 #define CONFIGURATION_WDATA_LEAD_CYA (1 << 15) 122 #define CONFIGURATION_WR_INTRLV_CYA (1 << 14) 123 #define CONFIGURATION_TARGET_READ_IDLE (1 << 11) 124 #define CONFIGURATION_TARGET_WRITE_IDLE (1 << 10) 125 #define CONFIGURATION_MSI_VEC_EMPTY (1 << 9) 126 #define CONFIGURATION_UFPCI_MSIAW (1 << 7) 127 #define CONFIGURATION_UFPCI_PWPASSPW (1 << 6) 128 #define CONFIGURATION_UFPCI_PASSPW (1 << 5) 129 #define CONFIGURATION_UFPCI_PWPASSNPW (1 << 4) 130 #define CONFIGURATION_DFPCI_PWPASSNPW (1 << 3) 131 #define CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) 132 #define CONFIGURATION_DFPCI_PASSPW (1 << 1) 133 #define CONFIGURATION_EN_FPCI (1 << 0) 134 135 /* IPFS address space */ 136 #define XUSB_HOST_FPCI_ERROR_MASKS 0x184 137 #define FPCI_ERROR_MASTER_ABORT (1 << 2) 138 #define FPCI_ERRORI_DATA_ERROR (1 << 1) 139 #define FPCI_ERROR_TARGET_ABORT (1 << 0) 140 141 #define XUSB_HOST_INTR_MASK 0x188 142 #define INTR_IP_INT_MASK (1 << 16) 143 #define INTR_MSI_MASK (1 << 8) 144 #define INTR_INT_MASK (1 << 0) 145 146 #define XUSB_HOST_CLKGATE_HYSTERESIS 0x1BC 147 148 /* CSB Falcon CPU */ 149 #define XUSB_FALCON_CPUCTL 0x100 150 #define CPUCTL_STOPPED (1 << 5) 151 #define CPUCTL_HALTED (1 << 4) 152 #define CPUCTL_HRESET (1 << 3) 153 #define CPUCTL_SRESET (1 << 2) 154 #define CPUCTL_STARTCPU (1 << 1) 155 #define CPUCTL_IINVAL (1 << 0) 156 157 #define XUSB_FALCON_BOOTVEC 0x104 158 #define XUSB_FALCON_DMACTL 0x10C 159 #define XUSB_FALCON_IMFILLRNG1 0x154 160 #define IMFILLRNG1_TAG_HI(x) (((x) & 0xFFF) << 16) 161 #define IMFILLRNG1_TAG_LO(x) (((x) & 0xFFF) << 0) 162 #define XUSB_FALCON_IMFILLCTL 0x158 163 164 /* CSB mempool */ 165 #define XUSB_CSB_MEMPOOL_APMAP 0x10181C 166 #define APMAP_BOOTPATH (1U << 31) 167 168 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR 0x101A00 169 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO 0x101A04 170 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI 0x101A08 171 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE 0x101A10 172 #define L2IMEMOP_SIZE_OFFSET(x) (((x) & 0x3FF) << 8) 173 #define L2IMEMOP_SIZE_SIZE(x) (((x) & 0x0FF) << 24) 174 175 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG 0x101A14 176 #define L2IMEMOP_INVALIDATE_ALL (0x40 << 24) 177 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << 24) 178 179 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101A18 180 #define L2IMEMOP_RESULT_VLD (1U << 31) 181 182 #define XUSB_CSB_IMEM_BLOCK_SIZE 256 183 184 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 185 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 186 187 /* MBOX commands. */ 188 #define MBOX_CMD_MSG_ENABLED 1 189 #define MBOX_CMD_INC_FALC_CLOCK 2 190 #define MBOX_CMD_DEC_FALC_CLOCK 3 191 #define MBOX_CMD_INC_SSPI_CLOCK 4 192 #define MBOX_CMD_DEC_SSPI_CLOCK 5 193 #define MBOX_CMD_SET_BW 6 194 #define MBOX_CMD_SET_SS_PWR_GATING 7 195 #define MBOX_CMD_SET_SS_PWR_UNGATING 8 196 #define MBOX_CMD_SAVE_DFE_CTLE_CTX 9 197 #define MBOX_CMD_AIRPLANE_MODE_ENABLED 10 198 #define MBOX_CMD_AIRPLANE_MODE_DISABLED 11 199 #define MBOX_CMD_START_HSIC_IDLE 12 200 #define MBOX_CMD_STOP_HSIC_IDLE 13 201 #define MBOX_CMD_DBC_WAKE_STACK 14 202 #define MBOX_CMD_HSIC_PRETEND_CONNECT 15 203 #define MBOX_CMD_RESET_SSPI 16 204 #define MBOX_CMD_DISABLE_SS_LFPS_DETECTION 17 205 #define MBOX_CMD_ENABLE_SS_LFPS_DETECTION 18 206 207 /* MBOX responses. */ 208 #define MBOX_CMD_ACK (0x80 + 0) 209 #define MBOX_CMD_NAK (0x80 + 1) 210 211 #define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v)) 212 #define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r)) 213 #define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v)) 214 #define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r)) 215 216 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) 217 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 218 #define SLEEP(_sc, timeout) \ 219 mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout); 220 #define LOCK_INIT(_sc) \ 221 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_xhci", MTX_DEF) 222 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 223 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 224 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 225 226 struct tegra_xusb_fw_hdr { 227 uint32_t boot_loadaddr_in_imem; 228 uint32_t boot_codedfi_offset; 229 uint32_t boot_codetag; 230 uint32_t boot_codesize; 231 232 uint32_t phys_memaddr; 233 uint16_t reqphys_memsize; 234 uint16_t alloc_phys_memsize; 235 236 uint32_t rodata_img_offset; 237 uint32_t rodata_section_start; 238 uint32_t rodata_section_end; 239 uint32_t main_fnaddr; 240 241 uint32_t fwimg_cksum; 242 uint32_t fwimg_created_time; 243 244 uint32_t imem_resident_start; 245 uint32_t imem_resident_end; 246 uint32_t idirect_start; 247 uint32_t idirect_end; 248 uint32_t l2_imem_start; 249 uint32_t l2_imem_end; 250 uint32_t version_id; 251 uint8_t init_ddirect; 252 uint8_t reserved[3]; 253 uint32_t phys_addr_log_buffer; 254 uint32_t total_log_entries; 255 uint32_t dequeue_ptr; 256 uint32_t dummy[2]; 257 uint32_t fwimg_len; 258 uint8_t magic[8]; 259 uint32_t ss_low_power_entry_timeout; 260 uint8_t num_hsic_port; 261 uint8_t ss_portmap; 262 uint8_t build; 263 uint8_t padding[137]; /* Pad to 256 bytes */ 264 }; 265 266 struct xhci_soc; 267 struct tegra_xhci_softc { 268 struct xhci_softc xhci_softc; 269 device_t dev; 270 struct xhci_soc *soc; 271 struct mtx mtx; 272 struct resource *mem_res_fpci; 273 struct resource *mem_res_ipfs; 274 struct resource *irq_res_mbox; 275 void *irq_hdl_mbox; 276 277 clk_t clk_xusb_host; 278 clk_t clk_xusb_gate; 279 clk_t clk_xusb_falcon_src; 280 clk_t clk_xusb_ss; 281 clk_t clk_xusb_hs_src; 282 clk_t clk_xusb_fs_src; 283 hwreset_t hwreset_xusb_host; 284 hwreset_t hwreset_xusb_ss; 285 regulator_t regulators[16]; /* Safe maximum */ 286 phy_t phys[8]; /* Safe maximum */ 287 288 struct intr_config_hook irq_hook; 289 bool xhci_inited; 290 void *fw_vaddr; 291 vm_size_t fw_size; 292 }; 293 294 struct xhci_soc { 295 char *fw_name; 296 char **regulator_names; 297 char **phy_names; 298 }; 299 300 /* Tegra 124 config */ 301 static char *tegra124_reg_names[] = { 302 "avddio-pex-supply", 303 "dvddio-pex-supply", 304 "avdd-usb-supply", 305 "avdd-pll-utmip-supply", 306 "avdd-pll-erefe-supply", 307 "avdd-usb-ss-pll-supply", 308 "hvdd-usb-ss-supply", 309 "hvdd-usb-ss-pll-e-supply", 310 NULL 311 }; 312 313 static char *tegra124_phy_names[] = { 314 "usb2-0", 315 "usb2-1", 316 "usb2-2", 317 "usb3-0", 318 NULL 319 }; 320 321 static struct xhci_soc tegra124_soc = 322 { 323 .fw_name = "tegra124_xusb_fw", 324 .regulator_names = tegra124_reg_names, 325 .phy_names = tegra124_phy_names, 326 }; 327 328 /* Tegra 210 config */ 329 static char *tegra210_reg_names[] = { 330 "dvddio-pex-supply", 331 "hvddio-pex-supply", 332 "avdd-usb-supply", 333 "avdd-pll-utmip-supply", 334 "avdd-pll-uerefe-supply", 335 "dvdd-usb-ss-pll-supply", 336 "hvdd-usb-ss-pll-e-supply", 337 NULL 338 }; 339 340 static char *tegra210_phy_names[] = { 341 "usb2-0", 342 "usb2-1", 343 "usb2-2", 344 "usb2-3", 345 "usb3-0", 346 "usb3-1", 347 NULL 348 }; 349 350 static struct xhci_soc tegra210_soc = 351 { 352 .fw_name = "tegra210_xusb_fw", 353 .regulator_names = tegra210_reg_names, 354 .phy_names = tegra210_phy_names, 355 }; 356 357 /* Compatible devices. */ 358 static struct ofw_compat_data compat_data[] = { 359 {"nvidia,tegra124-xusb", (uintptr_t)&tegra124_soc}, 360 {"nvidia,tegra210-xusb", (uintptr_t)&tegra210_soc}, 361 {NULL, 0} 362 }; 363 364 365 static uint32_t 366 CSB_RD4(struct tegra_xhci_softc *sc, uint32_t addr) 367 { 368 369 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 370 return (FPCI_RD4(sc, ARU_C11_CSBRANGE_ADDR(addr))); 371 } 372 373 static void 374 CSB_WR4(struct tegra_xhci_softc *sc, uint32_t addr, uint32_t val) 375 { 376 377 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 378 FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val); 379 } 380 381 static int 382 get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node) 383 { 384 int i, rv; 385 386 /* Regulators. */ 387 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 388 if (i >= nitems(sc->regulators)) { 389 device_printf(sc->dev, 390 "Too many regulators present in DT.\n"); 391 return (EOVERFLOW); 392 } 393 rv = regulator_get_by_ofw_property(sc->dev, 0, 394 sc->soc->regulator_names[i], sc->regulators + i); 395 if (rv != 0) { 396 device_printf(sc->dev, 397 "Cannot get '%s' regulator\n", 398 sc->soc->regulator_names[i]); 399 return (ENXIO); 400 } 401 } 402 403 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host", 404 &sc->hwreset_xusb_host); 405 if (rv != 0) { 406 device_printf(sc->dev, "Cannot get 'xusb_host' reset\n"); 407 return (ENXIO); 408 } 409 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss", 410 &sc->hwreset_xusb_ss); 411 if (rv != 0) { 412 device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n"); 413 return (ENXIO); 414 } 415 416 /* Phys. */ 417 for (i = 0; sc->soc->phy_names[i] != NULL; i++) { 418 if (i >= nitems(sc->phys)) { 419 device_printf(sc->dev, 420 "Too many phys present in DT.\n"); 421 return (EOVERFLOW); 422 } 423 rv = phy_get_by_ofw_name(sc->dev, 0, sc->soc->phy_names[i], 424 sc->phys + i); 425 if (rv != 0 && rv != ENOENT) { 426 device_printf(sc->dev, "Cannot get '%s' phy.\n", 427 sc->soc->phy_names[i]); 428 return (ENXIO); 429 } 430 } 431 432 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host", 433 &sc->clk_xusb_host); 434 if (rv != 0) { 435 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n"); 436 return (ENXIO); 437 } 438 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src", 439 &sc->clk_xusb_falcon_src); 440 if (rv != 0) { 441 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n"); 442 return (ENXIO); 443 } 444 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss", 445 &sc->clk_xusb_ss); 446 if (rv != 0) { 447 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n"); 448 return (ENXIO); 449 } 450 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src", 451 &sc->clk_xusb_hs_src); 452 if (rv != 0) { 453 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n"); 454 return (ENXIO); 455 } 456 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src", 457 &sc->clk_xusb_fs_src); 458 if (rv != 0) { 459 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n"); 460 return (ENXIO); 461 } 462 /* Clock xusb_gate is missing in mainstream DT */ 463 rv = clk_get_by_name(sc->dev, "xusb_gate", &sc->clk_xusb_gate); 464 if (rv != 0) { 465 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n"); 466 return (ENXIO); 467 } 468 return (0); 469 } 470 471 static int 472 enable_fdt_resources(struct tegra_xhci_softc *sc) 473 { 474 int i, rv; 475 476 rv = hwreset_assert(sc->hwreset_xusb_host); 477 if (rv != 0) { 478 device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n"); 479 return (rv); 480 } 481 rv = hwreset_assert(sc->hwreset_xusb_ss); 482 if (rv != 0) { 483 device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n"); 484 return (rv); 485 } 486 487 /* Regulators. */ 488 for (i = 0; i < nitems(sc->regulators); i++) { 489 if (sc->regulators[i] == NULL) 490 continue; 491 rv = regulator_enable(sc->regulators[i]); 492 if (rv != 0) { 493 device_printf(sc->dev, 494 "Cannot enable '%s' regulator\n", 495 sc->soc->regulator_names[i]); 496 return (rv); 497 } 498 } 499 500 /* Power off XUSB host and XUSB SS domains. */ 501 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 502 if (rv != 0) { 503 device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n"); 504 return (rv); 505 } 506 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 507 if (rv != 0) { 508 device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n"); 509 return (rv); 510 } 511 512 /* Setup XUSB ss_src clock first */ 513 clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0); 514 if (rv != 0) 515 return (rv); 516 517 /* The XUSB gate clock must be enabled before XUSBA can be powered. */ 518 rv = clk_enable(sc->clk_xusb_gate); 519 if (rv != 0) { 520 device_printf(sc->dev, 521 "Cannot enable 'xusb_gate' clock\n"); 522 return (rv); 523 } 524 525 /* Power on XUSB host and XUSB SS domains. */ 526 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 527 sc->clk_xusb_host, sc->hwreset_xusb_host); 528 if (rv != 0) { 529 device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n"); 530 return (rv); 531 } 532 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 533 sc->clk_xusb_ss, sc->hwreset_xusb_ss); 534 if (rv != 0) { 535 device_printf(sc->dev, "Cannot powerup 'xusba' domain\n"); 536 return (rv); 537 } 538 539 /* Enable rest of clocks */ 540 rv = clk_enable(sc->clk_xusb_falcon_src); 541 if (rv != 0) { 542 device_printf(sc->dev, 543 "Cannot enable 'xusb_falcon_src' clock\n"); 544 return (rv); 545 } 546 rv = clk_enable(sc->clk_xusb_fs_src); 547 if (rv != 0) { 548 device_printf(sc->dev, 549 "Cannot enable 'xusb_fs_src' clock\n"); 550 return (rv); 551 } 552 rv = clk_enable(sc->clk_xusb_hs_src); 553 if (rv != 0) { 554 device_printf(sc->dev, 555 "Cannot enable 'xusb_hs_src' clock\n"); 556 return (rv); 557 } 558 559 /* Phys. */ 560 for (i = 0; i < nitems(sc->phys); i++) { 561 if (sc->phys[i] == NULL) 562 continue; 563 rv = phy_enable(sc->phys[i]); 564 if (rv != 0) { 565 device_printf(sc->dev, "Cannot enable '%s' phy\n", 566 sc->soc->phy_names[i]); 567 return (rv); 568 } 569 } 570 571 return (0); 572 } 573 574 /* Respond by ACK/NAK back to FW */ 575 static void 576 mbox_send_ack(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 577 { 578 uint32_t reg; 579 580 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 581 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 582 583 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 584 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 585 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 586 } 587 588 /* Sent command to FW */ 589 static int 590 mbox_send_cmd(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 591 { 592 uint32_t reg; 593 int i; 594 595 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 596 if (reg != ARU_MAILBOX_OWNER_NONE) { 597 device_printf(sc->dev, 598 "CPU mailbox is busy: 0x%08X\n", reg); 599 return (EBUSY); 600 } 601 /* XXX Is this right? Retry loop? Wait before send? */ 602 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW); 603 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 604 if (reg != ARU_MAILBOX_OWNER_SW) { 605 device_printf(sc->dev, 606 "Cannot acquire CPU mailbox: 0x%08X\n", reg); 607 return (EBUSY); 608 } 609 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 610 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 611 612 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 613 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 614 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 615 616 for (i = 250; i > 0; i--) { 617 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 618 if (reg == ARU_MAILBOX_OWNER_NONE) 619 break; 620 DELAY(100); 621 } 622 if (i <= 0) { 623 device_printf(sc->dev, 624 "Command response timeout: 0x%08X\n", reg); 625 return (ETIMEDOUT); 626 } 627 628 return(0); 629 } 630 631 static void 632 process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data, 633 uint32_t *resp_cmd, uint32_t *resp_data) 634 { 635 uint64_t freq; 636 int rv; 637 638 /* In most cases, data are echoed back. */ 639 *resp_data = req_data; 640 switch (req_cmd) { 641 case MBOX_CMD_INC_FALC_CLOCK: 642 case MBOX_CMD_DEC_FALC_CLOCK: 643 rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL, 644 0); 645 if (rv == 0) { 646 rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq); 647 *resp_data = (uint32_t)(freq / 1000); 648 } 649 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 650 break; 651 652 case MBOX_CMD_INC_SSPI_CLOCK: 653 case MBOX_CMD_DEC_SSPI_CLOCK: 654 rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL, 655 0); 656 if (rv == 0) { 657 rv = clk_get_freq(sc->clk_xusb_ss, &freq); 658 *resp_data = (uint32_t)(freq / 1000); 659 } 660 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 661 break; 662 663 case MBOX_CMD_SET_BW: 664 /* No respense is expected. */ 665 *resp_cmd = 0; 666 break; 667 668 case MBOX_CMD_SET_SS_PWR_GATING: 669 case MBOX_CMD_SET_SS_PWR_UNGATING: 670 *resp_cmd = MBOX_CMD_NAK; 671 break; 672 673 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 674 /* Not implemented yet. */ 675 *resp_cmd = MBOX_CMD_ACK; 676 break; 677 678 case MBOX_CMD_START_HSIC_IDLE: 679 case MBOX_CMD_STOP_HSIC_IDLE: 680 /* Not implemented yet. */ 681 *resp_cmd = MBOX_CMD_NAK; 682 break; 683 684 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 685 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 686 /* Not implemented yet. */ 687 *resp_cmd = MBOX_CMD_NAK; 688 break; 689 690 case MBOX_CMD_AIRPLANE_MODE_ENABLED: 691 case MBOX_CMD_AIRPLANE_MODE_DISABLED: 692 case MBOX_CMD_DBC_WAKE_STACK: 693 case MBOX_CMD_HSIC_PRETEND_CONNECT: 694 case MBOX_CMD_RESET_SSPI: 695 device_printf(sc->dev, 696 "Received unused/unexpected command: %u\n", req_cmd); 697 *resp_cmd = 0; 698 break; 699 700 default: 701 device_printf(sc->dev, 702 "Received unknown command: %u\n", req_cmd); 703 } 704 } 705 706 static void 707 intr_mbox(void *arg) 708 { 709 struct tegra_xhci_softc *sc; 710 uint32_t reg, msg, resp_cmd, resp_data; 711 712 sc = (struct tegra_xhci_softc *)arg; 713 714 /* Clear interrupt first */ 715 reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR); 716 FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg); 717 if (reg & ARU_SMI_INTR_FW_HANG) { 718 device_printf(sc->dev, 719 "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n", 720 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 721 } 722 723 msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT); 724 resp_cmd = 0; 725 process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg), 726 ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data); 727 if (resp_cmd != 0) 728 mbox_send_ack(sc, resp_cmd, resp_data); 729 else 730 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, 731 ARU_MAILBOX_OWNER_NONE); 732 733 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 734 reg &= ~ARU_MAILBOX_CMD_DEST_SMI; 735 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 736 737 } 738 739 static int 740 load_fw(struct tegra_xhci_softc *sc) 741 { 742 const struct firmware *fw; 743 const struct tegra_xusb_fw_hdr *fw_hdr; 744 vm_paddr_t fw_paddr, fw_base; 745 void *fw_vaddr; 746 vm_size_t fw_size; 747 uint32_t code_tags, code_size; 748 struct clocktime fw_clock; 749 struct timespec fw_timespec; 750 int i; 751 752 /* Reset ARU */ 753 FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET); 754 DELAY(3000); 755 756 /* Check if FALCON already runs */ 757 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) { 758 device_printf(sc->dev, 759 "XUSB CPU is already loaded, CPUCTL: 0x%08X\n", 760 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 761 return (0); 762 } 763 764 fw = firmware_get(sc->soc->fw_name); 765 if (fw == NULL) { 766 device_printf(sc->dev, "Cannot read xusb firmware\n"); 767 return (ENOENT); 768 } 769 770 /* Allocate uncached memory and copy firmware into. */ 771 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data; 772 fw_size = fw_hdr->fwimg_len; 773 774 fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0, 775 VM_MEMATTR_UNCACHEABLE); 776 fw_paddr = vtophys((uintptr_t)fw_vaddr); 777 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr; 778 memcpy(fw_vaddr, fw->data, fw_size); 779 780 firmware_put(fw, FIRMWARE_UNLOAD); 781 sc->fw_vaddr = fw_vaddr; 782 sc->fw_size = fw_size; 783 784 /* Setup firmware physical address and size. */ 785 fw_base = fw_paddr + sizeof(*fw_hdr); 786 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size); 787 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF); 788 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32); 789 CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH); 790 791 /* Invalidate full L2IMEM context. */ 792 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 793 L2IMEMOP_INVALIDATE_ALL); 794 795 /* Program load of L2IMEM by boot code. */ 796 code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE); 797 code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE); 798 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE, 799 L2IMEMOP_SIZE_OFFSET(code_tags) | 800 L2IMEMOP_SIZE_SIZE(code_size)); 801 802 /* Execute L2IMEM boot code fetch. */ 803 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 804 L2IMEMOP_LOAD_LOCKED_RESULT); 805 806 /* Program FALCON auto-fill range and block count */ 807 CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size); 808 CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1, 809 IMFILLRNG1_TAG_LO(code_tags) | 810 IMFILLRNG1_TAG_HI(code_tags + code_size)); 811 812 CSB_WR4(sc, XUSB_FALCON_DMACTL, 0); 813 /* Wait for CPU */ 814 for (i = 500; i > 0; i--) { 815 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) & 816 L2IMEMOP_RESULT_VLD) 817 break; 818 DELAY(100); 819 } 820 if (i <= 0) { 821 device_printf(sc->dev, "Timedout while wating for DMA, " 822 "state: 0x%08X\n", 823 CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT)); 824 return (ETIMEDOUT); 825 } 826 827 /* Boot FALCON cpu */ 828 CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag); 829 CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU); 830 831 /* Wait for CPU */ 832 for (i = 50; i > 0; i--) { 833 if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED) 834 break; 835 DELAY(100); 836 } 837 if (i <= 0) { 838 device_printf(sc->dev, "Timedout while wating for FALCON cpu, " 839 "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 840 return (ETIMEDOUT); 841 } 842 843 fw_timespec.tv_sec = fw_hdr->fwimg_created_time; 844 fw_timespec.tv_nsec = 0; 845 clock_ts_to_ct(&fw_timespec, &fw_clock); 846 device_printf(sc->dev, 847 " Falcon firmware version: %02X.%02X.%04X," 848 " (%d/%d/%d %d:%02d:%02d UTC)\n", 849 (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF, 850 fw_hdr->version_id & 0xFFFF, 851 fw_clock.day, fw_clock.mon, fw_clock.year, 852 fw_clock.hour, fw_clock.min, fw_clock.sec); 853 854 return (0); 855 } 856 857 static int 858 init_hw(struct tegra_xhci_softc *sc) 859 { 860 int rv; 861 uint32_t reg; 862 rman_res_t base_addr; 863 864 base_addr = rman_get_start(sc->xhci_softc.sc_io_res); 865 866 /* Enable FPCI access */ 867 reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 868 reg |= CONFIGURATION_EN_FPCI; 869 IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg); 870 IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 871 872 /* Program bar for XHCI base address */ 873 reg = FPCI_RD4(sc, T_XUSB_CFG_4); 874 reg &= ~CFG_4_BASE_ADDRESS(~0); 875 reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15); 876 FPCI_WR4(sc, T_XUSB_CFG_4, reg); 877 FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32)); 878 879 /* Enable bus master */ 880 reg = FPCI_RD4(sc, T_XUSB_CFG_1); 881 reg |= CFG_1_IO_SPACE; 882 reg |= CFG_1_MEMORY_SPACE; 883 reg |= CFG_1_BUS_MASTER; 884 FPCI_WR4(sc, T_XUSB_CFG_1, reg); 885 886 /* Enable Interrupts */ 887 reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK); 888 reg |= INTR_IP_INT_MASK; 889 IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg); 890 891 /* Set hysteresis */ 892 IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128); 893 894 rv = load_fw(sc); 895 if (rv != 0) 896 return rv; 897 return (0); 898 } 899 900 static int 901 tegra_xhci_probe(device_t dev) 902 { 903 904 if (!ofw_bus_status_okay(dev)) 905 return (ENXIO); 906 907 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 908 device_set_desc(dev, "Nvidia Tegra XHCI controller"); 909 return (BUS_PROBE_DEFAULT); 910 } 911 return (ENXIO); 912 } 913 914 static int 915 tegra_xhci_detach(device_t dev) 916 { 917 struct tegra_xhci_softc *sc; 918 struct xhci_softc *xsc; 919 920 sc = device_get_softc(dev); 921 xsc = &sc->xhci_softc; 922 923 /* during module unload there are lots of children leftover */ 924 device_delete_children(dev); 925 if (sc->xhci_inited) { 926 usb_callout_drain(&xsc->sc_callout); 927 xhci_halt_controller(xsc); 928 } 929 930 if (xsc->sc_irq_res && xsc->sc_intr_hdl) { 931 bus_teardown_intr(dev, xsc->sc_irq_res, xsc->sc_intr_hdl); 932 xsc->sc_intr_hdl = NULL; 933 } 934 if (xsc->sc_irq_res) { 935 bus_release_resource(dev, SYS_RES_IRQ, 936 rman_get_rid(xsc->sc_irq_res), xsc->sc_irq_res); 937 xsc->sc_irq_res = NULL; 938 } 939 if (xsc->sc_io_res != NULL) { 940 bus_release_resource(dev, SYS_RES_MEMORY, 941 rman_get_rid(xsc->sc_io_res), xsc->sc_io_res); 942 xsc->sc_io_res = NULL; 943 } 944 if (sc->xhci_inited) 945 xhci_uninit(xsc); 946 if (sc->irq_hdl_mbox != NULL) 947 bus_teardown_intr(dev, sc->irq_res_mbox, sc->irq_hdl_mbox); 948 if (sc->fw_vaddr != NULL) 949 kmem_free(sc->fw_vaddr, sc->fw_size); 950 LOCK_DESTROY(sc); 951 return (0); 952 } 953 954 static int 955 tegra_xhci_attach(device_t dev) 956 { 957 struct tegra_xhci_softc *sc; 958 struct xhci_softc *xsc; 959 int rv, rid; 960 phandle_t node; 961 962 sc = device_get_softc(dev); 963 sc->dev = dev; 964 sc->soc = (struct xhci_soc *)ofw_bus_search_compatible(dev, 965 compat_data)->ocd_data; 966 node = ofw_bus_get_node(dev); 967 xsc = &sc->xhci_softc; 968 LOCK_INIT(sc); 969 970 rv = get_fdt_resources(sc, node); 971 if (rv != 0) { 972 rv = ENXIO; 973 goto error; 974 } 975 rv = enable_fdt_resources(sc); 976 if (rv != 0) { 977 rv = ENXIO; 978 goto error; 979 } 980 981 /* Allocate resources. */ 982 rid = 0; 983 xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 984 RF_ACTIVE); 985 if (xsc->sc_io_res == NULL) { 986 device_printf(dev, 987 "Could not allocate HCD memory resources\n"); 988 rv = ENXIO; 989 goto error; 990 } 991 rid = 1; 992 sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 993 RF_ACTIVE); 994 if (sc->mem_res_fpci == NULL) { 995 device_printf(dev, 996 "Could not allocate FPCI memory resources\n"); 997 rv = ENXIO; 998 goto error; 999 } 1000 rid = 2; 1001 sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1002 RF_ACTIVE); 1003 if (sc->mem_res_ipfs == NULL) { 1004 device_printf(dev, 1005 "Could not allocate IPFS memory resources\n"); 1006 rv = ENXIO; 1007 goto error; 1008 } 1009 1010 rid = 0; 1011 xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1012 RF_ACTIVE); 1013 if (xsc->sc_irq_res == NULL) { 1014 device_printf(dev, "Could not allocate HCD IRQ resources\n"); 1015 rv = ENXIO; 1016 goto error; 1017 } 1018 rid = 1; 1019 sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1020 RF_ACTIVE); 1021 if (sc->irq_res_mbox == NULL) { 1022 device_printf(dev, "Could not allocate MBOX IRQ resources\n"); 1023 rv = ENXIO; 1024 goto error; 1025 } 1026 1027 rv = init_hw(sc); 1028 if (rv != 0) { 1029 device_printf(dev, "Could not initialize XUSB hardware\n"); 1030 goto error; 1031 } 1032 1033 /* Wakeup and enable firmaware */ 1034 rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0); 1035 if (rv != 0) { 1036 device_printf(sc->dev, "Could not enable XUSB firmware\n"); 1037 goto error; 1038 } 1039 1040 /* Fill data for XHCI driver. */ 1041 xsc->sc_bus.parent = dev; 1042 xsc->sc_bus.devices = xsc->sc_devices; 1043 xsc->sc_bus.devices_max = XHCI_MAX_DEVICES; 1044 1045 xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res); 1046 xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res); 1047 xsc->sc_io_size = rman_get_size(xsc->sc_io_res); 1048 strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor)); 1049 1050 /* Add USB bus device. */ 1051 xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1); 1052 if (xsc->sc_bus.bdev == NULL) { 1053 device_printf(sc->dev, "Could not add USB device\n"); 1054 rv = ENXIO; 1055 goto error; 1056 } 1057 device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus); 1058 device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller"); 1059 1060 rv = xhci_init(xsc, sc->dev, 1); 1061 if (rv != 0) { 1062 device_printf(sc->dev, "USB init failed: %d\n", rv); 1063 goto error; 1064 } 1065 sc->xhci_inited = true; 1066 rv = xhci_start_controller(xsc); 1067 if (rv != 0) { 1068 device_printf(sc->dev, 1069 "Could not start XHCI controller: %d\n", rv); 1070 goto error; 1071 } 1072 1073 rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE, 1074 NULL, intr_mbox, sc, &sc->irq_hdl_mbox); 1075 if (rv != 0) { 1076 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1077 xsc->sc_intr_hdl = NULL; 1078 goto error; 1079 } 1080 1081 rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1082 NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl); 1083 if (rv != 0) { 1084 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1085 xsc->sc_intr_hdl = NULL; 1086 goto error; 1087 } 1088 1089 /* Probe the bus. */ 1090 rv = device_probe_and_attach(xsc->sc_bus.bdev); 1091 if (rv != 0) { 1092 device_printf(sc->dev, "Could not initialize USB: %d\n", rv); 1093 goto error; 1094 } 1095 1096 return (0); 1097 1098 error: 1099 panic("XXXXX"); 1100 tegra_xhci_detach(dev); 1101 return (rv); 1102 } 1103 1104 static device_method_t xhci_methods[] = { 1105 /* Device interface */ 1106 DEVMETHOD(device_probe, tegra_xhci_probe), 1107 DEVMETHOD(device_attach, tegra_xhci_attach), 1108 DEVMETHOD(device_detach, tegra_xhci_detach), 1109 DEVMETHOD(device_suspend, bus_generic_suspend), 1110 DEVMETHOD(device_resume, bus_generic_resume), 1111 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1112 1113 /* Bus interface */ 1114 DEVMETHOD(bus_print_child, bus_generic_print_child), 1115 1116 DEVMETHOD_END 1117 }; 1118 1119 static DEFINE_CLASS_0(xhci, xhci_driver, xhci_methods, 1120 sizeof(struct tegra_xhci_softc)); 1121 DRIVER_MODULE(tegra_xhci, simplebus, xhci_driver, NULL, NULL); 1122 MODULE_DEPEND(tegra_xhci, usb, 1, 1, 1); 1123