1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * XHCI driver for Tegra SoCs. 32 */ 33 #include "opt_bus.h" 34 #include "opt_platform.h" 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/clock.h> 39 #include <sys/condvar.h> 40 #include <sys/firmware.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/systm.h> 48 49 #include <vm/vm.h> 50 #include <vm/vm_extern.h> 51 #include <vm/vm_kern.h> 52 #include <vm/pmap.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/phy/phy.h> 60 #include <dev/extres/regulator/regulator.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_controller.h> 68 #include <dev/usb/usb_bus.h> 69 #include <dev/usb/controller/xhci.h> 70 #include <dev/usb/controller/xhcireg.h> 71 72 #include <arm/nvidia/tegra_pmc.h> 73 74 #include "usbdevs.h" 75 76 /* FPCI address space */ 77 #define T_XUSB_CFG_0 0x000 78 #define T_XUSB_CFG_1 0x004 79 #define CFG_1_BUS_MASTER (1 << 2) 80 #define CFG_1_MEMORY_SPACE (1 << 1) 81 #define CFG_1_IO_SPACE (1 << 0) 82 83 #define T_XUSB_CFG_2 0x008 84 #define T_XUSB_CFG_3 0x00C 85 #define T_XUSB_CFG_4 0x010 86 #define CFG_4_BASE_ADDRESS(x) (((x) & 0x1FFFF) << 15) 87 88 #define T_XUSB_CFG_5 0x014 89 #define T_XUSB_CFG_ARU_MAILBOX_CMD 0x0E4 90 #define ARU_MAILBOX_CMD_INT_EN (1U << 31) 91 #define ARU_MAILBOX_CMD_DEST_XHCI (1 << 30) 92 #define ARU_MAILBOX_CMD_DEST_SMI (1 << 29) 93 #define ARU_MAILBOX_CMD_DEST_PME (1 << 28) 94 #define ARU_MAILBOX_CMD_DEST_FALC (1 << 27) 95 96 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN 0x0E8 97 #define ARU_MAILBOX_DATA_IN_DATA(x) (((x) & 0xFFFFFF) << 0) 98 #define ARU_MAILBOX_DATA_IN_TYPE(x) (((x) & 0x0000FF) << 24) 99 100 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT 0x0EC 101 #define ARU_MAILBOX_DATA_OUT_DATA(x) (((x) >> 0) & 0xFFFFFF) 102 #define ARU_MAILBOX_DATA_OUT_TYPE(x) (((x) >> 24) & 0x0000FF) 103 104 #define T_XUSB_CFG_ARU_MAILBOX_OWNER 0x0F0 105 #define ARU_MAILBOX_OWNER_SW 2 106 #define ARU_MAILBOX_OWNER_FW 1 107 #define ARU_MAILBOX_OWNER_NONE 0 108 109 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41C /* ! UNDOCUMENTED ! */ 110 #define ARU_C11_CSBRANGE_PAGE(x) ((x) >> 9) 111 #define ARU_C11_CSBRANGE_ADDR(x) (0x800 + ((x) & 0x1FF)) 112 #define XUSB_CFG_ARU_SMI_INTR 0x428 /* ! UNDOCUMENTED ! */ 113 #define ARU_SMI_INTR_EN (1 << 3) 114 #define ARU_SMI_INTR_FW_HANG (1 << 1) 115 #define XUSB_CFG_ARU_RST 0x42C /* ! UNDOCUMENTED ! */ 116 #define ARU_RST_RESET (1 << 0) 117 118 #define XUSB_HOST_CONFIGURATION 0x180 119 #define CONFIGURATION_CLKEN_OVERRIDE (1U<< 31) 120 #define CONFIGURATION_PW_NO_DEVSEL_ERR_CYA (1 << 19) 121 #define CONFIGURATION_INITIATOR_READ_IDLE (1 << 18) 122 #define CONFIGURATION_INITIATOR_WRITE_IDLE (1 << 17) 123 #define CONFIGURATION_WDATA_LEAD_CYA (1 << 15) 124 #define CONFIGURATION_WR_INTRLV_CYA (1 << 14) 125 #define CONFIGURATION_TARGET_READ_IDLE (1 << 11) 126 #define CONFIGURATION_TARGET_WRITE_IDLE (1 << 10) 127 #define CONFIGURATION_MSI_VEC_EMPTY (1 << 9) 128 #define CONFIGURATION_UFPCI_MSIAW (1 << 7) 129 #define CONFIGURATION_UFPCI_PWPASSPW (1 << 6) 130 #define CONFIGURATION_UFPCI_PASSPW (1 << 5) 131 #define CONFIGURATION_UFPCI_PWPASSNPW (1 << 4) 132 #define CONFIGURATION_DFPCI_PWPASSNPW (1 << 3) 133 #define CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) 134 #define CONFIGURATION_DFPCI_PASSPW (1 << 1) 135 #define CONFIGURATION_EN_FPCI (1 << 0) 136 137 /* IPFS address space */ 138 #define XUSB_HOST_FPCI_ERROR_MASKS 0x184 139 #define FPCI_ERROR_MASTER_ABORT (1 << 2) 140 #define FPCI_ERRORI_DATA_ERROR (1 << 1) 141 #define FPCI_ERROR_TARGET_ABORT (1 << 0) 142 143 #define XUSB_HOST_INTR_MASK 0x188 144 #define INTR_IP_INT_MASK (1 << 16) 145 #define INTR_MSI_MASK (1 << 8) 146 #define INTR_INT_MASK (1 << 0) 147 148 #define XUSB_HOST_CLKGATE_HYSTERESIS 0x1BC 149 150 /* CSB Falcon CPU */ 151 #define XUSB_FALCON_CPUCTL 0x100 152 #define CPUCTL_STOPPED (1 << 5) 153 #define CPUCTL_HALTED (1 << 4) 154 #define CPUCTL_HRESET (1 << 3) 155 #define CPUCTL_SRESET (1 << 2) 156 #define CPUCTL_STARTCPU (1 << 1) 157 #define CPUCTL_IINVAL (1 << 0) 158 159 #define XUSB_FALCON_BOOTVEC 0x104 160 #define XUSB_FALCON_DMACTL 0x10C 161 #define XUSB_FALCON_IMFILLRNG1 0x154 162 #define IMFILLRNG1_TAG_HI(x) (((x) & 0xFFF) << 16) 163 #define IMFILLRNG1_TAG_LO(x) (((x) & 0xFFF) << 0) 164 #define XUSB_FALCON_IMFILLCTL 0x158 165 166 /* CSB mempool */ 167 #define XUSB_CSB_MEMPOOL_APMAP 0x10181C 168 #define APMAP_BOOTPATH (1U << 31) 169 170 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR 0x101A00 171 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO 0x101A04 172 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI 0x101A08 173 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE 0x101A10 174 #define L2IMEMOP_SIZE_OFFSET(x) (((x) & 0x3FF) << 8) 175 #define L2IMEMOP_SIZE_SIZE(x) (((x) & 0x0FF) << 24) 176 177 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG 0x101A14 178 #define L2IMEMOP_INVALIDATE_ALL (0x40 << 24) 179 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << 24) 180 181 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101A18 182 #define L2IMEMOP_RESULT_VLD (1U << 31) 183 184 #define XUSB_CSB_IMEM_BLOCK_SIZE 256 185 186 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 187 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 188 189 /* MBOX commands. */ 190 #define MBOX_CMD_MSG_ENABLED 1 191 #define MBOX_CMD_INC_FALC_CLOCK 2 192 #define MBOX_CMD_DEC_FALC_CLOCK 3 193 #define MBOX_CMD_INC_SSPI_CLOCK 4 194 #define MBOX_CMD_DEC_SSPI_CLOCK 5 195 #define MBOX_CMD_SET_BW 6 196 #define MBOX_CMD_SET_SS_PWR_GATING 7 197 #define MBOX_CMD_SET_SS_PWR_UNGATING 8 198 #define MBOX_CMD_SAVE_DFE_CTLE_CTX 9 199 #define MBOX_CMD_AIRPLANE_MODE_ENABLED 10 200 #define MBOX_CMD_AIRPLANE_MODE_DISABLED 11 201 #define MBOX_CMD_START_HSIC_IDLE 12 202 #define MBOX_CMD_STOP_HSIC_IDLE 13 203 #define MBOX_CMD_DBC_WAKE_STACK 14 204 #define MBOX_CMD_HSIC_PRETEND_CONNECT 15 205 #define MBOX_CMD_RESET_SSPI 16 206 #define MBOX_CMD_DISABLE_SS_LFPS_DETECTION 17 207 #define MBOX_CMD_ENABLE_SS_LFPS_DETECTION 18 208 209 /* MBOX responses. */ 210 #define MBOX_CMD_ACK (0x80 + 0) 211 #define MBOX_CMD_NAK (0x80 + 1) 212 213 #define IPFS_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_ipfs, (_r), (_v)) 214 #define IPFS_RD4(_sc, _r) bus_read_4((_sc)->mem_res_ipfs, (_r)) 215 #define FPCI_WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res_fpci, (_r), (_v)) 216 #define FPCI_RD4(_sc, _r) bus_read_4((_sc)->mem_res_fpci, (_r)) 217 218 #define LOCK(_sc) mtx_lock(&(_sc)->mtx) 219 #define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 220 #define SLEEP(_sc, timeout) \ 221 mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout); 222 #define LOCK_INIT(_sc) \ 223 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_xhci", MTX_DEF) 224 #define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 225 #define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 226 #define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 227 228 struct tegra_xusb_fw_hdr { 229 uint32_t boot_loadaddr_in_imem; 230 uint32_t boot_codedfi_offset; 231 uint32_t boot_codetag; 232 uint32_t boot_codesize; 233 234 uint32_t phys_memaddr; 235 uint16_t reqphys_memsize; 236 uint16_t alloc_phys_memsize; 237 238 uint32_t rodata_img_offset; 239 uint32_t rodata_section_start; 240 uint32_t rodata_section_end; 241 uint32_t main_fnaddr; 242 243 uint32_t fwimg_cksum; 244 uint32_t fwimg_created_time; 245 246 uint32_t imem_resident_start; 247 uint32_t imem_resident_end; 248 uint32_t idirect_start; 249 uint32_t idirect_end; 250 uint32_t l2_imem_start; 251 uint32_t l2_imem_end; 252 uint32_t version_id; 253 uint8_t init_ddirect; 254 uint8_t reserved[3]; 255 uint32_t phys_addr_log_buffer; 256 uint32_t total_log_entries; 257 uint32_t dequeue_ptr; 258 uint32_t dummy[2]; 259 uint32_t fwimg_len; 260 uint8_t magic[8]; 261 uint32_t ss_low_power_entry_timeout; 262 uint8_t num_hsic_port; 263 uint8_t ss_portmap; 264 uint8_t build; 265 uint8_t padding[137]; /* Pad to 256 bytes */ 266 }; 267 268 /* Compatible devices. */ 269 static struct ofw_compat_data compat_data[] = { 270 {"nvidia,tegra124-xusb", 1}, 271 {NULL, 0} 272 }; 273 274 struct tegra_xhci_softc { 275 struct xhci_softc xhci_softc; 276 device_t dev; 277 struct mtx mtx; 278 struct resource *mem_res_fpci; 279 struct resource *mem_res_ipfs; 280 struct resource *irq_res_mbox; 281 void *irq_hdl_mbox; 282 283 clk_t clk_xusb_host; 284 clk_t clk_xusb_gate; 285 clk_t clk_xusb_falcon_src; 286 clk_t clk_xusb_ss; 287 clk_t clk_xusb_hs_src; 288 clk_t clk_xusb_fs_src; 289 hwreset_t hwreset_xusb_host; 290 hwreset_t hwreset_xusb_ss; 291 regulator_t supply_avddio_pex; 292 regulator_t supply_dvddio_pex; 293 regulator_t supply_avdd_usb; 294 regulator_t supply_avdd_pll_utmip; 295 regulator_t supply_avdd_pll_erefe; 296 regulator_t supply_avdd_usb_ss_pll; 297 regulator_t supply_hvdd_usb_ss; 298 regulator_t supply_hvdd_usb_ss_pll_e; 299 phy_t phy_usb2_0; 300 phy_t phy_usb2_1; 301 phy_t phy_usb2_2; 302 phy_t phy_usb3_0; 303 304 struct intr_config_hook irq_hook; 305 bool xhci_inited; 306 char *fw_name; 307 vm_offset_t fw_vaddr; 308 vm_size_t fw_size; 309 }; 310 311 static uint32_t 312 CSB_RD4(struct tegra_xhci_softc *sc, uint32_t addr) 313 { 314 315 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 316 return (FPCI_RD4(sc, ARU_C11_CSBRANGE_ADDR(addr))); 317 } 318 319 static void 320 CSB_WR4(struct tegra_xhci_softc *sc, uint32_t addr, uint32_t val) 321 { 322 323 FPCI_WR4(sc, XUSB_CFG_ARU_C11_CSBRANGE, ARU_C11_CSBRANGE_PAGE(addr)); 324 FPCI_WR4(sc, ARU_C11_CSBRANGE_ADDR(addr), val); 325 } 326 327 static int 328 get_fdt_resources(struct tegra_xhci_softc *sc, phandle_t node) 329 { 330 int rv; 331 332 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 333 &sc->supply_avddio_pex); 334 if (rv != 0) { 335 device_printf(sc->dev, 336 "Cannot get 'avddio-pex' regulator\n"); 337 return (ENXIO); 338 } 339 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 340 &sc->supply_dvddio_pex); 341 if (rv != 0) { 342 device_printf(sc->dev, 343 "Cannot get 'dvddio-pex' regulator\n"); 344 return (ENXIO); 345 } 346 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-supply", 347 &sc->supply_avdd_usb); 348 if (rv != 0) { 349 device_printf(sc->dev, 350 "Cannot get 'avdd-usb' regulator\n"); 351 return (ENXIO); 352 } 353 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-utmip-supply", 354 &sc->supply_avdd_pll_utmip); 355 if (rv != 0) { 356 device_printf(sc->dev, 357 "Cannot get 'avdd-pll-utmip' regulator\n"); 358 return (ENXIO); 359 } 360 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 361 &sc->supply_avdd_pll_erefe); 362 if (rv != 0) { 363 device_printf(sc->dev, 364 "Cannot get 'avdd-pll-erefe' regulator\n"); 365 return (ENXIO); 366 } 367 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-usb-ss-pll-supply", 368 &sc->supply_avdd_usb_ss_pll); 369 if (rv != 0) { 370 device_printf(sc->dev, 371 "Cannot get 'avdd-usb-ss-pll' regulator\n"); 372 return (ENXIO); 373 } 374 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-usb-ss-supply", 375 &sc->supply_hvdd_usb_ss); 376 if (rv != 0) { 377 device_printf(sc->dev, 378 "Cannot get 'hvdd-usb-ss' regulator\n"); 379 return (ENXIO); 380 } 381 rv = regulator_get_by_ofw_property(sc->dev, 0, 382 "hvdd-usb-ss-pll-e-supply", &sc->supply_hvdd_usb_ss_pll_e); 383 if (rv != 0) { 384 device_printf(sc->dev, 385 "Cannot get 'hvdd-usb-ss-pll-e' regulator\n"); 386 return (ENXIO); 387 } 388 389 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host", 390 &sc->hwreset_xusb_host); 391 if (rv != 0) { 392 device_printf(sc->dev, "Cannot get 'xusb_host' reset\n"); 393 return (ENXIO); 394 } 395 rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss", 396 &sc->hwreset_xusb_ss); 397 if (rv != 0) { 398 device_printf(sc->dev, "Cannot get 'xusb_ss' reset\n"); 399 return (ENXIO); 400 } 401 402 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-0", &sc->phy_usb2_0); 403 if (rv != 0) { 404 device_printf(sc->dev, "Cannot get 'usb2-0' phy\n"); 405 return (ENXIO); 406 } 407 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-1", &sc->phy_usb2_1); 408 if (rv != 0) { 409 device_printf(sc->dev, "Cannot get 'usb2-1' phy\n"); 410 return (ENXIO); 411 } 412 rv = phy_get_by_ofw_name(sc->dev, 0, "usb2-2", &sc->phy_usb2_2); 413 if (rv != 0) { 414 device_printf(sc->dev, "Cannot get 'usb2-2' phy\n"); 415 return (ENXIO); 416 } 417 rv = phy_get_by_ofw_name(sc->dev, 0, "usb3-0", &sc->phy_usb3_0); 418 if (rv != 0) { 419 device_printf(sc->dev, "Cannot get 'usb3-0' phy\n"); 420 return (ENXIO); 421 } 422 423 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host", 424 &sc->clk_xusb_host); 425 if (rv != 0) { 426 device_printf(sc->dev, "Cannot get 'xusb_host' clock\n"); 427 return (ENXIO); 428 } 429 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src", 430 &sc->clk_xusb_falcon_src); 431 if (rv != 0) { 432 device_printf(sc->dev, "Cannot get 'xusb_falcon_src' clock\n"); 433 return (ENXIO); 434 } 435 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss", 436 &sc->clk_xusb_ss); 437 if (rv != 0) { 438 device_printf(sc->dev, "Cannot get 'xusb_ss' clock\n"); 439 return (ENXIO); 440 } 441 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src", 442 &sc->clk_xusb_hs_src); 443 if (rv != 0) { 444 device_printf(sc->dev, "Cannot get 'xusb_hs_src' clock\n"); 445 return (ENXIO); 446 } 447 rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src", 448 &sc->clk_xusb_fs_src); 449 if (rv != 0) { 450 device_printf(sc->dev, "Cannot get 'xusb_fs_src' clock\n"); 451 return (ENXIO); 452 } 453 rv = clk_get_by_ofw_index_prop(sc->dev, 0, "freebsd,clock-xusb-gate", 0, 454 &sc->clk_xusb_gate); 455 if (rv != 0) { 456 device_printf(sc->dev, "Cannot get 'xusb_gate' clock\n"); 457 return (ENXIO); 458 } 459 return (0); 460 } 461 462 static int 463 enable_fdt_resources(struct tegra_xhci_softc *sc) 464 { 465 int rv; 466 467 rv = hwreset_assert(sc->hwreset_xusb_host); 468 if (rv != 0) { 469 device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n"); 470 return (rv); 471 } 472 rv = hwreset_assert(sc->hwreset_xusb_ss); 473 if (rv != 0) { 474 device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n"); 475 return (rv); 476 } 477 478 rv = regulator_enable(sc->supply_avddio_pex); 479 if (rv != 0) { 480 device_printf(sc->dev, 481 "Cannot enable 'avddio_pex' regulator\n"); 482 return (rv); 483 } 484 rv = regulator_enable(sc->supply_dvddio_pex); 485 if (rv != 0) { 486 device_printf(sc->dev, 487 "Cannot enable 'dvddio_pex' regulator\n"); 488 return (rv); 489 } 490 rv = regulator_enable(sc->supply_avdd_usb); 491 if (rv != 0) { 492 device_printf(sc->dev, 493 "Cannot enable 'avdd_usb' regulator\n"); 494 return (rv); 495 } 496 rv = regulator_enable(sc->supply_avdd_pll_utmip); 497 if (rv != 0) { 498 device_printf(sc->dev, 499 "Cannot enable 'avdd_pll_utmip-5v' regulator\n"); 500 return (rv); 501 } 502 rv = regulator_enable(sc->supply_avdd_pll_erefe); 503 if (rv != 0) { 504 device_printf(sc->dev, 505 "Cannot enable 'avdd_pll_erefe' regulator\n"); 506 return (rv); 507 } 508 rv = regulator_enable(sc->supply_avdd_usb_ss_pll); 509 if (rv != 0) { 510 device_printf(sc->dev, 511 "Cannot enable 'avdd_usb_ss_pll' regulator\n"); 512 return (rv); 513 } 514 rv = regulator_enable(sc->supply_hvdd_usb_ss); 515 if (rv != 0) { 516 device_printf(sc->dev, 517 "Cannot enable 'hvdd_usb_ss' regulator\n"); 518 return (rv); 519 } 520 rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e); 521 if (rv != 0) { 522 device_printf(sc->dev, 523 "Cannot enable 'hvdd_usb_ss_pll_e' regulator\n"); 524 return (rv); 525 } 526 527 /* Power off XUSB host and XUSB SS domains. */ 528 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 529 if (rv != 0) { 530 device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n"); 531 return (rv); 532 } 533 rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 534 if (rv != 0) { 535 device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n"); 536 return (rv); 537 } 538 539 /* Setup XUSB ss_src clock first */ 540 clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0); 541 if (rv != 0) 542 return (rv); 543 544 /* The XUSB gate clock must be enabled before XUSBA can be powered. */ 545 rv = clk_enable(sc->clk_xusb_gate); 546 if (rv != 0) { 547 device_printf(sc->dev, 548 "Cannot enable 'xusb_gate' clock\n"); 549 return (rv); 550 } 551 552 /* Power on XUSB host and XUSB SS domains. */ 553 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 554 sc->clk_xusb_host, sc->hwreset_xusb_host); 555 if (rv != 0) { 556 device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n"); 557 return (rv); 558 } 559 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 560 sc->clk_xusb_ss, sc->hwreset_xusb_ss); 561 if (rv != 0) { 562 device_printf(sc->dev, "Cannot powerup 'xusba' domain\n"); 563 return (rv); 564 } 565 566 /* Enable rest of clocks */ 567 rv = clk_enable(sc->clk_xusb_falcon_src); 568 if (rv != 0) { 569 device_printf(sc->dev, 570 "Cannot enable 'xusb_falcon_src' clock\n"); 571 return (rv); 572 } 573 rv = clk_enable(sc->clk_xusb_fs_src); 574 if (rv != 0) { 575 device_printf(sc->dev, 576 "Cannot enable 'xusb_fs_src' clock\n"); 577 return (rv); 578 } 579 rv = clk_enable(sc->clk_xusb_hs_src); 580 if (rv != 0) { 581 device_printf(sc->dev, 582 "Cannot enable 'xusb_hs_src' clock\n"); 583 return (rv); 584 } 585 586 rv = phy_enable(sc->phy_usb2_0); 587 if (rv != 0) { 588 device_printf(sc->dev, "Cannot enable USB2_0 phy\n"); 589 return (rv); 590 } 591 rv = phy_enable(sc->phy_usb2_1); 592 if (rv != 0) { 593 device_printf(sc->dev, "Cannot enable USB2_1 phy\n"); 594 return (rv); 595 } 596 rv = phy_enable(sc->phy_usb2_2); 597 if (rv != 0) { 598 device_printf(sc->dev, "Cannot enable USB2_2 phy\n"); 599 return (rv); 600 } 601 rv = phy_enable(sc->phy_usb3_0); 602 if (rv != 0) { 603 device_printf(sc->dev, "Cannot enable USB3_0 phy\n"); 604 return (rv); 605 } 606 607 return (0); 608 } 609 610 /* Respond by ACK/NAK back to FW */ 611 static void 612 mbox_send_ack(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 613 { 614 uint32_t reg; 615 616 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 617 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 618 619 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 620 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 621 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 622 } 623 624 /* Sent command to FW */ 625 static int 626 mbox_send_cmd(struct tegra_xhci_softc *sc, uint32_t cmd, uint32_t data) 627 { 628 uint32_t reg; 629 int i; 630 631 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 632 if (reg != ARU_MAILBOX_OWNER_NONE) { 633 device_printf(sc->dev, 634 "CPU mailbox is busy: 0x%08X\n", reg); 635 return (EBUSY); 636 } 637 /* XXX Is this right? Retry loop? Wait before send? */ 638 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, ARU_MAILBOX_OWNER_SW); 639 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 640 if (reg != ARU_MAILBOX_OWNER_SW) { 641 device_printf(sc->dev, 642 "Cannot acquire CPU mailbox: 0x%08X\n", reg); 643 return (EBUSY); 644 } 645 reg = ARU_MAILBOX_DATA_IN_TYPE(cmd) | ARU_MAILBOX_DATA_IN_DATA(data); 646 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_IN, reg); 647 648 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 649 reg |= ARU_MAILBOX_CMD_DEST_FALC | ARU_MAILBOX_CMD_INT_EN; 650 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 651 652 for (i = 250; i > 0; i--) { 653 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER); 654 if (reg == ARU_MAILBOX_OWNER_NONE) 655 break; 656 DELAY(100); 657 } 658 if (i <= 0) { 659 device_printf(sc->dev, 660 "Command response timeout: 0x%08X\n", reg); 661 return (ETIMEDOUT); 662 } 663 664 return(0); 665 } 666 667 static void 668 process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data, 669 uint32_t *resp_cmd, uint32_t *resp_data) 670 { 671 uint64_t freq; 672 int rv; 673 674 /* In most cases, data are echoed back. */ 675 *resp_data = req_data; 676 switch (req_cmd) { 677 case MBOX_CMD_INC_FALC_CLOCK: 678 case MBOX_CMD_DEC_FALC_CLOCK: 679 rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL, 680 0); 681 if (rv == 0) { 682 rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq); 683 *resp_data = (uint32_t)(freq / 1000); 684 } 685 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 686 break; 687 688 case MBOX_CMD_INC_SSPI_CLOCK: 689 case MBOX_CMD_DEC_SSPI_CLOCK: 690 rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL, 691 0); 692 if (rv == 0) { 693 rv = clk_get_freq(sc->clk_xusb_ss, &freq); 694 *resp_data = (uint32_t)(freq / 1000); 695 } 696 *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; 697 break; 698 699 case MBOX_CMD_SET_BW: 700 /* No respense is expected. */ 701 *resp_cmd = 0; 702 break; 703 704 case MBOX_CMD_SET_SS_PWR_GATING: 705 case MBOX_CMD_SET_SS_PWR_UNGATING: 706 *resp_cmd = MBOX_CMD_NAK; 707 break; 708 709 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 710 /* Not implemented yet. */ 711 *resp_cmd = MBOX_CMD_ACK; 712 break; 713 714 case MBOX_CMD_START_HSIC_IDLE: 715 case MBOX_CMD_STOP_HSIC_IDLE: 716 /* Not implemented yet. */ 717 *resp_cmd = MBOX_CMD_NAK; 718 break; 719 720 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 721 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 722 /* Not implemented yet. */ 723 *resp_cmd = MBOX_CMD_NAK; 724 break; 725 726 case MBOX_CMD_AIRPLANE_MODE_ENABLED: 727 case MBOX_CMD_AIRPLANE_MODE_DISABLED: 728 case MBOX_CMD_DBC_WAKE_STACK: 729 case MBOX_CMD_HSIC_PRETEND_CONNECT: 730 case MBOX_CMD_RESET_SSPI: 731 device_printf(sc->dev, 732 "Received unused/unexpected command: %u\n", req_cmd); 733 *resp_cmd = 0; 734 break; 735 736 default: 737 device_printf(sc->dev, 738 "Received unknown command: %u\n", req_cmd); 739 } 740 } 741 742 static void 743 intr_mbox(void *arg) 744 { 745 struct tegra_xhci_softc *sc; 746 uint32_t reg, msg, resp_cmd, resp_data; 747 748 sc = (struct tegra_xhci_softc *)arg; 749 750 /* Clear interrupt first */ 751 reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR); 752 FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg); 753 if (reg & ARU_SMI_INTR_FW_HANG) { 754 device_printf(sc->dev, 755 "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n", 756 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 757 } 758 759 msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT); 760 resp_cmd = 0; 761 process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg), 762 ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data); 763 if (resp_cmd != 0) 764 mbox_send_ack(sc, resp_cmd, resp_data); 765 else 766 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, 767 ARU_MAILBOX_OWNER_NONE); 768 769 reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); 770 reg &= ~ARU_MAILBOX_CMD_DEST_SMI; 771 FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); 772 773 } 774 775 static int 776 load_fw(struct tegra_xhci_softc *sc) 777 { 778 const struct firmware *fw; 779 const struct tegra_xusb_fw_hdr *fw_hdr; 780 vm_paddr_t fw_paddr, fw_base; 781 vm_offset_t fw_vaddr; 782 vm_size_t fw_size; 783 uint32_t code_tags, code_size; 784 struct clocktime fw_clock; 785 struct timespec fw_timespec; 786 int i; 787 788 /* Reset ARU */ 789 FPCI_WR4(sc, XUSB_CFG_ARU_RST, ARU_RST_RESET); 790 DELAY(3000); 791 792 /* Check if FALCON already runs */ 793 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) { 794 device_printf(sc->dev, 795 "XUSB CPU is already loaded, CPUCTL: 0x%08X\n", 796 CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 797 return (0); 798 } 799 800 fw = firmware_get(sc->fw_name); 801 if (fw == NULL) { 802 device_printf(sc->dev, "Cannot read xusb firmware\n"); 803 return (ENOENT); 804 } 805 806 /* Allocate uncached memory and copy firmware into. */ 807 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw->data; 808 fw_size = fw_hdr->fwimg_len; 809 810 fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0, 811 VM_MEMATTR_UNCACHEABLE); 812 fw_paddr = vtophys(fw_vaddr); 813 fw_hdr = (const struct tegra_xusb_fw_hdr *)fw_vaddr; 814 memcpy((void *)fw_vaddr, fw->data, fw_size); 815 816 firmware_put(fw, FIRMWARE_UNLOAD); 817 sc->fw_vaddr = fw_vaddr; 818 sc->fw_size = fw_size; 819 820 /* Setup firmware physical address and size. */ 821 fw_base = fw_paddr + sizeof(*fw_hdr); 822 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_ATTR, fw_size); 823 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF); 824 CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI, (uint64_t)fw_base >> 32); 825 CSB_WR4(sc, XUSB_CSB_MEMPOOL_APMAP, APMAP_BOOTPATH); 826 827 /* Invalidate full L2IMEM context. */ 828 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 829 L2IMEMOP_INVALIDATE_ALL); 830 831 /* Program load of L2IMEM by boot code. */ 832 code_tags = howmany(fw_hdr->boot_codetag, XUSB_CSB_IMEM_BLOCK_SIZE); 833 code_size = howmany(fw_hdr->boot_codesize, XUSB_CSB_IMEM_BLOCK_SIZE); 834 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE, 835 L2IMEMOP_SIZE_OFFSET(code_tags) | 836 L2IMEMOP_SIZE_SIZE(code_size)); 837 838 /* Execute L2IMEM boot code fetch. */ 839 CSB_WR4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG, 840 L2IMEMOP_LOAD_LOCKED_RESULT); 841 842 /* Program FALCON auto-fill range and block count */ 843 CSB_WR4(sc, XUSB_FALCON_IMFILLCTL, code_size); 844 CSB_WR4(sc, XUSB_FALCON_IMFILLRNG1, 845 IMFILLRNG1_TAG_LO(code_tags) | 846 IMFILLRNG1_TAG_HI(code_tags + code_size)); 847 848 CSB_WR4(sc, XUSB_FALCON_DMACTL, 0); 849 /* Wait for CPU */ 850 for (i = 500; i > 0; i--) { 851 if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT) & 852 L2IMEMOP_RESULT_VLD) 853 break; 854 DELAY(100); 855 } 856 if (i <= 0) { 857 device_printf(sc->dev, "Timedout while wating for DMA, " 858 "state: 0x%08X\n", 859 CSB_RD4(sc, XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT)); 860 return (ETIMEDOUT); 861 } 862 863 /* Boot FALCON cpu */ 864 CSB_WR4(sc, XUSB_FALCON_BOOTVEC, fw_hdr->boot_codetag); 865 CSB_WR4(sc, XUSB_FALCON_CPUCTL, CPUCTL_STARTCPU); 866 867 /* Wait for CPU */ 868 for (i = 50; i > 0; i--) { 869 if (CSB_RD4(sc, XUSB_FALCON_CPUCTL) == CPUCTL_STOPPED) 870 break; 871 DELAY(100); 872 } 873 if (i <= 0) { 874 device_printf(sc->dev, "Timedout while wating for FALCON cpu, " 875 "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL)); 876 return (ETIMEDOUT); 877 } 878 879 fw_timespec.tv_sec = fw_hdr->fwimg_created_time; 880 fw_timespec.tv_nsec = 0; 881 clock_ts_to_ct(&fw_timespec, &fw_clock); 882 device_printf(sc->dev, 883 " Falcon firmware version: %02X.%02X.%04X," 884 " (%d/%d/%d %d:%02d:%02d UTC)\n", 885 (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF, 886 fw_hdr->version_id & 0xFFFF, 887 fw_clock.day, fw_clock.mon, fw_clock.year, 888 fw_clock.hour, fw_clock.min, fw_clock.sec); 889 890 return (0); 891 } 892 893 static int 894 init_hw(struct tegra_xhci_softc *sc) 895 { 896 int rv; 897 uint32_t reg; 898 rman_res_t base_addr; 899 900 base_addr = rman_get_start(sc->xhci_softc.sc_io_res); 901 902 /* Enable FPCI access */ 903 reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 904 reg |= CONFIGURATION_EN_FPCI; 905 IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg); 906 IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); 907 908 /* Program bar for XHCI base address */ 909 reg = FPCI_RD4(sc, T_XUSB_CFG_4); 910 reg &= ~CFG_4_BASE_ADDRESS(~0); 911 reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15); 912 FPCI_WR4(sc, T_XUSB_CFG_4, reg); 913 FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32)); 914 915 /* Enable bus master */ 916 reg = FPCI_RD4(sc, T_XUSB_CFG_1); 917 reg |= CFG_1_IO_SPACE; 918 reg |= CFG_1_MEMORY_SPACE; 919 reg |= CFG_1_BUS_MASTER; 920 FPCI_WR4(sc, T_XUSB_CFG_1, reg); 921 922 /* Enable Interrupts */ 923 reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK); 924 reg |= INTR_IP_INT_MASK; 925 IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg); 926 927 /* Set hysteresis */ 928 IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128); 929 930 rv = load_fw(sc); 931 if (rv != 0) 932 return rv; 933 return (0); 934 } 935 936 static int 937 tegra_xhci_probe(device_t dev) 938 { 939 940 if (!ofw_bus_status_okay(dev)) 941 return (ENXIO); 942 943 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 944 device_set_desc(dev, "Nvidia Tegra XHCI controller"); 945 return (BUS_PROBE_DEFAULT); 946 } 947 return (ENXIO); 948 } 949 950 static int 951 tegra_xhci_detach(device_t dev) 952 { 953 struct tegra_xhci_softc *sc; 954 struct xhci_softc *xsc; 955 956 sc = device_get_softc(dev); 957 xsc = &sc->xhci_softc; 958 959 /* during module unload there are lots of children leftover */ 960 device_delete_children(dev); 961 if (sc->xhci_inited) { 962 usb_callout_drain(&xsc->sc_callout); 963 xhci_halt_controller(xsc); 964 } 965 966 if (xsc->sc_irq_res && xsc->sc_intr_hdl) { 967 bus_teardown_intr(dev, xsc->sc_irq_res, xsc->sc_intr_hdl); 968 xsc->sc_intr_hdl = NULL; 969 } 970 if (xsc->sc_irq_res) { 971 bus_release_resource(dev, SYS_RES_IRQ, 972 rman_get_rid(xsc->sc_irq_res), xsc->sc_irq_res); 973 xsc->sc_irq_res = NULL; 974 } 975 if (xsc->sc_io_res != NULL) { 976 bus_release_resource(dev, SYS_RES_MEMORY, 977 rman_get_rid(xsc->sc_io_res), xsc->sc_io_res); 978 xsc->sc_io_res = NULL; 979 } 980 if (sc->xhci_inited) 981 xhci_uninit(xsc); 982 if (sc->irq_hdl_mbox != NULL) 983 bus_teardown_intr(dev, sc->irq_res_mbox, sc->irq_hdl_mbox); 984 if (sc->fw_vaddr != 0) 985 kmem_free(sc->fw_vaddr, sc->fw_size); 986 LOCK_DESTROY(sc); 987 return (0); 988 } 989 990 static int 991 tegra_xhci_attach(device_t dev) 992 { 993 struct tegra_xhci_softc *sc; 994 struct xhci_softc *xsc; 995 int rv, rid; 996 phandle_t node; 997 998 sc = device_get_softc(dev); 999 sc->dev = dev; 1000 sc->fw_name = "tegra124_xusb_fw"; 1001 node = ofw_bus_get_node(dev); 1002 xsc = &sc->xhci_softc; 1003 LOCK_INIT(sc); 1004 1005 rv = get_fdt_resources(sc, node); 1006 if (rv != 0) { 1007 rv = ENXIO; 1008 goto error; 1009 } 1010 rv = enable_fdt_resources(sc); 1011 if (rv != 0) { 1012 rv = ENXIO; 1013 goto error; 1014 } 1015 1016 /* Allocate resources. */ 1017 rid = 0; 1018 xsc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1019 RF_ACTIVE); 1020 if (xsc->sc_io_res == NULL) { 1021 device_printf(dev, 1022 "Could not allocate HCD memory resources\n"); 1023 rv = ENXIO; 1024 goto error; 1025 } 1026 rid = 1; 1027 sc->mem_res_fpci = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1028 RF_ACTIVE); 1029 if (sc->mem_res_fpci == NULL) { 1030 device_printf(dev, 1031 "Could not allocate FPCI memory resources\n"); 1032 rv = ENXIO; 1033 goto error; 1034 } 1035 rid = 2; 1036 sc->mem_res_ipfs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1037 RF_ACTIVE); 1038 if (sc->mem_res_ipfs == NULL) { 1039 device_printf(dev, 1040 "Could not allocate IPFS memory resources\n"); 1041 rv = ENXIO; 1042 goto error; 1043 } 1044 1045 rid = 0; 1046 xsc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1047 RF_ACTIVE); 1048 if (xsc->sc_irq_res == NULL) { 1049 device_printf(dev, "Could not allocate HCD IRQ resources\n"); 1050 rv = ENXIO; 1051 goto error; 1052 } 1053 rid = 1; 1054 sc->irq_res_mbox = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1055 RF_ACTIVE); 1056 if (sc->irq_res_mbox == NULL) { 1057 device_printf(dev, "Could not allocate MBOX IRQ resources\n"); 1058 rv = ENXIO; 1059 goto error; 1060 } 1061 1062 rv = init_hw(sc); 1063 if (rv != 0) { 1064 device_printf(dev, "Could not initialize XUSB hardware\n"); 1065 goto error; 1066 } 1067 1068 /* Wakeup and enable firmaware */ 1069 rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0); 1070 if (rv != 0) { 1071 device_printf(sc->dev, "Could not enable XUSB firmware\n"); 1072 goto error; 1073 } 1074 1075 /* Fill data for XHCI driver. */ 1076 xsc->sc_bus.parent = dev; 1077 xsc->sc_bus.devices = xsc->sc_devices; 1078 xsc->sc_bus.devices_max = XHCI_MAX_DEVICES; 1079 1080 xsc->sc_io_tag = rman_get_bustag(xsc->sc_io_res); 1081 xsc->sc_io_hdl = rman_get_bushandle(xsc->sc_io_res); 1082 xsc->sc_io_size = rman_get_size(xsc->sc_io_res); 1083 strlcpy(xsc->sc_vendor, "Nvidia", sizeof(xsc->sc_vendor)); 1084 1085 /* Add USB bus device. */ 1086 xsc->sc_bus.bdev = device_add_child(sc->dev, "usbus", -1); 1087 if (xsc->sc_bus.bdev == NULL) { 1088 device_printf(sc->dev, "Could not add USB device\n"); 1089 rv = ENXIO; 1090 goto error; 1091 } 1092 device_set_ivars(xsc->sc_bus.bdev, &xsc->sc_bus); 1093 device_set_desc(xsc->sc_bus.bdev, "Nvidia USB 3.0 controller"); 1094 1095 rv = xhci_init(xsc, sc->dev, 1); 1096 if (rv != 0) { 1097 device_printf(sc->dev, "USB init failed: %d\n", rv); 1098 goto error; 1099 } 1100 sc->xhci_inited = true; 1101 rv = xhci_start_controller(xsc); 1102 if (rv != 0) { 1103 device_printf(sc->dev, 1104 "Could not start XHCI controller: %d\n", rv); 1105 goto error; 1106 } 1107 1108 rv = bus_setup_intr(dev, sc->irq_res_mbox, INTR_TYPE_MISC | INTR_MPSAFE, 1109 NULL, intr_mbox, sc, &sc->irq_hdl_mbox); 1110 if (rv != 0) { 1111 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1112 xsc->sc_intr_hdl = NULL; 1113 goto error; 1114 } 1115 1116 rv = bus_setup_intr(dev, xsc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1117 NULL, (driver_intr_t *)xhci_interrupt, xsc, &xsc->sc_intr_hdl); 1118 if (rv != 0) { 1119 device_printf(dev, "Could not setup error IRQ: %d\n",rv); 1120 xsc->sc_intr_hdl = NULL; 1121 goto error; 1122 } 1123 1124 /* Probe the bus. */ 1125 rv = device_probe_and_attach(xsc->sc_bus.bdev); 1126 if (rv != 0) { 1127 device_printf(sc->dev, "Could not initialize USB: %d\n", rv); 1128 goto error; 1129 } 1130 1131 return (0); 1132 1133 error: 1134 panic("XXXXX"); 1135 tegra_xhci_detach(dev); 1136 return (rv); 1137 } 1138 1139 static device_method_t xhci_methods[] = { 1140 /* Device interface */ 1141 DEVMETHOD(device_probe, tegra_xhci_probe), 1142 DEVMETHOD(device_attach, tegra_xhci_attach), 1143 DEVMETHOD(device_detach, tegra_xhci_detach), 1144 DEVMETHOD(device_suspend, bus_generic_suspend), 1145 DEVMETHOD(device_resume, bus_generic_resume), 1146 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1147 1148 /* Bus interface */ 1149 DEVMETHOD(bus_print_child, bus_generic_print_child), 1150 1151 DEVMETHOD_END 1152 }; 1153 1154 static devclass_t xhci_devclass; 1155 static DEFINE_CLASS_0(xhci, xhci_driver, xhci_methods, 1156 sizeof(struct tegra_xhci_softc)); 1157 DRIVER_MODULE(tegra_xhci, simplebus, xhci_driver, xhci_devclass, NULL, NULL); 1158 MODULE_DEPEND(tegra_xhci, usb, 1, 1, 1); 1159