1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 31 /* 32 * USB phy driver for Tegra SoCs. 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 42 #include <machine/bus.h> 43 #include <machine/fdt.h> 44 45 #include <dev/extres/clk/clk.h> 46 #include <dev/extres/hwreset/hwreset.h> 47 #include <dev/extres/phy/phy.h> 48 #include <dev/extres/regulator/regulator.h> 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/fdt/fdt_pinctrl.h> 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include "phy_if.h" 56 57 #define CTRL_ICUSB_CTRL 0x15c 58 #define ICUSB_CTR_IC_ENB1 (1 << 3) 59 60 #define CTRL_USB_USBMODE 0x1f8 61 #define USB_USBMODE_MASK (3 << 0) 62 #define USB_USBMODE_HOST (3 << 0) 63 #define USB_USBMODE_DEVICE (2 << 0) 64 65 #define CTRL_USB_HOSTPC1_DEVLC 0x1b4 66 #define USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) 67 #define USB_HOSTPC1_DEVLC_STS (1 << 28) 68 #define USB_HOSTPC1_DEVLC_PHCD (1 << 22) 69 70 71 #define IF_USB_SUSP_CTRL 0x400 72 #define FAST_WAKEUP_RESP (1 << 26) 73 #define UTMIP_SUSPL1_SET (1 << 25) 74 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 75 #define USB_SUSP_SET (1 << 14) 76 #define UTMIP_PHY_ENB (1 << 12) 77 #define UTMIP_RESET (1 << 11) 78 #define USB_SUSP_POL (1 << 10) 79 #define USB_PHY_CLK_VALID_INT_ENB (1 << 9) 80 #define USB_PHY_CLK_VALID_INT_STS (1 << 8) 81 #define USB_PHY_CLK_VALID (1 << 7) 82 #define USB_CLKEN (1 << 6) 83 #define USB_SUSP_CLR (1 << 5) 84 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 85 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 86 #define USB_WAKE_ON_RESUME_EN (1 << 2) 87 #define USB_WAKEUP_INT_ENB (1 << 1) 88 #define USB_WAKEUP_INT_STS (1 << 0) 89 90 #define IF_USB_PHY_VBUS_SENSORS 0x404 91 #define B_SESS_END_SW_VALUE (1 << 4) 92 #define B_SESS_END_SW_EN (1 << 3) 93 94 95 #define UTMIP_XCVR_CFG0 0x808 96 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) 97 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) 98 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) 99 #define UTMIP_XCVR_DISCON_METHOD (1 << 20) 100 #define UTMIP_FORCE_PDZI_POWERUP (1 << 19) 101 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 102 #define UTMIP_FORCE_PD2_POWERUP (1 << 17) 103 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 104 #define UTMIP_FORCE_PD_POWERUP (1 << 15) 105 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 106 #define UTMIP_XCVR_TERMEN (1 << 13) 107 #define UTMIP_XCVR_HSLOOPBACK (1 << 12) 108 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 109 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 110 #define UTMIP_XCVR_FSSLEW(x) (((x) & 0x3) << 6) 111 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) 112 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 113 114 #define UTMIP_BIAS_CFG0 0x80C 115 #define UTMIP_IDDIG_C_VAL (1 << 30) 116 #define UTMIP_IDDIG_C_SEL (1 << 29) 117 #define UTMIP_IDDIG_B_VAL (1 << 28) 118 #define UTMIP_IDDIG_B_SEL (1 << 27) 119 #define UTMIP_IDDIG_A_VAL (1 << 26) 120 #define UTMIP_IDDIG_A_SEL (1 << 25) 121 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) 122 #define UTMIP_IDPD_VAL (1 << 23) 123 #define UTMIP_IDPD_SEL (1 << 22) 124 #define UTMIP_IDDIG_VAL (1 << 21) 125 #define UTMIP_IDDIG_SEL (1 << 20) 126 #define UTMIP_GPI_VAL (1 << 19) 127 #define UTMIP_GPI_SEL (1 << 18) 128 #define UTMIP_ACTIVE_TERM_OFFSET(x) (((x) & 0x7) << 15) 129 #define UTMIP_ACTIVE_PULLUP_OFFSET(x) (((x) & 0x7) << 12) 130 #define UTMIP_OTGPD (1 << 11) 131 #define UTMIP_BIASPD (1 << 10) 132 #define UTMIP_VBUS_LEVEL_LEVEL(x) (((x) & 0x3) << 8) 133 #define UTMIP_SESS_LEVEL_LEVEL(x) (((x) & 0x3) << 6) 134 #define UTMIP_HSCHIRP_LEVEL(x) (((x) & 0x3) << 4) 135 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) 136 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) 137 138 139 #define UTMIP_HSRX_CFG0 0x810 140 #define UTMIP_KEEP_PATT_ON_ACTIVE(x) (((x) & 0x3) << 30) 141 #define UTMIP_ALLOW_CONSEC_UPDN (1 << 29) 142 #define UTMIP_REALIGN_ON_NEW_PKT (1 << 28) 143 #define UTMIP_PCOUNT_UPDN_DIV(x) (((x) & 0xf) << 24) 144 #define UTMIP_SQUELCH_EOP_DLY(x) (((x) & 0x7) << 21) 145 #define UTMIP_NO_STRIPPING (1 << 20) 146 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 147 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 148 #define UTMIP_ELASTIC_OVERRUN_DISABLE (1 << 9) 149 #define UTMIP_ELASTIC_UNDERRUN_DISABLE (1 << 8) 150 #define UTMIP_PASS_CHIRP (1 << 7) 151 #define UTMIP_PASS_FEEDBACK (1 << 6) 152 #define UTMIP_PCOUNT_INERTIA(x) (((x) & 0x3) << 4) 153 #define UTMIP_PHASE_ADJUST(x) (((x) & 0x3) << 2) 154 #define UTMIP_THREE_SYNCBITS (1 << 1) 155 #define UTMIP_USE4SYNC_TRAN (1 << 0) 156 157 #define UTMIP_HSRX_CFG1 0x814 158 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1F) << 1) 159 #define UTMIP_HS_ALLOW_KEEP_ALIVE (1 << 0) 160 161 #define UTMIP_TX_CFG0 0x820 162 #define UTMIP_FS_PREAMBLE_J (1 << 19) 163 #define UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE (1 << 18) 164 #define UTMIP_FS_PREAMBLE_OUTPUT_ENABLE (1 << 17) 165 #define UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR (1 << 16) 166 #define UTMIP_HS_READY_WAIT_FOR_VALID (1 << 15) 167 #define UTMIP_HS_TX_IPG_DLY(x) (((x) & 0x1f) << 10) 168 #define UTMIP_HS_DISCON_EOP_ONLY (1 << 9) 169 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 170 #define UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE (1 << 7) 171 #define UTMIP_HS_PREAMBLE_OUTPUT_ENABLE (1 << 6) 172 #define UTMIP_SIE_RESUME_ON_LINESTATE (1 << 5) 173 #define UTMIP_SOF_ON_NO_STUFF (1 << 4) 174 #define UTMIP_SOF_ON_NO_ENCODE (1 << 3) 175 #define UTMIP_NO_STUFFING (1 << 2) 176 #define UTMIP_NO_ENCODING (1 << 1) 177 #define UTMIP_NO_SYNC_NO_EOP (1 << 0) 178 179 #define UTMIP_MISC_CFG0 0x824 180 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 181 #define UTMIP_DPDM_OBSERVE (1 << 26) 182 #define UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON (1 << 25) 183 #define UTMIP_ALLOW_LS_ON_SOFT_DISCON (1 << 24) 184 #define UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP (1 << 23) 185 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 186 #define UTMIP_LS_TO_FS_SKIP_4MS (1 << 21) 187 #define UTMIP_INJECT_ERROR_TYPE(x) (((x) & 0x3) << 19) 188 #define UTMIP_FORCE_HS_CLOCK_ON (1 << 18) 189 #define UTMIP_DISABLE_HS_TERM (1 << 17) 190 #define UTMIP_FORCE_HS_TERM (1 << 16) 191 #define UTMIP_DISABLE_PULLUP_DP (1 << 15) 192 #define UTMIP_DISABLE_PULLUP_DM (1 << 14) 193 #define UTMIP_DISABLE_PULLDN_DP (1 << 13) 194 #define UTMIP_DISABLE_PULLDN_DM (1 << 12) 195 #define UTMIP_FORCE_PULLUP_DP (1 << 11) 196 #define UTMIP_FORCE_PULLUP_DM (1 << 10) 197 #define UTMIP_FORCE_PULLDN_DP (1 << 9) 198 #define UTMIP_FORCE_PULLDN_DM (1 << 8) 199 #define UTMIP_STABLE_COUNT(x) (((x) & 0x7) << 5) 200 #define UTMIP_STABLE_ALL (1 << 4) 201 #define UTMIP_NO_FREE_ON_SUSPEND (1 << 3) 202 #define UTMIP_NEVER_FREE_RUNNING_TERMS (1 << 2) 203 #define UTMIP_ALWAYS_FREE_RUNNING_TERMS (1 << 1) 204 #define UTMIP_COMB_TERMS (1 << 0) 205 206 #define UTMIP_MISC_CFG1 0x828 207 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) 208 209 #define UTMIP_DEBOUNCE_CFG0 0x82C 210 #define UTMIP_BIAS_DEBOUNCE_B(x) (((x) & 0xffff) << 16) 211 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 212 213 #define UTMIP_BAT_CHRG_CFG0 0x830 214 #define UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) (((x) & 0x1f) << 8) 215 #define UTMIP_OP_I_SRC_ENG (1 << 5) 216 #define UTMIP_ON_SRC_ENG (1 << 4) 217 #define UTMIP_OP_SRC_ENG (1 << 3) 218 #define UTMIP_ON_SINK_ENG (1 << 2) 219 #define UTMIP_OP_SINK_ENG (1 << 1) 220 #define UTMIP_PD_CHRG (1 << 0) 221 222 #define UTMIP_SPARE_CFG0 0x834 223 #define FUSE_HS_IREF_CAP_CFG (1 << 7) 224 #define FUSE_HS_SQUELCH_LEVEL (1 << 6) 225 #define FUSE_SPARE (1 << 5) 226 #define FUSE_TERM_RANGE_ADJ_SEL (1 << 4) 227 #define FUSE_SETUP_SEL (1 << 3) 228 #define HS_RX_LATE_SQUELCH (1 << 2) 229 #define HS_RX_FLUSH_ALAP (1 << 1) 230 #define HS_RX_IPG_ERROR_ENABLE (1 << 0) 231 232 #define UTMIP_XCVR_CFG1 0x838 233 #define UTMIP_XCVR_RPU_RANGE_ADJ(x) (((x) & 0x3) << 26) 234 #define UTMIP_XCVR_HS_IREF_CAP(x) (((x) & 0x3) << 24) 235 #define UTMIP_XCVR_SPARE(x) (((x) & 0x3) << 22) 236 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 237 #define UTMIP_RCTRL_SW_SET (1 << 17) 238 #define UTMIP_RCTRL_SW_VAL(x) (((x) & 0x1f) << 12) 239 #define UTMIP_TCTRL_SW_SET (1 << 11) 240 #define UTMIP_TCTRL_SW_VAL(x) (((x) & 0x1f) << 6) 241 #define UTMIP_FORCE_PDDR_POWERUP (1 << 5) 242 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 243 #define UTMIP_FORCE_PDCHRP_POWERUP (1 << 3) 244 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 245 #define UTMIP_FORCE_PDDISC_POWERUP (1 << 1) 246 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 247 248 #define UTMIP_BIAS_CFG1 0x83c 249 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE(x) (((x) & 0x3f) << 8) 250 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 251 #define UTMIP_VBUS_WAKEUP_POWERDOWN (1 << 2) 252 #define UTMIP_FORCE_PDTRK_POWERUP (1 << 1) 253 #define UTMIP_FORCE_PDTRK_POWERDOWN (1 << 0) 254 255 static int usbpby_enable_cnt; 256 257 enum usb_ifc_type { 258 USB_IFC_TYPE_UNKNOWN = 0, 259 USB_IFC_TYPE_UTMI, 260 USB_IFC_TYPE_ULPI 261 }; 262 263 enum usb_dr_mode { 264 USB_DR_MODE_UNKNOWN = 0, 265 USB_DR_MODE_DEVICE, 266 USB_DR_MODE_HOST, 267 USB_DR_MODE_OTG 268 }; 269 270 struct usbphy_softc { 271 device_t dev; 272 struct resource *mem_res; 273 struct resource *pads_res; 274 clk_t clk_reg; 275 clk_t clk_pads; 276 clk_t clk_pllu; 277 regulator_t supply_vbus; 278 hwreset_t reset_usb; 279 hwreset_t reset_pads; 280 enum usb_ifc_type ifc_type; 281 enum usb_dr_mode dr_mode; 282 bool have_utmi_regs; 283 284 /* UTMI params */ 285 int hssync_start_delay; 286 int elastic_limit; 287 int idle_wait_delay; 288 int term_range_adj; 289 int xcvr_lsfslew; 290 int xcvr_lsrslew; 291 int xcvr_hsslew; 292 int hssquelch_level; 293 int hsdiscon_level; 294 int xcvr_setup; 295 int xcvr_setup_use_fuses; 296 }; 297 298 static struct ofw_compat_data compat_data[] = { 299 {"nvidia,tegra30-usb-phy", 1}, 300 {NULL, 0}, 301 }; 302 303 #define RD4(sc, offs) \ 304 bus_read_4(sc->mem_res, offs) 305 306 #define WR4(sc, offs, val) \ 307 bus_write_4(sc->mem_res, offs, val) 308 309 static int 310 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val) 311 { 312 int i; 313 314 for (i = 0; i < 1000; i++) { 315 if ((RD4(sc, reg) & mask) == val) 316 return (0); 317 DELAY(10); 318 } 319 return (ETIMEDOUT); 320 } 321 322 static int 323 usbphy_utmi_phy_clk(struct usbphy_softc *sc, bool enable) 324 { 325 uint32_t val; 326 int rv; 327 328 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 329 if (enable) 330 val &= ~USB_HOSTPC1_DEVLC_PHCD; 331 else 332 val |= USB_HOSTPC1_DEVLC_PHCD; 333 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 334 335 rv = reg_wait(sc, IF_USB_SUSP_CTRL, USB_PHY_CLK_VALID, 336 enable ? USB_PHY_CLK_VALID: 0); 337 if (rv != 0) { 338 device_printf(sc->dev, "USB phy clock timeout.\n"); 339 return (ETIMEDOUT); 340 } 341 return (0); 342 } 343 344 static int 345 usbphy_utmi_enable(struct usbphy_softc *sc) 346 { 347 int rv; 348 uint32_t val; 349 350 /* Reset phy */ 351 val = RD4(sc, IF_USB_SUSP_CTRL); 352 val |= UTMIP_RESET; 353 WR4(sc, IF_USB_SUSP_CTRL, val); 354 355 356 val = RD4(sc, UTMIP_TX_CFG0); 357 val |= UTMIP_FS_PREAMBLE_J; 358 WR4(sc, UTMIP_TX_CFG0, val); 359 360 val = RD4(sc, UTMIP_HSRX_CFG0); 361 val &= ~UTMIP_IDLE_WAIT(~0); 362 val &= ~UTMIP_ELASTIC_LIMIT(~0); 363 val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay); 364 val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit); 365 WR4(sc, UTMIP_HSRX_CFG0, val); 366 367 val = RD4(sc, UTMIP_HSRX_CFG1); 368 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 369 val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay); 370 WR4(sc, UTMIP_HSRX_CFG1, val); 371 372 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); 373 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 374 val |= UTMIP_BIAS_DEBOUNCE_A(0x7530); /* For 12MHz */ 375 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); 376 377 val = RD4(sc, UTMIP_MISC_CFG0); 378 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 379 WR4(sc, UTMIP_MISC_CFG0, val); 380 381 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 382 val = RD4(sc,IF_USB_SUSP_CTRL); 383 val &= ~USB_WAKE_ON_CNNT_EN_DEV; 384 val &= ~USB_WAKE_ON_DISCON_EN_DEV; 385 WR4(sc, IF_USB_SUSP_CTRL, val); 386 387 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 388 val &= ~UTMIP_PD_CHRG; 389 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 390 } else { 391 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 392 val |= UTMIP_PD_CHRG; 393 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 394 } 395 396 usbpby_enable_cnt++; 397 if (usbpby_enable_cnt == 1) { 398 rv = hwreset_deassert(sc->reset_pads); 399 if (rv != 0) { 400 device_printf(sc->dev, 401 "Cannot unreset 'utmi-pads' reset\n"); 402 return (rv); 403 } 404 rv = clk_enable(sc->clk_pads); 405 if (rv != 0) { 406 device_printf(sc->dev, 407 "Cannot enable 'utmi-pads' clock\n"); 408 return (rv); 409 } 410 411 val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 412 val &= ~UTMIP_OTGPD; 413 val &= ~UTMIP_BIASPD; 414 val &= ~UTMIP_HSSQUELCH_LEVEL(~0); 415 val &= ~UTMIP_HSDISCON_LEVEL(~0); 416 val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0); 417 val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level); 418 val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level); 419 val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level); 420 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 421 422 rv = clk_disable(sc->clk_pads); 423 if (rv != 0) { 424 device_printf(sc->dev, 425 "Cannot disable 'utmi-pads' clock\n"); 426 return (rv); 427 } 428 } 429 430 val = RD4(sc, UTMIP_XCVR_CFG0); 431 val &= ~UTMIP_FORCE_PD_POWERDOWN; 432 val &= ~UTMIP_FORCE_PD2_POWERDOWN ; 433 val &= ~UTMIP_FORCE_PDZI_POWERDOWN; 434 val &= ~UTMIP_XCVR_LSBIAS_SEL; 435 val &= ~UTMIP_XCVR_LSFSLEW(~0); 436 val &= ~UTMIP_XCVR_LSRSLEW(~0); 437 val &= ~UTMIP_XCVR_HSSLEW(~0); 438 val &= ~UTMIP_XCVR_HSSLEW_MSB(~0); 439 val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew); 440 val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew); 441 val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew); 442 val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew); 443 if (!sc->xcvr_setup_use_fuses) { 444 val &= ~UTMIP_XCVR_SETUP(~0); 445 val &= ~UTMIP_XCVR_SETUP_MSB(~0); 446 val |= UTMIP_XCVR_SETUP(sc->xcvr_setup); 447 val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup); 448 } 449 WR4(sc, UTMIP_XCVR_CFG0, val); 450 451 val = RD4(sc, UTMIP_XCVR_CFG1); 452 val &= ~UTMIP_FORCE_PDDISC_POWERDOWN; 453 val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN; 454 val &= ~UTMIP_FORCE_PDDR_POWERDOWN; 455 val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0); 456 val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj); 457 WR4(sc, UTMIP_XCVR_CFG1, val); 458 459 460 val = RD4(sc, UTMIP_BIAS_CFG1); 461 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 462 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 463 WR4(sc, UTMIP_BIAS_CFG1, val); 464 465 val = RD4(sc, UTMIP_SPARE_CFG0); 466 if (sc->xcvr_setup_use_fuses) 467 val |= FUSE_SETUP_SEL; 468 else 469 val &= ~FUSE_SETUP_SEL; 470 WR4(sc, UTMIP_SPARE_CFG0, val); 471 472 val = RD4(sc, IF_USB_SUSP_CTRL); 473 val |= UTMIP_PHY_ENB; 474 WR4(sc, IF_USB_SUSP_CTRL, val); 475 476 val = RD4(sc, IF_USB_SUSP_CTRL); 477 val &= ~UTMIP_RESET; 478 WR4(sc, IF_USB_SUSP_CTRL, val); 479 480 usbphy_utmi_phy_clk(sc, true); 481 482 val = RD4(sc, CTRL_USB_USBMODE); 483 val &= ~USB_USBMODE_MASK; 484 if (sc->dr_mode == USB_DR_MODE_HOST) 485 val |= USB_USBMODE_HOST; 486 else 487 val |= USB_USBMODE_DEVICE; 488 WR4(sc, CTRL_USB_USBMODE, val); 489 490 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); 491 val &= ~USB_HOSTPC1_DEVLC_PTS(~0); 492 val |= USB_HOSTPC1_DEVLC_PTS(0); 493 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 494 495 return (0); 496 } 497 498 static int 499 usbphy_utmi_disable(struct usbphy_softc *sc) 500 { 501 int rv; 502 uint32_t val; 503 504 usbphy_utmi_phy_clk(sc, false); 505 506 if (sc->dr_mode == USB_DR_MODE_DEVICE) { 507 val = RD4(sc, IF_USB_SUSP_CTRL); 508 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 509 val |= USB_WAKE_ON_CNNT_EN_DEV; 510 val |= USB_WAKEUP_DEBOUNCE_COUNT(5); 511 WR4(sc, IF_USB_SUSP_CTRL, val); 512 } 513 514 val = RD4(sc, IF_USB_SUSP_CTRL); 515 val |= UTMIP_RESET; 516 WR4(sc, IF_USB_SUSP_CTRL, val); 517 518 val = RD4(sc, UTMIP_BAT_CHRG_CFG0); 519 val |= UTMIP_PD_CHRG; 520 WR4(sc, UTMIP_BAT_CHRG_CFG0, val); 521 522 val = RD4(sc, UTMIP_XCVR_CFG0); 523 val |= UTMIP_FORCE_PD_POWERDOWN; 524 val |= UTMIP_FORCE_PD2_POWERDOWN; 525 val |= UTMIP_FORCE_PDZI_POWERDOWN; 526 WR4(sc, UTMIP_XCVR_CFG0, val); 527 528 val = RD4(sc, UTMIP_XCVR_CFG1); 529 val |= UTMIP_FORCE_PDDISC_POWERDOWN; 530 val |= UTMIP_FORCE_PDCHRP_POWERDOWN; 531 val |= UTMIP_FORCE_PDDR_POWERDOWN; 532 WR4(sc, UTMIP_XCVR_CFG1, val); 533 534 usbpby_enable_cnt--; 535 if (usbpby_enable_cnt <= 0) { 536 rv = clk_enable(sc->clk_pads); 537 if (rv != 0) { 538 device_printf(sc->dev, 539 "Cannot enable 'utmi-pads' clock\n"); 540 return (rv); 541 } 542 val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0); 543 val |= UTMIP_OTGPD; 544 val |= UTMIP_BIASPD; 545 bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val); 546 547 rv = clk_disable(sc->clk_pads); 548 if (rv != 0) { 549 device_printf(sc->dev, 550 "Cannot disable 'utmi-pads' clock\n"); 551 return (rv); 552 } 553 } 554 return (0); 555 } 556 557 static int 558 usbphy_phy_enable(device_t dev, int id, bool enable) 559 { 560 struct usbphy_softc *sc; 561 int rv = 0; 562 563 sc = device_get_softc(dev); 564 565 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 566 device_printf(sc->dev, 567 "Only UTMI interface is supported.\n"); 568 return (ENXIO); 569 } 570 if (enable) 571 rv = usbphy_utmi_enable(sc); 572 else 573 rv = usbphy_utmi_disable(sc); 574 575 return (rv); 576 } 577 578 static enum usb_ifc_type 579 usb_get_ifc_mode(device_t dev, phandle_t node, char *name) 580 { 581 char *tmpstr; 582 int rv; 583 enum usb_ifc_type ret; 584 585 rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr); 586 if (rv <= 0) 587 return (USB_IFC_TYPE_UNKNOWN); 588 589 ret = USB_IFC_TYPE_UNKNOWN; 590 if (strcmp(tmpstr, "utmi") == 0) 591 ret = USB_IFC_TYPE_UTMI; 592 else if (strcmp(tmpstr, "ulpi") == 0) 593 ret = USB_IFC_TYPE_ULPI; 594 else 595 device_printf(dev, "Unsupported phy type: %s\n", tmpstr); 596 free(tmpstr, M_OFWPROP); 597 return (ret); 598 } 599 600 static enum usb_dr_mode 601 usb_get_dr_mode(device_t dev, phandle_t node, char *name) 602 { 603 char *tmpstr; 604 int rv; 605 enum usb_dr_mode ret; 606 607 rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr); 608 if (rv <= 0) 609 return (USB_DR_MODE_UNKNOWN); 610 611 ret = USB_DR_MODE_UNKNOWN; 612 if (strcmp(tmpstr, "device") == 0) 613 ret = USB_DR_MODE_DEVICE; 614 else if (strcmp(tmpstr, "host") == 0) 615 ret = USB_DR_MODE_HOST; 616 else if (strcmp(tmpstr, "otg") == 0) 617 ret = USB_DR_MODE_OTG; 618 else 619 device_printf(dev, "Unknown dr mode: %s\n", tmpstr); 620 free(tmpstr, M_OFWPROP); 621 return (ret); 622 } 623 624 static int 625 usbphy_utmi_read_params(struct usbphy_softc *sc, phandle_t node) 626 { 627 int rv; 628 629 rv = OF_getencprop(node, "nvidia,hssync-start-delay", 630 &sc->hssync_start_delay, sizeof (sc->hssync_start_delay)); 631 if (rv <= 0) 632 return (ENXIO); 633 634 rv = OF_getencprop(node, "nvidia,elastic-limit", 635 &sc->elastic_limit, sizeof (sc->elastic_limit)); 636 if (rv <= 0) 637 return (ENXIO); 638 639 rv = OF_getencprop(node, "nvidia,idle-wait-delay", 640 &sc->idle_wait_delay, sizeof (sc->idle_wait_delay)); 641 if (rv <= 0) 642 return (ENXIO); 643 644 rv = OF_getencprop(node, "nvidia,term-range-adj", 645 &sc->term_range_adj, sizeof (sc->term_range_adj)); 646 if (rv <= 0) 647 return (ENXIO); 648 649 rv = OF_getencprop(node, "nvidia,xcvr-lsfslew", 650 &sc->xcvr_lsfslew, sizeof (sc->xcvr_lsfslew)); 651 if (rv <= 0) 652 return (ENXIO); 653 654 rv = OF_getencprop(node, "nvidia,xcvr-lsrslew", 655 &sc->xcvr_lsrslew, sizeof (sc->xcvr_lsrslew)); 656 if (rv <= 0) 657 return (ENXIO); 658 659 rv = OF_getencprop(node, "nvidia,xcvr-hsslew", 660 &sc->xcvr_hsslew, sizeof (sc->xcvr_hsslew)); 661 if (rv <= 0) 662 return (ENXIO); 663 664 rv = OF_getencprop(node, "nvidia,hssquelch-level", 665 &sc->hssquelch_level, sizeof (sc->hssquelch_level)); 666 if (rv <= 0) 667 return (ENXIO); 668 669 rv = OF_getencprop(node, "nvidia,hsdiscon-level", 670 &sc->hsdiscon_level, sizeof (sc->hsdiscon_level)); 671 if (rv <= 0) 672 return (ENXIO); 673 674 rv = OF_getproplen(node, "nvidia,xcvr-setup-use-fuses"); 675 if (rv >= 1) { 676 sc->xcvr_setup_use_fuses = 1; 677 } else { 678 rv = OF_getencprop(node, "nvidia,xcvr-setup", 679 &sc->xcvr_setup, sizeof (sc->xcvr_setup)); 680 if (rv <= 0) 681 return (ENXIO); 682 } 683 684 return (0); 685 } 686 687 static int 688 usbphy_probe(device_t dev) 689 { 690 691 if (!ofw_bus_status_okay(dev)) 692 return (ENXIO); 693 694 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 695 return (ENXIO); 696 697 device_set_desc(dev, "Tegra USB phy"); 698 return (BUS_PROBE_DEFAULT); 699 } 700 701 static int 702 usbphy_attach(device_t dev) 703 { 704 struct usbphy_softc * sc; 705 int rid, rv; 706 phandle_t node; 707 708 sc = device_get_softc(dev); 709 sc->dev = dev; 710 711 rid = 0; 712 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 713 RF_ACTIVE | RF_SHAREABLE); 714 if (sc->mem_res == NULL) { 715 device_printf(dev, "Cannot allocate memory resources\n"); 716 return (ENXIO); 717 } 718 719 rid = 1; 720 sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 721 RF_ACTIVE | RF_SHAREABLE); 722 if (sc->mem_res == NULL) { 723 device_printf(dev, "Cannot allocate memory resources\n"); 724 return (ENXIO); 725 } 726 727 node = ofw_bus_get_node(dev); 728 729 rv = hwreset_get_by_ofw_name(sc->dev, "usb", &sc->reset_usb); 730 if (rv != 0) { 731 device_printf(dev, "Cannot get 'usb' reset\n"); 732 return (ENXIO); 733 } 734 rv = hwreset_get_by_ofw_name(sc->dev, "utmi-pads", &sc->reset_pads); 735 if (rv != 0) { 736 device_printf(dev, "Cannot get 'utmi-pads' reset\n"); 737 return (ENXIO); 738 } 739 740 rv = clk_get_by_ofw_name(sc->dev, "reg", &sc->clk_reg); 741 if (rv != 0) { 742 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 743 return (ENXIO); 744 } 745 rv = clk_get_by_ofw_name(sc->dev, "pll_u", &sc->clk_pllu); 746 if (rv != 0) { 747 device_printf(sc->dev, "Cannot get 'pll_u' clock\n"); 748 return (ENXIO); 749 } 750 rv = clk_get_by_ofw_name(sc->dev, "utmi-pads", &sc->clk_pads); 751 if (rv != 0) { 752 device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n"); 753 return (ENXIO); 754 } 755 756 rv = hwreset_deassert(sc->reset_usb); 757 if (rv != 0) { 758 device_printf(dev, "Cannot unreset 'usb' reset\n"); 759 return (ENXIO); 760 } 761 762 rv = clk_enable(sc->clk_pllu); 763 if (rv != 0) { 764 device_printf(sc->dev, "Cannot enable 'pllu' clock\n"); 765 return (ENXIO); 766 } 767 rv = clk_enable(sc->clk_reg); 768 if (rv != 0) { 769 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 770 return (ENXIO); 771 } 772 if (OF_hasprop(node, "nvidia,has-utmi-pad-registers")) 773 sc->have_utmi_regs = true; 774 775 sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode"); 776 if (sc->dr_mode == USB_DR_MODE_UNKNOWN) 777 sc->dr_mode = USB_DR_MODE_HOST; 778 779 sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type"); 780 781 /* We supports only utmi phy mode for now .... */ 782 if (sc->ifc_type != USB_IFC_TYPE_UTMI) { 783 device_printf(dev, "Unsupported phy type\n"); 784 return (ENXIO); 785 } 786 rv = usbphy_utmi_read_params(sc, node); 787 if (rv < 0) 788 return rv; 789 790 if (OF_hasprop(node, "vbus-supply")) { 791 rv = regulator_get_by_ofw_property(sc->dev, "vbus-supply", 792 &sc->supply_vbus); 793 if (rv != 0) { 794 device_printf(sc->dev, 795 "Cannot get \"vbus\" regulator\n"); 796 return (ENXIO); 797 } 798 rv = regulator_enable(sc->supply_vbus); 799 if (rv != 0) { 800 device_printf(sc->dev, 801 "Cannot enable \"vbus\" regulator\n"); 802 return (rv); 803 } 804 } 805 806 phy_register_provider(dev); 807 return (0); 808 } 809 810 static int 811 usbphy_detach(device_t dev) 812 { 813 814 /* This device is always present. */ 815 return (EBUSY); 816 } 817 818 static device_method_t tegra_usbphy_methods[] = { 819 /* Device interface */ 820 DEVMETHOD(device_probe, usbphy_probe), 821 DEVMETHOD(device_attach, usbphy_attach), 822 DEVMETHOD(device_detach, usbphy_detach), 823 824 /* phy interface */ 825 DEVMETHOD(phy_enable, usbphy_phy_enable), 826 827 DEVMETHOD_END 828 }; 829 830 static driver_t tegra_usbphy_driver = { 831 "tegra_usbphy", 832 tegra_usbphy_methods, 833 sizeof(struct usbphy_softc), 834 }; 835 836 static devclass_t tegra_usbphy_devclass; 837 838 EARLY_DRIVER_MODULE(tegra_usbphy, simplebus, tegra_usbphy_driver, 839 tegra_usbphy_devclass, 0, 0, 79); 840