xref: /freebsd/sys/arm/nvidia/tegra_usbphy.c (revision 396c556d77189a5c474d35cec6f44a762e310b7d)
1 /*-
2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 
31 /*
32  * USB phy driver for Tegra SoCs.
33  */
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/rman.h>
41 
42 #include <machine/bus.h>
43 #include <machine/fdt.h>
44 
45 #include <dev/extres/clk/clk.h>
46 #include <dev/extres/hwreset/hwreset.h>
47 #include <dev/extres/phy/phy.h>
48 #include <dev/extres/regulator/regulator.h>
49 #include <dev/fdt/fdt_pinctrl.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
53 
54 #include "phy_if.h"
55 
56 #define	CTRL_ICUSB_CTRL			0x15c
57 #define	  ICUSB_CTR_IC_ENB1			(1 << 3)
58 
59 #define	CTRL_USB_USBMODE		0x1f8
60 #define	  USB_USBMODE_MASK			(3 << 0)
61 #define	  USB_USBMODE_HOST			(3 << 0)
62 #define	  USB_USBMODE_DEVICE			(2 << 0)
63 
64 #define	CTRL_USB_HOSTPC1_DEVLC		0x1b4
65 #define	 USB_HOSTPC1_DEVLC_PTS(x)		(((x) & 0x7) << 29)
66 #define	 USB_HOSTPC1_DEVLC_STS			(1 << 28)
67 #define	 USB_HOSTPC1_DEVLC_PHCD			(1 << 22)
68 
69 
70 #define	IF_USB_SUSP_CTRL		0x400
71 #define	 FAST_WAKEUP_RESP			(1 << 26)
72 #define	 UTMIP_SUSPL1_SET			(1 << 25)
73 #define	 USB_WAKEUP_DEBOUNCE_COUNT(x)		(((x) & 0x7) << 16)
74 #define	 USB_SUSP_SET				(1 << 14)
75 #define	 UTMIP_PHY_ENB				(1 << 12)
76 #define	 UTMIP_RESET				(1 << 11)
77 #define	 USB_SUSP_POL				(1 << 10)
78 #define	 USB_PHY_CLK_VALID_INT_ENB		(1 << 9)
79 #define	 USB_PHY_CLK_VALID_INT_STS		(1 << 8)
80 #define	 USB_PHY_CLK_VALID			(1 << 7)
81 #define	 USB_CLKEN				(1 << 6)
82 #define	 USB_SUSP_CLR				(1 << 5)
83 #define	 USB_WAKE_ON_DISCON_EN_DEV		(1 << 4)
84 #define	 USB_WAKE_ON_CNNT_EN_DEV		(1 << 3)
85 #define	 USB_WAKE_ON_RESUME_EN			(1 << 2)
86 #define	 USB_WAKEUP_INT_ENB			(1 << 1)
87 #define	 USB_WAKEUP_INT_STS			(1 << 0)
88 
89 #define	IF_USB_PHY_VBUS_SENSORS		0x404
90 #define	 B_SESS_END_SW_VALUE			(1 << 4)
91 #define	 B_SESS_END_SW_EN			(1 << 3)
92 
93 
94 #define	UTMIP_XCVR_CFG0			0x808
95 #define	 UTMIP_XCVR_HSSLEW_MSB(x)		((((x) & 0x1fc) >> 2) << 25)
96 #define	 UTMIP_XCVR_SETUP_MSB(x)		((((x) & 0x70) >> 4) << 22)
97 #define	 UTMIP_XCVR_LSBIAS_SEL			(1 << 21)
98 #define	 UTMIP_XCVR_DISCON_METHOD		(1 << 20)
99 #define	 UTMIP_FORCE_PDZI_POWERUP		(1 << 19)
100 #define	 UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
101 #define	 UTMIP_FORCE_PD2_POWERUP		(1 << 17)
102 #define	 UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
103 #define	 UTMIP_FORCE_PD_POWERUP			(1 << 15)
104 #define	 UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
105 #define	 UTMIP_XCVR_TERMEN			(1 << 13)
106 #define	 UTMIP_XCVR_HSLOOPBACK			(1 << 12)
107 #define	 UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
108 #define	 UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
109 #define	 UTMIP_XCVR_FSSLEW(x)			(((x) & 0x3) << 6)
110 #define	 UTMIP_XCVR_HSSLEW(x)			(((x) & 0x3) << 4)
111 #define	 UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
112 
113 #define	UTMIP_BIAS_CFG0			0x80C
114 #define	 UTMIP_IDDIG_C_VAL			(1 << 30)
115 #define	 UTMIP_IDDIG_C_SEL			(1 << 29)
116 #define	 UTMIP_IDDIG_B_VAL			(1 << 28)
117 #define	 UTMIP_IDDIG_B_SEL			(1 << 27)
118 #define	 UTMIP_IDDIG_A_VAL			(1 << 26)
119 #define	 UTMIP_IDDIG_A_SEL			(1 << 25)
120 #define	 UTMIP_HSDISCON_LEVEL_MSB(x)		((((x) & 0x4) >> 2) << 24)
121 #define	 UTMIP_IDPD_VAL				(1 << 23)
122 #define	 UTMIP_IDPD_SEL				(1 << 22)
123 #define	 UTMIP_IDDIG_VAL			(1 << 21)
124 #define	 UTMIP_IDDIG_SEL			(1 << 20)
125 #define	 UTMIP_GPI_VAL				(1 << 19)
126 #define	 UTMIP_GPI_SEL				(1 << 18)
127 #define	 UTMIP_ACTIVE_TERM_OFFSET(x)		(((x) & 0x7) << 15)
128 #define	 UTMIP_ACTIVE_PULLUP_OFFSET(x)		(((x) & 0x7) << 12)
129 #define	 UTMIP_OTGPD				(1 << 11)
130 #define	 UTMIP_BIASPD				(1 << 10)
131 #define	 UTMIP_VBUS_LEVEL_LEVEL(x)		(((x) & 0x3) << 8)
132 #define	 UTMIP_SESS_LEVEL_LEVEL(x)		(((x) & 0x3) << 6)
133 #define	 UTMIP_HSCHIRP_LEVEL(x)			(((x) & 0x3) << 4)
134 #define	 UTMIP_HSDISCON_LEVEL(x)		(((x) & 0x3) << 2)
135 #define	 UTMIP_HSSQUELCH_LEVEL(x)		(((x) & 0x3) << 0)
136 
137 
138 #define	UTMIP_HSRX_CFG0			0x810
139 #define	 UTMIP_KEEP_PATT_ON_ACTIVE(x)		(((x) & 0x3) << 30)
140 #define	 UTMIP_ALLOW_CONSEC_UPDN		(1 << 29)
141 #define	 UTMIP_REALIGN_ON_NEW_PKT		(1 << 28)
142 #define	 UTMIP_PCOUNT_UPDN_DIV(x)		(((x) & 0xf) << 24)
143 #define	 UTMIP_SQUELCH_EOP_DLY(x)		(((x) & 0x7) << 21)
144 #define	 UTMIP_NO_STRIPPING			(1 << 20)
145 #define	 UTMIP_IDLE_WAIT(x)			(((x) & 0x1f) << 15)
146 #define	 UTMIP_ELASTIC_LIMIT(x)			(((x) & 0x1f) << 10)
147 #define	 UTMIP_ELASTIC_OVERRUN_DISABLE		(1 << 9)
148 #define	 UTMIP_ELASTIC_UNDERRUN_DISABLE		(1 << 8)
149 #define	 UTMIP_PASS_CHIRP			(1 << 7)
150 #define	 UTMIP_PASS_FEEDBACK			(1 << 6)
151 #define	 UTMIP_PCOUNT_INERTIA(x)		(((x) & 0x3) << 4)
152 #define	 UTMIP_PHASE_ADJUST(x)			(((x) & 0x3) << 2)
153 #define	 UTMIP_THREE_SYNCBITS			(1 << 1)
154 #define	 UTMIP_USE4SYNC_TRAN			(1 << 0)
155 
156 #define	UTMIP_HSRX_CFG1			0x814
157 #define	 UTMIP_HS_SYNC_START_DLY(x)		(((x) & 0x1F) << 1)
158 #define	 UTMIP_HS_ALLOW_KEEP_ALIVE		(1 << 0)
159 
160 #define	UTMIP_TX_CFG0			0x820
161 #define	 UTMIP_FS_PREAMBLE_J			(1 << 19)
162 #define	 UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE	(1 << 18)
163 #define	 UTMIP_FS_PREAMBLE_OUTPUT_ENABLE	(1 << 17)
164 #define	 UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR	(1 << 16)
165 #define	 UTMIP_HS_READY_WAIT_FOR_VALID		(1 << 15)
166 #define	 UTMIP_HS_TX_IPG_DLY(x)			(((x) & 0x1f) << 10)
167 #define	 UTMIP_HS_DISCON_EOP_ONLY		(1 << 9)
168 #define	 UTMIP_HS_DISCON_DISABLE		(1 << 8)
169 #define	 UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE	(1 << 7)
170 #define	 UTMIP_HS_PREAMBLE_OUTPUT_ENABLE	(1 << 6)
171 #define	 UTMIP_SIE_RESUME_ON_LINESTATE		(1 << 5)
172 #define	 UTMIP_SOF_ON_NO_STUFF			(1 << 4)
173 #define	 UTMIP_SOF_ON_NO_ENCODE			(1 << 3)
174 #define	 UTMIP_NO_STUFFING			(1 << 2)
175 #define	 UTMIP_NO_ENCODING			(1 << 1)
176 #define	 UTMIP_NO_SYNC_NO_EOP			(1 << 0)
177 
178 #define	UTMIP_MISC_CFG0			0x824
179 #define	 UTMIP_DPDM_OBSERVE_SEL(x)		(((x) & 0xf) << 27)
180 #define	 UTMIP_DPDM_OBSERVE			(1 << 26)
181 #define	 UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON	(1 << 25)
182 #define	 UTMIP_ALLOW_LS_ON_SOFT_DISCON		(1 << 24)
183 #define	 UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP	(1 << 23)
184 #define	 UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
185 #define	 UTMIP_LS_TO_FS_SKIP_4MS		(1 << 21)
186 #define	 UTMIP_INJECT_ERROR_TYPE(x)		(((x) & 0x3) << 19)
187 #define	 UTMIP_FORCE_HS_CLOCK_ON		(1 << 18)
188 #define	 UTMIP_DISABLE_HS_TERM			(1 << 17)
189 #define	 UTMIP_FORCE_HS_TERM			(1 << 16)
190 #define	 UTMIP_DISABLE_PULLUP_DP		(1 << 15)
191 #define	 UTMIP_DISABLE_PULLUP_DM		(1 << 14)
192 #define	 UTMIP_DISABLE_PULLDN_DP		(1 << 13)
193 #define	 UTMIP_DISABLE_PULLDN_DM		(1 << 12)
194 #define	 UTMIP_FORCE_PULLUP_DP			(1 << 11)
195 #define	 UTMIP_FORCE_PULLUP_DM			(1 << 10)
196 #define	 UTMIP_FORCE_PULLDN_DP			(1 << 9)
197 #define	 UTMIP_FORCE_PULLDN_DM			(1 << 8)
198 #define	 UTMIP_STABLE_COUNT(x)			(((x) & 0x7) << 5)
199 #define	 UTMIP_STABLE_ALL			(1 << 4)
200 #define	 UTMIP_NO_FREE_ON_SUSPEND		(1 << 3)
201 #define	 UTMIP_NEVER_FREE_RUNNING_TERMS		(1 << 2)
202 #define	 UTMIP_ALWAYS_FREE_RUNNING_TERMS	(1 << 1)
203 #define	 UTMIP_COMB_TERMS			(1 << 0)
204 
205 #define	UTMIP_MISC_CFG1			0x828
206 #define	 UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
207 
208 #define	UTMIP_DEBOUNCE_CFG0		0x82C
209 #define	 UTMIP_BIAS_DEBOUNCE_B(x)		(((x) & 0xffff) << 16)
210 #define	 UTMIP_BIAS_DEBOUNCE_A(x)		(((x) & 0xffff) << 0)
211 
212 #define	UTMIP_BAT_CHRG_CFG0		0x830
213 #define	 UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) 	(((x) & 0x1f) << 8)
214 #define	 UTMIP_OP_I_SRC_ENG			(1 << 5)
215 #define	 UTMIP_ON_SRC_ENG			(1 << 4)
216 #define	 UTMIP_OP_SRC_ENG			(1 << 3)
217 #define	 UTMIP_ON_SINK_ENG			(1 << 2)
218 #define	 UTMIP_OP_SINK_ENG			(1 << 1)
219 #define	 UTMIP_PD_CHRG				(1 << 0)
220 
221 #define	UTMIP_SPARE_CFG0		0x834
222 #define	 FUSE_HS_IREF_CAP_CFG			(1 << 7)
223 #define	 FUSE_HS_SQUELCH_LEVEL			(1 << 6)
224 #define	 FUSE_SPARE				(1 << 5)
225 #define	 FUSE_TERM_RANGE_ADJ_SEL		(1 << 4)
226 #define	 FUSE_SETUP_SEL				(1 << 3)
227 #define	 HS_RX_LATE_SQUELCH			(1 << 2)
228 #define	 HS_RX_FLUSH_ALAP  			(1 << 1)
229 #define	 HS_RX_IPG_ERROR_ENABLE 		(1 << 0)
230 
231 #define	UTMIP_XCVR_CFG1			0x838
232 #define	 UTMIP_XCVR_RPU_RANGE_ADJ(x)		(((x) & 0x3) << 26)
233 #define	 UTMIP_XCVR_HS_IREF_CAP(x)		(((x) & 0x3) << 24)
234 #define	 UTMIP_XCVR_SPARE(x)			(((x) & 0x3) << 22)
235 #define	 UTMIP_XCVR_TERM_RANGE_ADJ(x)		(((x) & 0xf) << 18)
236 #define	 UTMIP_RCTRL_SW_SET			(1 << 17)
237 #define	 UTMIP_RCTRL_SW_VAL(x)			(((x) & 0x1f) << 12)
238 #define	 UTMIP_TCTRL_SW_SET			(1 << 11)
239 #define	 UTMIP_TCTRL_SW_VAL(x)			(((x) & 0x1f) << 6)
240 #define	 UTMIP_FORCE_PDDR_POWERUP		(1 << 5)
241 #define	 UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
242 #define	 UTMIP_FORCE_PDCHRP_POWERUP		(1 << 3)
243 #define	 UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
244 #define	 UTMIP_FORCE_PDDISC_POWERUP		(1 << 1)
245 #define	 UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
246 
247 #define	UTMIP_BIAS_CFG1			0x83c
248 #define	 UTMIP_BIAS_DEBOUNCE_TIMESCALE(x)	(((x) & 0x3f) << 8)
249 #define	 UTMIP_BIAS_PDTRK_COUNT(x)		(((x) & 0x1f) << 3)
250 #define	 UTMIP_VBUS_WAKEUP_POWERDOWN		(1 << 2)
251 #define	 UTMIP_FORCE_PDTRK_POWERUP		(1 << 1)
252 #define	 UTMIP_FORCE_PDTRK_POWERDOWN		(1 << 0)
253 
254 static int usbpby_enable_cnt;
255 
256 enum usb_ifc_type {
257 	USB_IFC_TYPE_UNKNOWN = 0,
258 	USB_IFC_TYPE_UTMI,
259 	USB_IFC_TYPE_ULPI
260 };
261 
262 enum usb_dr_mode {
263 	USB_DR_MODE_UNKNOWN = 0,
264 	USB_DR_MODE_DEVICE,
265 	USB_DR_MODE_HOST,
266 	USB_DR_MODE_OTG
267 };
268 
269 struct usbphy_softc {
270 	device_t		dev;
271 	struct resource		*mem_res;
272 	struct resource		*pads_res;
273 	clk_t			clk_reg;
274 	clk_t			clk_pads;
275 	clk_t			clk_pllu;
276 	regulator_t		supply_vbus;
277 	hwreset_t		reset_usb;
278 	hwreset_t		reset_pads;
279 	enum usb_ifc_type	ifc_type;
280 	enum usb_dr_mode	dr_mode;
281 	bool			have_utmi_regs;
282 
283 	/* UTMI params */
284 	int			hssync_start_delay;
285 	int			elastic_limit;
286 	int			idle_wait_delay;
287 	int			term_range_adj;
288 	int			xcvr_lsfslew;
289 	int			xcvr_lsrslew;
290 	int			xcvr_hsslew;
291 	int			hssquelch_level;
292 	int			hsdiscon_level;
293 	int			xcvr_setup;
294 	int			xcvr_setup_use_fuses;
295 };
296 
297 static struct ofw_compat_data compat_data[] = {
298 	{"nvidia,tegra30-usb-phy",	1},
299 	{NULL,				0},
300 };
301 
302 #define	RD4(sc, offs)							\
303 	 bus_read_4(sc->mem_res, offs)
304 
305 #define	WR4(sc, offs, val)						\
306 	 bus_write_4(sc->mem_res, offs, val)
307 
308 static int
309 reg_wait(struct usbphy_softc *sc, uint32_t reg, uint32_t mask, uint32_t val)
310 {
311 	int i;
312 
313 	for (i = 0; i < 1000; i++) {
314 		if ((RD4(sc, reg) & mask) == val)
315 			return (0);
316 		DELAY(10);
317 	}
318 	return (ETIMEDOUT);
319 }
320 
321 static int
322 usbphy_utmi_phy_clk(struct usbphy_softc *sc, bool enable)
323 {
324 	uint32_t val;
325 	int rv;
326 
327 	val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
328 	if (enable)
329 		val &= ~USB_HOSTPC1_DEVLC_PHCD;
330 	else
331 		val |= USB_HOSTPC1_DEVLC_PHCD;
332 	WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
333 
334 	rv = reg_wait(sc, IF_USB_SUSP_CTRL, USB_PHY_CLK_VALID,
335 	    enable ? USB_PHY_CLK_VALID: 0);
336 	if (rv != 0) {
337 		device_printf(sc->dev, "USB phy clock timeout.\n");
338 		return (ETIMEDOUT);
339 	}
340 	return (0);
341 }
342 
343 static int
344 usbphy_utmi_enable(struct usbphy_softc *sc)
345 {
346 	int rv;
347 	uint32_t val;
348 
349 	/* Reset phy */
350 	val = RD4(sc, IF_USB_SUSP_CTRL);
351 	val |= UTMIP_RESET;
352 	WR4(sc, IF_USB_SUSP_CTRL, val);
353 
354 
355 	val = RD4(sc, UTMIP_TX_CFG0);
356 	val |= UTMIP_FS_PREAMBLE_J;
357 	WR4(sc, UTMIP_TX_CFG0, val);
358 
359 	val = RD4(sc, UTMIP_HSRX_CFG0);
360 	val &= ~UTMIP_IDLE_WAIT(~0);
361 	val &= ~UTMIP_ELASTIC_LIMIT(~0);
362 	val |= UTMIP_IDLE_WAIT(sc->idle_wait_delay);
363 	val |= UTMIP_ELASTIC_LIMIT(sc->elastic_limit);
364 	WR4(sc, UTMIP_HSRX_CFG0, val);
365 
366 	val = RD4(sc, UTMIP_HSRX_CFG1);
367 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);
368 	val |= UTMIP_HS_SYNC_START_DLY(sc->hssync_start_delay);
369 	WR4(sc, UTMIP_HSRX_CFG1, val);
370 
371 	val = RD4(sc, UTMIP_DEBOUNCE_CFG0);
372 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
373 	val |= UTMIP_BIAS_DEBOUNCE_A(0x7530);  /* For 12MHz */
374 	WR4(sc, UTMIP_DEBOUNCE_CFG0, val);
375 
376 	val = RD4(sc, UTMIP_MISC_CFG0);
377 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
378 	WR4(sc, UTMIP_MISC_CFG0, val);
379 
380 	if (sc->dr_mode == USB_DR_MODE_DEVICE) {
381 		val = RD4(sc,IF_USB_SUSP_CTRL);
382 		val &= ~USB_WAKE_ON_CNNT_EN_DEV;
383 		val &= ~USB_WAKE_ON_DISCON_EN_DEV;
384 		WR4(sc, IF_USB_SUSP_CTRL, val);
385 
386 		val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
387 		val &= ~UTMIP_PD_CHRG;
388 		WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
389 	} else {
390 		val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
391 		val |= UTMIP_PD_CHRG;
392 		WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
393 	}
394 
395 	usbpby_enable_cnt++;
396 	if (usbpby_enable_cnt == 1) {
397 		rv = hwreset_deassert(sc->reset_pads);
398 		if (rv != 0) {
399 			device_printf(sc->dev,
400 			     "Cannot unreset 'utmi-pads' reset\n");
401 			return (rv);
402 		}
403 		rv = clk_enable(sc->clk_pads);
404 		if (rv != 0) {
405 			device_printf(sc->dev,
406 			    "Cannot enable 'utmi-pads' clock\n");
407 			return (rv);
408 		}
409 
410 		val = bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);
411 		val &= ~UTMIP_OTGPD;
412 		val &= ~UTMIP_BIASPD;
413 		val &= ~UTMIP_HSSQUELCH_LEVEL(~0);
414 		val &= ~UTMIP_HSDISCON_LEVEL(~0);
415 		val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0);
416 		val |= UTMIP_HSSQUELCH_LEVEL(sc->hssquelch_level);
417 		val |= UTMIP_HSDISCON_LEVEL(sc->hsdiscon_level);
418 		val |= UTMIP_HSDISCON_LEVEL_MSB(sc->hsdiscon_level);
419 		bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);
420 
421 		rv = clk_disable(sc->clk_pads);
422 		if (rv != 0) {
423 			device_printf(sc->dev,
424 			    "Cannot disable 'utmi-pads' clock\n");
425 			return (rv);
426 		}
427 	}
428 
429 	val = RD4(sc, UTMIP_XCVR_CFG0);
430 	val &= ~UTMIP_FORCE_PD_POWERDOWN;
431 	val &= ~UTMIP_FORCE_PD2_POWERDOWN ;
432 	val &= ~UTMIP_FORCE_PDZI_POWERDOWN;
433 	val &= ~UTMIP_XCVR_LSBIAS_SEL;
434 	val &= ~UTMIP_XCVR_LSFSLEW(~0);
435 	val &= ~UTMIP_XCVR_LSRSLEW(~0);
436 	val &= ~UTMIP_XCVR_HSSLEW(~0);
437 	val &= ~UTMIP_XCVR_HSSLEW_MSB(~0);
438 	val |= UTMIP_XCVR_LSFSLEW(sc->xcvr_lsfslew);
439 	val |= UTMIP_XCVR_LSRSLEW(sc->xcvr_lsrslew);
440 	val |= UTMIP_XCVR_HSSLEW(sc->xcvr_hsslew);
441 	val |= UTMIP_XCVR_HSSLEW_MSB(sc->xcvr_hsslew);
442 	if (!sc->xcvr_setup_use_fuses) {
443 		val &= ~UTMIP_XCVR_SETUP(~0);
444 		val &= ~UTMIP_XCVR_SETUP_MSB(~0);
445 		val |= UTMIP_XCVR_SETUP(sc->xcvr_setup);
446 		val |= UTMIP_XCVR_SETUP_MSB(sc->xcvr_setup);
447 	}
448 	WR4(sc, UTMIP_XCVR_CFG0, val);
449 
450 	val = RD4(sc, UTMIP_XCVR_CFG1);
451 	val &= ~UTMIP_FORCE_PDDISC_POWERDOWN;
452 	val &= ~UTMIP_FORCE_PDCHRP_POWERDOWN;
453 	val &= ~UTMIP_FORCE_PDDR_POWERDOWN;
454 	val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0);
455 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(sc->term_range_adj);
456 	WR4(sc, UTMIP_XCVR_CFG1, val);
457 
458 
459 	val = RD4(sc, UTMIP_BIAS_CFG1);
460 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
461 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
462 	WR4(sc, UTMIP_BIAS_CFG1, val);
463 
464 	val = RD4(sc, UTMIP_SPARE_CFG0);
465 	if (sc->xcvr_setup_use_fuses)
466 		val |= FUSE_SETUP_SEL;
467 	else
468 		val &= ~FUSE_SETUP_SEL;
469 	WR4(sc, UTMIP_SPARE_CFG0, val);
470 
471 	val = RD4(sc, IF_USB_SUSP_CTRL);
472 	val |= UTMIP_PHY_ENB;
473 	WR4(sc, IF_USB_SUSP_CTRL, val);
474 
475 	val = RD4(sc, IF_USB_SUSP_CTRL);
476 	val &= ~UTMIP_RESET;
477 	WR4(sc, IF_USB_SUSP_CTRL, val);
478 
479 	usbphy_utmi_phy_clk(sc, true);
480 
481 	val = RD4(sc, CTRL_USB_USBMODE);
482 	val &= ~USB_USBMODE_MASK;
483 	if (sc->dr_mode == USB_DR_MODE_HOST)
484 		val |= USB_USBMODE_HOST;
485 	else
486 		val |= USB_USBMODE_DEVICE;
487 	WR4(sc, CTRL_USB_USBMODE, val);
488 
489 	val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC);
490 	val &= ~USB_HOSTPC1_DEVLC_PTS(~0);
491 	val |= USB_HOSTPC1_DEVLC_PTS(0);
492 	WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val);
493 
494 	return (0);
495 }
496 
497 static int
498 usbphy_utmi_disable(struct usbphy_softc *sc)
499 {
500 	int rv;
501 	uint32_t val;
502 
503 	usbphy_utmi_phy_clk(sc, false);
504 
505 	if (sc->dr_mode == USB_DR_MODE_DEVICE) {
506 		val = RD4(sc, IF_USB_SUSP_CTRL);
507 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
508 		val |= USB_WAKE_ON_CNNT_EN_DEV;
509 		val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
510 		WR4(sc, IF_USB_SUSP_CTRL, val);
511 	}
512 
513 	val = RD4(sc, IF_USB_SUSP_CTRL);
514 	val |= UTMIP_RESET;
515 	WR4(sc, IF_USB_SUSP_CTRL, val);
516 
517 	val = RD4(sc, UTMIP_BAT_CHRG_CFG0);
518 	val |= UTMIP_PD_CHRG;
519 	WR4(sc, UTMIP_BAT_CHRG_CFG0, val);
520 
521 	val = RD4(sc, UTMIP_XCVR_CFG0);
522 	val |= UTMIP_FORCE_PD_POWERDOWN;
523 	val |= UTMIP_FORCE_PD2_POWERDOWN;
524 	val |= UTMIP_FORCE_PDZI_POWERDOWN;
525 	WR4(sc, UTMIP_XCVR_CFG0, val);
526 
527 	val = RD4(sc, UTMIP_XCVR_CFG1);
528 	val |= UTMIP_FORCE_PDDISC_POWERDOWN;
529 	val |= UTMIP_FORCE_PDCHRP_POWERDOWN;
530 	val |= UTMIP_FORCE_PDDR_POWERDOWN;
531 	WR4(sc, UTMIP_XCVR_CFG1, val);
532 
533 	usbpby_enable_cnt--;
534 	if (usbpby_enable_cnt <= 0) {
535 		rv = clk_enable(sc->clk_pads);
536 		if (rv != 0) {
537 			device_printf(sc->dev,
538 			    "Cannot enable 'utmi-pads' clock\n");
539 			return (rv);
540 		}
541 		val =bus_read_4(sc->pads_res, UTMIP_BIAS_CFG0);
542 		val |= UTMIP_OTGPD;
543 		val |= UTMIP_BIASPD;
544 		bus_write_4(sc->pads_res, UTMIP_BIAS_CFG0, val);
545 
546 		rv = clk_disable(sc->clk_pads);
547 		if (rv != 0) {
548 			device_printf(sc->dev,
549 			    "Cannot disable 'utmi-pads' clock\n");
550 			return (rv);
551 		}
552 	}
553 	return (0);
554 }
555 
556 static int
557 usbphy_phy_enable(device_t dev, int id, bool enable)
558 {
559 	struct usbphy_softc *sc;
560 	int rv = 0;
561 
562 	sc = device_get_softc(dev);
563 
564 	if (sc->ifc_type != USB_IFC_TYPE_UTMI) {
565 			device_printf(sc->dev,
566 			    "Only UTMI interface is supported.\n");
567 			return (ENXIO);
568 	}
569 	if (enable)
570 		rv = usbphy_utmi_enable(sc);
571 	else
572 		rv = usbphy_utmi_disable(sc);
573 
574 	return (rv);
575 }
576 
577 static enum usb_ifc_type
578 usb_get_ifc_mode(device_t dev, phandle_t node, char *name)
579 {
580 	char *tmpstr;
581 	int rv;
582 	enum usb_ifc_type ret;
583 
584 	rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr);
585 	if (rv <= 0)
586 		return (USB_IFC_TYPE_UNKNOWN);
587 
588 	ret = USB_IFC_TYPE_UNKNOWN;
589 	if (strcmp(tmpstr, "utmi") == 0)
590 		ret = USB_IFC_TYPE_UTMI;
591 	else if (strcmp(tmpstr, "ulpi") == 0)
592 		ret = USB_IFC_TYPE_ULPI;
593 	else
594 		device_printf(dev, "Unsupported phy type: %s\n", tmpstr);
595 	OF_prop_free(tmpstr);
596 	return (ret);
597 }
598 
599 static enum usb_dr_mode
600 usb_get_dr_mode(device_t dev, phandle_t node, char *name)
601 {
602 	char *tmpstr;
603 	int rv;
604 	enum usb_dr_mode ret;
605 
606 	rv = OF_getprop_alloc(node, name, 1, (void **)&tmpstr);
607 	if (rv <= 0)
608 		return (USB_DR_MODE_UNKNOWN);
609 
610 	ret = USB_DR_MODE_UNKNOWN;
611 	if (strcmp(tmpstr, "device") == 0)
612 		ret = USB_DR_MODE_DEVICE;
613 	else if (strcmp(tmpstr, "host") == 0)
614 		ret = USB_DR_MODE_HOST;
615 	else if (strcmp(tmpstr, "otg") == 0)
616 		ret = USB_DR_MODE_OTG;
617 	else
618 		device_printf(dev, "Unknown dr mode: %s\n", tmpstr);
619 	OF_prop_free(tmpstr);
620 	return (ret);
621 }
622 
623 static int
624 usbphy_utmi_read_params(struct usbphy_softc *sc, phandle_t node)
625 {
626 	int rv;
627 
628 	rv = OF_getencprop(node, "nvidia,hssync-start-delay",
629 	    &sc->hssync_start_delay, sizeof (sc->hssync_start_delay));
630 	if (rv <= 0)
631 		return (ENXIO);
632 
633 	rv = OF_getencprop(node, "nvidia,elastic-limit",
634 	    &sc->elastic_limit, sizeof (sc->elastic_limit));
635 	if (rv <= 0)
636 		return (ENXIO);
637 
638 	rv = OF_getencprop(node, "nvidia,idle-wait-delay",
639 	    &sc->idle_wait_delay, sizeof (sc->idle_wait_delay));
640 	if (rv <= 0)
641 		return (ENXIO);
642 
643 	rv = OF_getencprop(node, "nvidia,term-range-adj",
644 	    &sc->term_range_adj, sizeof (sc->term_range_adj));
645 	if (rv <= 0)
646 		return (ENXIO);
647 
648 	rv = OF_getencprop(node, "nvidia,xcvr-lsfslew",
649 	    &sc->xcvr_lsfslew, sizeof (sc->xcvr_lsfslew));
650 	if (rv <= 0)
651 		return (ENXIO);
652 
653 	rv = OF_getencprop(node, "nvidia,xcvr-lsrslew",
654 	    &sc->xcvr_lsrslew, sizeof (sc->xcvr_lsrslew));
655 	if (rv <= 0)
656 		return (ENXIO);
657 
658 	rv = OF_getencprop(node, "nvidia,xcvr-hsslew",
659 	    &sc->xcvr_hsslew, sizeof (sc->xcvr_hsslew));
660 	if (rv <= 0)
661 		return (ENXIO);
662 
663 	rv = OF_getencprop(node, "nvidia,hssquelch-level",
664 	    &sc->hssquelch_level, sizeof (sc->hssquelch_level));
665 	if (rv <= 0)
666 		return (ENXIO);
667 
668 	rv = OF_getencprop(node, "nvidia,hsdiscon-level",
669 	    &sc->hsdiscon_level, sizeof (sc->hsdiscon_level));
670 	if (rv <= 0)
671 		return (ENXIO);
672 
673 	rv = OF_getproplen(node, "nvidia,xcvr-setup-use-fuses");
674 	if (rv >= 1) {
675 		sc->xcvr_setup_use_fuses = 1;
676 	} else {
677 		rv = OF_getencprop(node, "nvidia,xcvr-setup",
678 		    &sc->xcvr_setup, sizeof (sc->xcvr_setup));
679 		if (rv <= 0)
680 			return (ENXIO);
681 	}
682 
683 	return (0);
684 }
685 
686 static int
687 usbphy_probe(device_t dev)
688 {
689 
690 	if (!ofw_bus_status_okay(dev))
691 		return (ENXIO);
692 
693 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
694 		return (ENXIO);
695 
696 	device_set_desc(dev, "Tegra USB phy");
697 	return (BUS_PROBE_DEFAULT);
698 }
699 
700 static int
701 usbphy_attach(device_t dev)
702 {
703 	struct usbphy_softc * sc;
704 	int rid, rv;
705 	phandle_t node;
706 
707 	sc = device_get_softc(dev);
708 	sc->dev = dev;
709 
710 	rid = 0;
711 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
712 	    RF_ACTIVE | RF_SHAREABLE);
713 	if (sc->mem_res == NULL) {
714 		device_printf(dev, "Cannot allocate memory resources\n");
715 		return (ENXIO);
716 	}
717 
718 	rid = 1;
719 	sc->pads_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
720 	    RF_ACTIVE | RF_SHAREABLE);
721 	if (sc->mem_res == NULL) {
722 		device_printf(dev, "Cannot allocate memory resources\n");
723 		return (ENXIO);
724 	}
725 
726 	node = ofw_bus_get_node(dev);
727 
728 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb);
729 	if (rv != 0) {
730 		device_printf(dev, "Cannot get 'usb' reset\n");
731 		return (ENXIO);
732 	}
733 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads);
734 	if (rv != 0) {
735 		device_printf(dev, "Cannot get 'utmi-pads' reset\n");
736 		return (ENXIO);
737 	}
738 
739 	rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
740 	if (rv != 0) {
741 		device_printf(sc->dev, "Cannot get 'reg' clock\n");
742 		return (ENXIO);
743 	}
744 	rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu);
745 	if (rv != 0) {
746 		device_printf(sc->dev, "Cannot get 'pll_u' clock\n");
747 		return (ENXIO);
748 	}
749 	rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads);
750 	if (rv != 0) {
751 		device_printf(sc->dev, "Cannot get 'utmi-pads' clock\n");
752 		return (ENXIO);
753 	}
754 
755 	rv = hwreset_deassert(sc->reset_usb);
756 	if (rv != 0) {
757 		device_printf(dev, "Cannot unreset 'usb' reset\n");
758 		return (ENXIO);
759 	}
760 
761 	rv = clk_enable(sc->clk_pllu);
762 	if (rv != 0) {
763 		device_printf(sc->dev, "Cannot enable 'pllu' clock\n");
764 		return (ENXIO);
765 	}
766 	rv = clk_enable(sc->clk_reg);
767 	if (rv != 0) {
768 		device_printf(sc->dev, "Cannot enable 'reg' clock\n");
769 		return (ENXIO);
770 	}
771 	if (OF_hasprop(node, "nvidia,has-utmi-pad-registers"))
772 		sc->have_utmi_regs = true;
773 
774 	sc->dr_mode = usb_get_dr_mode(dev, node, "dr_mode");
775 	if (sc->dr_mode == USB_DR_MODE_UNKNOWN)
776 		sc->dr_mode = USB_DR_MODE_HOST;
777 
778 	sc->ifc_type = usb_get_ifc_mode(dev, node, "phy_type");
779 
780 	/* We supports only utmi phy mode for now .... */
781 	if (sc->ifc_type != USB_IFC_TYPE_UTMI) {
782 		device_printf(dev, "Unsupported phy type\n");
783 		return (ENXIO);
784 	}
785 	rv = usbphy_utmi_read_params(sc, node);
786 	if (rv < 0)
787 		return rv;
788 
789 	if (OF_hasprop(node, "vbus-supply")) {
790 		rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply",
791 		    &sc->supply_vbus);
792 		if (rv != 0) {
793 			device_printf(sc->dev,
794 			   "Cannot get \"vbus\" regulator\n");
795 			return (ENXIO);
796 		}
797 		rv = regulator_enable(sc->supply_vbus);
798 		if (rv != 0) {
799 			device_printf(sc->dev,
800 			    "Cannot enable  \"vbus\" regulator\n");
801 			return (rv);
802 		}
803 	}
804 
805 	phy_register_provider(dev);
806 	return (0);
807 }
808 
809 static int
810 usbphy_detach(device_t dev)
811 {
812 
813 	/* This device is always present. */
814 	return (EBUSY);
815 }
816 
817 static device_method_t tegra_usbphy_methods[] = {
818 	/* Device interface */
819 	DEVMETHOD(device_probe,		usbphy_probe),
820 	DEVMETHOD(device_attach,	usbphy_attach),
821 	DEVMETHOD(device_detach,	usbphy_detach),
822 
823 	/* phy interface */
824 	DEVMETHOD(phy_enable,		usbphy_phy_enable),
825 
826 	DEVMETHOD_END
827 };
828 
829 static devclass_t tegra_usbphy_devclass;
830 static DEFINE_CLASS_0(usbphy, tegra_usbphy_driver, tegra_usbphy_methods,
831     sizeof(struct usbphy_softc));
832 EARLY_DRIVER_MODULE(tegra_usbphy, simplebus, tegra_usbphy_driver,
833     tegra_usbphy_devclass, NULL, NULL, 79);
834