1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for NVIDIA Tegra family 32 * 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/gpio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/resource.h> 46 #include <sys/rman.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 #include <sys/time.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/intr.h> 54 55 #include <dev/extres/clk/clk.h> 56 #include <dev/extres/hwreset/hwreset.h> 57 #include <dev/gpio/gpiobusvar.h> 58 #include <dev/mmc/bridge.h> 59 #include <dev/mmc/mmcreg.h> 60 #include <dev/mmc/mmcbrvar.h> 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/sdhci/sdhci.h> 64 #include <dev/sdhci/sdhci_fdt_gpio.h> 65 66 #include "sdhci_if.h" 67 68 /* Tegra SDHOST controller vendor register definitions */ 69 #define SDMMC_VENDOR_CLOCK_CNTRL 0x100 70 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8 71 #define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF 72 #define SDMMC_VENDOR_SYS_SW_CNTRL 0x104 73 #define SDMMC_VENDOR_CAP_OVERRIDES 0x10C 74 #define SDMMC_VENDOR_BOOT_CNTRL 0x110 75 #define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114 76 #define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118 77 #define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C 78 #define SDMMC_VENDOR_MISC_CNTRL 0x120 79 #define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8 80 #define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10 81 #define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 82 #define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200 83 #define SDMMC_MAX_CURRENT_OVERRIDE 0x124 84 #define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128 85 #define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0 86 #define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4 87 #define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8 88 #define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC 89 #define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0 90 #define SDMMC_AUTO_CAL_CONFIG 0x1E4 91 #define SDMMC_AUTO_CAL_INTERVAL 0x1E8 92 #define SDMMC_AUTO_CAL_STATUS 0x1EC 93 #define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4 94 #define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8 95 96 /* Compatible devices. */ 97 static struct ofw_compat_data compat_data[] = { 98 {"nvidia,tegra124-sdhci", 1}, 99 {NULL, 0}, 100 }; 101 102 struct tegra_sdhci_softc { 103 device_t dev; 104 struct resource * mem_res; 105 struct resource * irq_res; 106 void * intr_cookie; 107 u_int quirks; /* Chip specific quirks */ 108 u_int caps; /* If we override SDHCI_CAPABILITIES */ 109 uint32_t max_clk; /* Max possible freq */ 110 clk_t clk; 111 hwreset_t reset; 112 gpio_pin_t gpio_power; 113 struct sdhci_fdt_gpio *gpio; 114 115 int force_card_present; 116 struct sdhci_slot slot; 117 118 }; 119 120 static inline uint32_t 121 RD4(struct tegra_sdhci_softc *sc, bus_size_t off) 122 { 123 124 return (bus_read_4(sc->mem_res, off)); 125 } 126 127 static uint8_t 128 tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 129 { 130 struct tegra_sdhci_softc *sc; 131 132 sc = device_get_softc(dev); 133 return (bus_read_1(sc->mem_res, off)); 134 } 135 136 static uint16_t 137 tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 138 { 139 struct tegra_sdhci_softc *sc; 140 141 sc = device_get_softc(dev); 142 return (bus_read_2(sc->mem_res, off)); 143 } 144 145 static uint32_t 146 tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 147 { 148 struct tegra_sdhci_softc *sc; 149 uint32_t val32; 150 151 sc = device_get_softc(dev); 152 val32 = bus_read_4(sc->mem_res, off); 153 /* Force the card-present state if necessary. */ 154 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 155 val32 |= SDHCI_CARD_PRESENT; 156 return (val32); 157 } 158 159 static void 160 tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 161 uint32_t *data, bus_size_t count) 162 { 163 struct tegra_sdhci_softc *sc; 164 165 sc = device_get_softc(dev); 166 bus_read_multi_4(sc->mem_res, off, data, count); 167 } 168 169 static void 170 tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 171 uint8_t val) 172 { 173 struct tegra_sdhci_softc *sc; 174 175 sc = device_get_softc(dev); 176 bus_write_1(sc->mem_res, off, val); 177 } 178 179 static void 180 tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 181 uint16_t val) 182 { 183 struct tegra_sdhci_softc *sc; 184 185 sc = device_get_softc(dev); 186 bus_write_2(sc->mem_res, off, val); 187 } 188 189 static void 190 tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 191 uint32_t val) 192 { 193 struct tegra_sdhci_softc *sc; 194 195 sc = device_get_softc(dev); 196 bus_write_4(sc->mem_res, off, val); 197 } 198 199 static void 200 tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 201 uint32_t *data, bus_size_t count) 202 { 203 struct tegra_sdhci_softc *sc; 204 205 sc = device_get_softc(dev); 206 bus_write_multi_4(sc->mem_res, off, data, count); 207 } 208 209 static void 210 tegra_sdhci_intr(void *arg) 211 { 212 struct tegra_sdhci_softc *sc = arg; 213 214 sdhci_generic_intr(&sc->slot); 215 RD4(sc, SDHCI_INT_STATUS); 216 } 217 218 static int 219 tegra_sdhci_get_ro(device_t brdev, device_t reqdev) 220 { 221 struct tegra_sdhci_softc *sc = device_get_softc(brdev); 222 223 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 224 } 225 226 static bool 227 tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 228 { 229 struct tegra_sdhci_softc *sc = device_get_softc(dev); 230 231 return (sdhci_fdt_gpio_get_present(sc->gpio)); 232 } 233 234 static int 235 tegra_sdhci_probe(device_t dev) 236 { 237 struct tegra_sdhci_softc *sc; 238 phandle_t node; 239 pcell_t cid; 240 const struct ofw_compat_data *cd; 241 242 sc = device_get_softc(dev); 243 if (!ofw_bus_status_okay(dev)) 244 return (ENXIO); 245 246 if (ofw_bus_is_compatible(dev, "nvidia,tegra124-sdhci")) { 247 device_set_desc(dev, "Tegra SDHCI controller"); 248 } else 249 return (ENXIO); 250 cd = ofw_bus_search_compatible(dev, compat_data); 251 if (cd->ocd_data == 0) 252 return (ENXIO); 253 254 node = ofw_bus_get_node(dev); 255 256 /* Allow dts to patch quirks, slots, and max-frequency. */ 257 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 258 sc->quirks = cid; 259 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 260 sc->max_clk = cid; 261 262 return (BUS_PROBE_DEFAULT); 263 } 264 265 static int 266 tegra_sdhci_attach(device_t dev) 267 { 268 struct tegra_sdhci_softc *sc; 269 int rid, rv; 270 uint64_t freq; 271 phandle_t node, prop; 272 273 sc = device_get_softc(dev); 274 sc->dev = dev; 275 node = ofw_bus_get_node(dev); 276 277 rid = 0; 278 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 279 RF_ACTIVE); 280 if (!sc->mem_res) { 281 device_printf(dev, "cannot allocate memory window\n"); 282 rv = ENXIO; 283 goto fail; 284 } 285 286 rid = 0; 287 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 288 RF_ACTIVE); 289 if (!sc->irq_res) { 290 device_printf(dev, "cannot allocate interrupt\n"); 291 rv = ENXIO; 292 goto fail; 293 } 294 295 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 296 NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) { 297 device_printf(dev, "cannot setup interrupt handler\n"); 298 rv = ENXIO; 299 goto fail; 300 } 301 302 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset); 303 if (rv != 0) { 304 device_printf(sc->dev, "Cannot get 'sdhci' reset\n"); 305 goto fail; 306 } 307 rv = hwreset_deassert(sc->reset); 308 if (rv != 0) { 309 device_printf(dev, "Cannot unreset 'sdhci' reset\n"); 310 goto fail; 311 } 312 313 gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power); 314 315 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 316 if (rv != 0) { 317 318 device_printf(dev, "Cannot get clock\n"); 319 goto fail; 320 } 321 322 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 323 if (rv != 0) { 324 device_printf(dev, "Cannot get clock\n"); 325 goto fail; 326 } 327 rv = clk_enable(sc->clk); 328 if (rv != 0) { 329 device_printf(dev, "Cannot enable clock\n"); 330 goto fail; 331 } 332 rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN); 333 if (rv != 0) { 334 device_printf(dev, "Cannot set clock\n"); 335 } 336 rv = clk_get_freq(sc->clk, &freq); 337 if (rv != 0) { 338 device_printf(dev, "Cannot get clock frequency\n"); 339 goto fail; 340 } 341 if (bootverbose) 342 device_printf(dev, " Base MMC clock: %lld\n", freq); 343 344 /* Fill slot information. */ 345 sc->max_clk = (int)freq; 346 sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 347 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 348 SDHCI_QUIRK_MISSING_CAPS; 349 350 /* Limit real slot capabilities. */ 351 sc->caps = RD4(sc, SDHCI_CAPABILITIES); 352 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 353 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 354 switch (prop) { 355 case 8: 356 sc->caps |= MMC_CAP_8_BIT_DATA; 357 /* FALLTHROUGH */ 358 case 4: 359 sc->caps |= MMC_CAP_4_BIT_DATA; 360 break; 361 case 1: 362 break; 363 default: 364 device_printf(dev, "Bad bus-width value %u\n", prop); 365 break; 366 } 367 } 368 if (OF_hasprop(node, "non-removable")) 369 sc->force_card_present = 1; 370 /* 371 * Clear clock field, so SDHCI driver uses supplied frequency. 372 * in sc->slot.max_clk 373 */ 374 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 375 376 sc->slot.quirks = sc->quirks; 377 sc->slot.max_clk = sc->max_clk; 378 sc->slot.caps = sc->caps; 379 380 rv = sdhci_init_slot(dev, &sc->slot, 0); 381 if (rv != 0) { 382 goto fail; 383 } 384 385 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); 386 387 bus_generic_probe(dev); 388 bus_generic_attach(dev); 389 390 sdhci_start_slot(&sc->slot); 391 392 return (0); 393 394 fail: 395 if (sc->gpio != NULL) 396 sdhci_fdt_gpio_teardown(sc->gpio); 397 if (sc->intr_cookie != NULL) 398 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 399 if (sc->gpio_power != NULL) 400 gpio_pin_release(sc->gpio_power); 401 if (sc->clk != NULL) 402 clk_release(sc->clk); 403 if (sc->reset != NULL) 404 hwreset_release(sc->reset); 405 if (sc->irq_res != NULL) 406 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 407 if (sc->mem_res != NULL) 408 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 409 410 return (rv); 411 } 412 413 static int 414 tegra_sdhci_detach(device_t dev) 415 { 416 struct tegra_sdhci_softc *sc = device_get_softc(dev); 417 struct sdhci_slot *slot = &sc->slot; 418 419 bus_generic_detach(dev); 420 sdhci_fdt_gpio_teardown(sc->gpio); 421 clk_release(sc->clk); 422 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 423 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 424 sc->irq_res); 425 426 sdhci_cleanup_slot(slot); 427 bus_release_resource(dev, SYS_RES_MEMORY, 428 rman_get_rid(sc->mem_res), 429 sc->mem_res); 430 return (0); 431 } 432 433 static device_method_t tegra_sdhci_methods[] = { 434 /* Device interface */ 435 DEVMETHOD(device_probe, tegra_sdhci_probe), 436 DEVMETHOD(device_attach, tegra_sdhci_attach), 437 DEVMETHOD(device_detach, tegra_sdhci_detach), 438 439 /* Bus interface */ 440 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 441 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 442 443 /* MMC bridge interface */ 444 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 445 DEVMETHOD(mmcbr_request, sdhci_generic_request), 446 DEVMETHOD(mmcbr_get_ro, tegra_sdhci_get_ro), 447 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 448 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 449 450 /* SDHCI registers accessors */ 451 DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1), 452 DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2), 453 DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4), 454 DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4), 455 DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1), 456 DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2), 457 DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4), 458 DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4), 459 DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present), 460 461 DEVMETHOD_END 462 }; 463 464 static devclass_t tegra_sdhci_devclass; 465 static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods, 466 sizeof(struct tegra_sdhci_softc)); 467 DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass, 468 NULL, NULL); 469 MODULE_DEPEND(sdhci_tegra, sdhci, 1, 1, 1); 470 DRIVER_MODULE(mmc, sdhci, mmc_driver, mmc_devclass, NULL, NULL); 471 MODULE_DEPEND(sdhci_tegra, mmc, 1, 1, 1); 472