1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SDHCI driver glue for NVIDIA Tegra family 32 * 33 */ 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/callout.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/resource.h> 45 #include <sys/rman.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/intr.h> 53 54 #include <dev/extres/clk/clk.h> 55 #include <dev/extres/hwreset/hwreset.h> 56 #include <dev/gpio/gpiobusvar.h> 57 #include <dev/mmc/bridge.h> 58 #include <dev/mmc/mmcreg.h> 59 #include <dev/mmc/mmcbrvar.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 #include <dev/sdhci/sdhci.h> 63 64 #include "sdhci_if.h" 65 66 /* Tegra SDHOST controller vendor register definitions */ 67 #define SDMMC_VENDOR_CLOCK_CNTRL 0x100 68 #define VENDOR_CLOCK_CNTRL_CLK_SHIFT 8 69 #define VENDOR_CLOCK_CNTRL_CLK_MASK 0xFF 70 #define SDMMC_VENDOR_SYS_SW_CNTRL 0x104 71 #define SDMMC_VENDOR_CAP_OVERRIDES 0x10C 72 #define SDMMC_VENDOR_BOOT_CNTRL 0x110 73 #define SDMMC_VENDOR_BOOT_ACK_TIMEOUT 0x114 74 #define SDMMC_VENDOR_BOOT_DAT_TIMEOUT 0x118 75 #define SDMMC_VENDOR_DEBOUNCE_COUNT 0x11C 76 #define SDMMC_VENDOR_MISC_CNTRL 0x120 77 #define VENDOR_MISC_CTRL_ENABLE_SDR104 0x8 78 #define VENDOR_MISC_CTRL_ENABLE_SDR50 0x10 79 #define VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 80 #define VENDOR_MISC_CTRL_ENABLE_DDR50 0x200 81 #define SDMMC_MAX_CURRENT_OVERRIDE 0x124 82 #define SDMMC_MAX_CURRENT_OVERRIDE_HI 0x128 83 #define SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 0x1D0 84 #define SDMMC_VENDOR_PHWRESET_VAL0 0x1D4 85 #define SDMMC_VENDOR_PHWRESET_VAL1 0x1D8 86 #define SDMMC_VENDOR_PHWRESET_VAL2 0x1DC 87 #define SDMMC_SDMEMCOMPPADCTRL_0 0x1E0 88 #define SDMMC_AUTO_CAL_CONFIG 0x1E4 89 #define SDMMC_AUTO_CAL_INTERVAL 0x1E8 90 #define SDMMC_AUTO_CAL_STATUS 0x1EC 91 #define SDMMC_SDMMC_MCCIF_FIFOCTRL 0x1F4 92 #define SDMMC_TIMEOUT_WCOAL_SDMMC 0x1F8 93 94 /* Compatible devices. */ 95 static struct ofw_compat_data compat_data[] = { 96 {"nvidia,tegra124-sdhci", 1}, 97 {NULL, 0}, 98 }; 99 100 struct tegra_sdhci_softc { 101 device_t dev; 102 struct resource * mem_res; 103 struct resource * irq_res; 104 void * intr_cookie; 105 u_int quirks; /* Chip specific quirks */ 106 u_int caps; /* If we override SDHCI_CAPABILITIES */ 107 uint32_t max_clk; /* Max possible freq */ 108 clk_t clk; 109 hwreset_t reset; 110 gpio_pin_t gpio_cd; 111 gpio_pin_t gpio_wp; 112 gpio_pin_t gpio_power; 113 114 int force_card_present; 115 struct sdhci_slot slot; 116 117 }; 118 119 static inline uint32_t 120 RD4(struct tegra_sdhci_softc *sc, bus_size_t off) 121 { 122 123 return (bus_read_4(sc->mem_res, off)); 124 } 125 126 static uint8_t 127 tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 128 { 129 struct tegra_sdhci_softc *sc; 130 131 sc = device_get_softc(dev); 132 return (bus_read_1(sc->mem_res, off)); 133 } 134 135 static uint16_t 136 tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 137 { 138 struct tegra_sdhci_softc *sc; 139 140 sc = device_get_softc(dev); 141 return (bus_read_2(sc->mem_res, off)); 142 } 143 144 static uint32_t 145 tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 146 { 147 struct tegra_sdhci_softc *sc; 148 uint32_t val32; 149 150 sc = device_get_softc(dev); 151 val32 = bus_read_4(sc->mem_res, off); 152 /* Force the card-present state if necessary. */ 153 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 154 val32 |= SDHCI_CARD_PRESENT; 155 return (val32); 156 } 157 158 static void 159 tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 160 uint32_t *data, bus_size_t count) 161 { 162 struct tegra_sdhci_softc *sc; 163 164 sc = device_get_softc(dev); 165 bus_read_multi_4(sc->mem_res, off, data, count); 166 } 167 168 static void 169 tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 170 uint8_t val) 171 { 172 struct tegra_sdhci_softc *sc; 173 174 sc = device_get_softc(dev); 175 bus_write_1(sc->mem_res, off, val); 176 } 177 178 static void 179 tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 180 uint16_t val) 181 { 182 struct tegra_sdhci_softc *sc; 183 184 sc = device_get_softc(dev); 185 bus_write_2(sc->mem_res, off, val); 186 } 187 188 static void 189 tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 190 uint32_t val) 191 { 192 struct tegra_sdhci_softc *sc; 193 194 sc = device_get_softc(dev); 195 bus_write_4(sc->mem_res, off, val); 196 } 197 198 static void 199 tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 200 uint32_t *data, bus_size_t count) 201 { 202 struct tegra_sdhci_softc *sc; 203 204 sc = device_get_softc(dev); 205 bus_write_multi_4(sc->mem_res, off, data, count); 206 } 207 208 static void 209 tegra_sdhci_intr(void *arg) 210 { 211 struct tegra_sdhci_softc *sc = arg; 212 213 sdhci_generic_intr(&sc->slot); 214 RD4(sc, SDHCI_INT_STATUS); 215 } 216 217 static int 218 tegra_generic_get_ro(device_t brdev, device_t reqdev) 219 { 220 221 return (0); 222 } 223 224 static int 225 tegra_sdhci_probe(device_t dev) 226 { 227 struct tegra_sdhci_softc *sc; 228 phandle_t node; 229 pcell_t cid; 230 const struct ofw_compat_data *cd; 231 232 sc = device_get_softc(dev); 233 if (!ofw_bus_status_okay(dev)) 234 return (ENXIO); 235 236 if (ofw_bus_is_compatible(dev, "nvidia,tegra124-sdhci")) { 237 device_set_desc(dev, "Tegra SDHCI controller"); 238 } else 239 return (ENXIO); 240 cd = ofw_bus_search_compatible(dev, compat_data); 241 if (cd->ocd_data == 0) 242 return (ENXIO); 243 244 node = ofw_bus_get_node(dev); 245 246 /* Allow dts to patch quirks, slots, and max-frequency. */ 247 if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) 248 sc->quirks = cid; 249 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) 250 sc->max_clk = cid; 251 252 return (BUS_PROBE_DEFAULT); 253 } 254 255 static int 256 tegra_sdhci_attach(device_t dev) 257 { 258 struct tegra_sdhci_softc *sc; 259 int rid, rv; 260 uint64_t freq; 261 phandle_t node, prop; 262 263 sc = device_get_softc(dev); 264 sc->dev = dev; 265 node = ofw_bus_get_node(dev); 266 267 rid = 0; 268 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 269 RF_ACTIVE); 270 if (!sc->mem_res) { 271 device_printf(dev, "cannot allocate memory window\n"); 272 rv = ENXIO; 273 goto fail; 274 } 275 276 rid = 0; 277 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 278 RF_ACTIVE); 279 if (!sc->irq_res) { 280 device_printf(dev, "cannot allocate interrupt\n"); 281 rv = ENXIO; 282 goto fail; 283 } 284 285 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 286 NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) { 287 device_printf(dev, "cannot setup interrupt handler\n"); 288 rv = ENXIO; 289 goto fail; 290 } 291 292 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset); 293 if (rv != 0) { 294 device_printf(sc->dev, "Cannot get 'sdhci' reset\n"); 295 goto fail; 296 } 297 rv = hwreset_deassert(sc->reset); 298 if (rv != 0) { 299 device_printf(dev, "Cannot unreset 'sdhci' reset\n"); 300 goto fail; 301 } 302 303 gpio_pin_get_by_ofw_property(sc->dev, node, "cd-gpios", &sc->gpio_cd); 304 gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power); 305 gpio_pin_get_by_ofw_property(sc->dev, node, "wp-gpios", &sc->gpio_wp); 306 307 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 308 if (rv != 0) { 309 310 device_printf(dev, "Cannot get clock\n"); 311 goto fail; 312 } 313 314 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 315 if (rv != 0) { 316 device_printf(dev, "Cannot get clock\n"); 317 goto fail; 318 } 319 rv = clk_enable(sc->clk); 320 if (rv != 0) { 321 device_printf(dev, "Cannot enable clock\n"); 322 goto fail; 323 } 324 rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN); 325 if (rv != 0) { 326 device_printf(dev, "Cannot set clock\n"); 327 } 328 rv = clk_get_freq(sc->clk, &freq); 329 if (rv != 0) { 330 device_printf(dev, "Cannot get clock frequency\n"); 331 goto fail; 332 } 333 if (bootverbose) 334 device_printf(dev, " Base MMC clock: %lld\n", freq); 335 336 /* Fill slot information. */ 337 sc->max_clk = (int)freq; 338 sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | 339 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 340 SDHCI_QUIRK_MISSING_CAPS; 341 342 /* Limit real slot capabilities. */ 343 sc->caps = RD4(sc, SDHCI_CAPABILITIES); 344 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 345 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 346 switch (prop) { 347 case 8: 348 sc->caps |= MMC_CAP_8_BIT_DATA; 349 /* FALLTHROUGH */ 350 case 4: 351 sc->caps |= MMC_CAP_4_BIT_DATA; 352 break; 353 case 1: 354 break; 355 default: 356 device_printf(dev, "Bad bus-width value %u\n", prop); 357 break; 358 } 359 } 360 if (OF_hasprop(node, "non-removable")) 361 sc->force_card_present = 1; 362 /* 363 * Clear clock field, so SDHCI driver uses supplied frequency. 364 * in sc->slot.max_clk 365 */ 366 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 367 368 sc->slot.quirks = sc->quirks; 369 sc->slot.max_clk = sc->max_clk; 370 sc->slot.caps = sc->caps; 371 372 rv = sdhci_init_slot(dev, &sc->slot, 0); 373 if (rv != 0) { 374 goto fail; 375 } 376 377 bus_generic_probe(dev); 378 bus_generic_attach(dev); 379 380 sdhci_start_slot(&sc->slot); 381 382 return (0); 383 384 fail: 385 if (sc->gpio_cd != NULL) 386 gpio_pin_release(sc->gpio_cd); 387 if (sc->gpio_wp != NULL) 388 gpio_pin_release(sc->gpio_wp); 389 if (sc->gpio_power != NULL) 390 gpio_pin_release(sc->gpio_power); 391 if (sc->clk != NULL) 392 clk_release(sc->clk); 393 if (sc->reset != NULL) 394 hwreset_release(sc->reset); 395 if (sc->intr_cookie != NULL) 396 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 397 if (sc->irq_res != NULL) 398 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 399 if (sc->mem_res != NULL) 400 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 401 402 return (rv); 403 } 404 405 static int 406 tegra_sdhci_detach(device_t dev) 407 { 408 struct tegra_sdhci_softc *sc = device_get_softc(dev); 409 struct sdhci_slot *slot = &sc->slot; 410 411 bus_generic_detach(dev); 412 clk_release(sc->clk); 413 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 414 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), 415 sc->irq_res); 416 417 sdhci_cleanup_slot(slot); 418 bus_release_resource(dev, SYS_RES_MEMORY, 419 rman_get_rid(sc->mem_res), 420 sc->mem_res); 421 return (0); 422 } 423 424 static device_method_t tegra_sdhci_methods[] = { 425 /* Device interface */ 426 DEVMETHOD(device_probe, tegra_sdhci_probe), 427 DEVMETHOD(device_attach, tegra_sdhci_attach), 428 DEVMETHOD(device_detach, tegra_sdhci_detach), 429 430 /* Bus interface */ 431 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 432 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 433 434 /* MMC bridge interface */ 435 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 436 DEVMETHOD(mmcbr_request, sdhci_generic_request), 437 DEVMETHOD(mmcbr_get_ro, tegra_generic_get_ro), 438 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 439 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 440 441 /* SDHCI registers accessors */ 442 DEVMETHOD(sdhci_read_1, tegra_sdhci_read_1), 443 DEVMETHOD(sdhci_read_2, tegra_sdhci_read_2), 444 DEVMETHOD(sdhci_read_4, tegra_sdhci_read_4), 445 DEVMETHOD(sdhci_read_multi_4, tegra_sdhci_read_multi_4), 446 DEVMETHOD(sdhci_write_1, tegra_sdhci_write_1), 447 DEVMETHOD(sdhci_write_2, tegra_sdhci_write_2), 448 DEVMETHOD(sdhci_write_4, tegra_sdhci_write_4), 449 DEVMETHOD(sdhci_write_multi_4, tegra_sdhci_write_multi_4), 450 451 DEVMETHOD_END 452 }; 453 454 static devclass_t tegra_sdhci_devclass; 455 static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods, 456 sizeof(struct tegra_sdhci_softc)); 457 DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass, 458 NULL, NULL); 459 MODULE_DEPEND(sdhci_tegra, sdhci, 1, 1, 1); 460 DRIVER_MODULE(mmc, sdhci, mmc_driver, mmc_devclass, NULL, NULL); 461 MODULE_DEPEND(sdhci_tegra, mmc, 1, 1, 1); 462