1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/bus.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 46 #include <machine/intr.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 51 #include <dev/extres/clk/clk.h> 52 #include <dev/extres/hwreset/hwreset.h> 53 #include <dev/extres/phy/phy.h> 54 #include <dev/extres/regulator/regulator.h> 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcib_private.h> 62 63 #include <machine/devmap.h> 64 #include <machine/resource.h> 65 #include <machine/bus.h> 66 67 #include "ofw_bus_if.h" 68 #include "pcib_if.h" 69 70 #include <arm/nvidia/tegra_pmc.h> 71 72 /* --- Move to ofw_pci.c/.h ----------------------- */ 73 74 struct tegra_pci_range { 75 /* parsed phys.hi */ 76 int nonrelocatable; 77 int prefetchable; 78 int aliased; 79 int space_code; /* In native format (not shifted)*/ 80 int bus; 81 int device; 82 int function; 83 int reg; 84 pci_addr_t pci_addr; /* PCI Address */ 85 bus_addr_t host_addr; /* Host bus address*/ 86 bus_size_t size; /* Range size */ 87 }; 88 89 static int 90 tegra_pci_get_ranges(phandle_t node, struct tegra_pci_range **ranges) 91 { 92 int host_address_cells, pci_address_cells, size_cells; 93 cell_t *base_ranges; 94 ssize_t nbase_ranges; 95 int nranges; 96 int i, j, k; 97 uint32_t flags; 98 uint64_t tmp; 99 100 host_address_cells = 1; 101 pci_address_cells = 3; 102 size_cells = 2; 103 OF_getencprop(OF_parent(node), "#address-cells", &host_address_cells, 104 sizeof(host_address_cells)); 105 OF_getencprop(node, "#address-cells", &pci_address_cells, 106 sizeof(pci_address_cells)); 107 OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); 108 109 nbase_ranges = OF_getproplen(node, "ranges"); 110 if (nbase_ranges <= 0) 111 return (-1); 112 nranges = nbase_ranges / sizeof(cell_t) / 113 (pci_address_cells + host_address_cells + size_cells); 114 115 *ranges = malloc(nranges * sizeof(struct tegra_pci_range), 116 M_DEVBUF, M_WAITOK); 117 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 118 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 119 120 for (i = 0, j = 0; i < nranges; i++) { 121 flags = base_ranges[j++]; 122 (*ranges)[i].nonrelocatable = 123 flags & OFW_PCI_PHYS_HI_NONRELOCATABLE ? 1 : 0; 124 (*ranges)[i].prefetchable = 125 flags & OFW_PCI_PHYS_HI_PREFETCHABLE ? 1 : 0; 126 (*ranges)[i].aliased = 127 flags & OFW_PCI_PHYS_HI_ALIASED ? 1 : 0; 128 (*ranges)[i].space_code = flags & OFW_PCI_PHYS_HI_SPACEMASK; 129 (*ranges)[i].bus = OFW_PCI_PHYS_HI_BUS(flags); 130 (*ranges)[i].device = OFW_PCI_PHYS_HI_DEVICE(flags); 131 (*ranges)[i].function = OFW_PCI_PHYS_HI_FUNCTION(flags); 132 (*ranges)[i].reg = flags & OFW_PCI_PHYS_HI_REGISTERMASK; 133 134 tmp = 0; 135 for (k = 0; k < pci_address_cells - 1; k++) { 136 tmp <<= 32; 137 tmp |= base_ranges[j++]; 138 } 139 (*ranges)[i].pci_addr = (pci_addr_t)tmp; 140 141 tmp = 0; 142 for (k = 0; k < host_address_cells; k++) { 143 tmp <<= 32; 144 tmp |= base_ranges[j++]; 145 } 146 (*ranges)[i].host_addr = (bus_addr_t)tmp; 147 tmp = 0; 148 149 for (k = 0; k < size_cells; k++) { 150 tmp <<= 32; 151 tmp |= base_ranges[j++]; 152 } 153 (*ranges)[i].size = (bus_size_t)tmp; 154 } 155 156 free(base_ranges, M_DEVBUF); 157 return (nranges); 158 } 159 160 /* -------------------------------------------------------------------------- */ 161 #define AFI_AXI_BAR0_SZ 0x000 162 #define AFI_AXI_BAR1_SZ 0x004 163 #define AFI_AXI_BAR2_SZ 0x008 164 #define AFI_AXI_BAR3_SZ 0x00c 165 #define AFI_AXI_BAR4_SZ 0x010 166 #define AFI_AXI_BAR5_SZ 0x014 167 #define AFI_AXI_BAR0_START 0x018 168 #define AFI_AXI_BAR1_START 0x01c 169 #define AFI_AXI_BAR2_START 0x020 170 #define AFI_AXI_BAR3_START 0x024 171 #define AFI_AXI_BAR4_START 0x028 172 #define AFI_AXI_BAR5_START 0x02c 173 #define AFI_FPCI_BAR0 0x030 174 #define AFI_FPCI_BAR1 0x034 175 #define AFI_FPCI_BAR2 0x038 176 #define AFI_FPCI_BAR3 0x03c 177 #define AFI_FPCI_BAR4 0x040 178 #define AFI_FPCI_BAR5 0x044 179 #define AFI_MSI_BAR_SZ 0x060 180 #define AFI_MSI_FPCI_BAR_ST 0x064 181 #define AFI_MSI_AXI_BAR_ST 0x068 182 183 184 #define AFI_AXI_BAR6_SZ 0x134 185 #define AFI_AXI_BAR7_SZ 0x138 186 #define AFI_AXI_BAR8_SZ 0x13c 187 #define AFI_AXI_BAR6_START 0x140 188 #define AFI_AXI_BAR7_START 0x144 189 #define AFI_AXI_BAR8_START 0x148 190 #define AFI_FPCI_BAR6 0x14c 191 #define AFI_FPCI_BAR7 0x150 192 #define AFI_FPCI_BAR8 0x154 193 194 #define AFI_CONFIGURATION 0x0ac 195 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 196 197 #define AFI_FPCI_ERROR_MASKS 0x0b0 198 #define AFI_INTR_MASK 0x0b4 199 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 200 #define AFI_INTR_MASK_INT_MASK (1 << 0) 201 202 #define AFI_INTR_CODE 0x0b8 203 #define AFI_INTR_CODE_MASK 0xf 204 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 205 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 206 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 207 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 208 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 209 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 210 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 211 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 212 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 213 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 214 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 215 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 216 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 217 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 218 219 220 #define AFI_INTR_SIGNATURE 0x0bc 221 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 222 #define AFI_SM_INTR_ENABLE 0x0c4 223 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 224 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 225 #define AFI_SM_INTR_HOTPLUG (1 << 12) 226 #define AFI_SM_INTR_PME (1 << 11) 227 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 228 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 229 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 230 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 231 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 232 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 233 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 234 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 235 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 236 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 237 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 238 239 #define AFI_AFI_INTR_ENABLE 0x0c8 240 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 241 242 #define AFI_PCIE_CONFIG 0x0f8 243 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 244 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 245 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 246 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 247 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 248 249 #define AFI_FUSE 0x104 250 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 251 252 #define AFI_PEX0_CTRL 0x110 253 #define AFI_PEX1_CTRL 0x118 254 #define AFI_PEX2_CTRL 0x128 255 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 256 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 257 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 258 #define AFI_PEX_CTRL_RST_L (1 << 0) 259 260 #define AFI_AXI_BAR6_SZ 0x134 261 #define AFI_AXI_BAR7_SZ 0x138 262 #define AFI_AXI_BAR8_SZ 0x13c 263 #define AFI_AXI_BAR6_START 0x140 264 #define AFI_AXI_BAR7_START 0x144 265 #define AFI_AXI_BAR8_START 0x148 266 #define AFI_FPCI_BAR6 0x14c 267 #define AFI_FPCI_BAR7 0x150 268 #define AFI_FPCI_BAR8 0x154 269 #define AFI_PLLE_CONTROL 0x160 270 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 271 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 272 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 273 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 274 275 #define AFI_PEXBIAS_CTRL 0x168 276 277 /* FPCI Address space */ 278 #define FPCI_MAP_IO 0xfdfc000000ULL 279 #define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 280 #define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 281 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 282 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 283 284 /* Configuration space */ 285 #define RP_VEND_XP 0x00000F00 286 #define RP_VEND_XP_DL_UP (1 << 30) 287 288 #define RP_PRIV_MISC 0x00000FE0 289 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 290 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 291 292 #define RP_LINK_CONTROL_STATUS 0x00000090 293 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 294 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 295 296 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 297 298 #define DEBUG 299 #ifdef DEBUG 300 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 301 #else 302 #define debugf(fmt, args...) 303 #endif 304 305 /* 306 * Configuration space format: 307 * [27:24] extended register 308 * [23:16] bus 309 * [15:11] slot (device) 310 * [10: 8] function 311 * [ 7: 0] register 312 */ 313 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 314 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 315 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 316 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 317 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 318 319 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 320 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 321 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 322 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 323 324 static struct { 325 bus_size_t axi_start; 326 bus_size_t fpci_start; 327 bus_size_t size; 328 } bars[] = { 329 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 330 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 331 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 332 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 333 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 334 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 335 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 336 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 337 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 338 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 339 }; 340 341 /* Compatible devices. */ 342 static struct ofw_compat_data compat_data[] = { 343 {"nvidia,tegra124-pcie", 1}, 344 {NULL, 0}, 345 }; 346 347 struct tegra_pcib_port { 348 int enabled; 349 int port_idx; /* chip port index */ 350 int num_lanes; /* number of lanes */ 351 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 352 353 /* Config space properties. */ 354 bus_addr_t rp_base_addr; /* PA of config window */ 355 bus_size_t rp_size; /* size of config window */ 356 bus_space_handle_t cfg_handle; /* handle of config window */ 357 }; 358 359 #define TEGRA_PCIB_MAX_PORTS 3 360 struct tegra_pcib_softc { 361 device_t dev; 362 struct mtx mtx; 363 struct ofw_bus_iinfo pci_iinfo; 364 struct rman pref_mem_rman; 365 struct rman mem_rman; 366 struct rman io_rman; 367 struct resource *pads_mem_res; 368 struct resource *afi_mem_res; 369 struct resource *cfg_mem_res; 370 struct resource *irq_res; 371 struct resource *msi_irq_res; 372 void *intr_cookie; 373 void *msi_intr_cookie; 374 375 struct tegra_pci_range mem_range; 376 struct tegra_pci_range pref_mem_range; 377 struct tegra_pci_range io_range; 378 379 phy_t phy; 380 clk_t clk_pex; 381 clk_t clk_afi; 382 clk_t clk_pll_e; 383 clk_t clk_cml; 384 hwreset_t hwreset_pex; 385 hwreset_t hwreset_afi; 386 hwreset_t hwreset_pcie_x; 387 regulator_t supply_avddio_pex; 388 regulator_t supply_dvddio_pex; 389 regulator_t supply_avdd_pex_pll; 390 regulator_t supply_hvdd_pex; 391 regulator_t supply_hvdd_pex_pll_e; 392 regulator_t supply_vddio_pex_ctl; 393 regulator_t supply_avdd_pll_erefe; 394 395 int busnr; /* host bridge bus number */ 396 uint32_t msi_bitmap; 397 bus_addr_t cfg_base_addr; /* base address of config */ 398 bus_size_t cfg_cur_offs; /* currently mapped window */ 399 bus_space_handle_t cfg_handle; /* handle of config window */ 400 bus_space_tag_t bus_tag; /* tag of config window */ 401 int lanes_cfg; 402 int num_ports; 403 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 404 }; 405 406 /* ------------------------------------------------------------------------- */ 407 /* 408 * Resource manager 409 */ 410 static int 411 tegra_pcib_rman_init(struct tegra_pcib_softc *sc) 412 { 413 int err; 414 char buf[64]; 415 416 /* Memory management. */ 417 sc->pref_mem_rman.rm_type = RMAN_ARRAY; 418 snprintf(buf, sizeof(buf), "%s prefetchable memory space", 419 device_get_nameunit(sc->dev)); 420 sc->pref_mem_rman.rm_descr = strdup(buf, M_DEVBUF); 421 err = rman_init(&sc->pref_mem_rman); 422 if (err) 423 return (err); 424 425 sc->mem_rman.rm_type = RMAN_ARRAY; 426 snprintf(buf, sizeof(buf), "%s non prefetchable memory space", 427 device_get_nameunit(sc->dev)); 428 sc->mem_rman.rm_descr = strdup(buf, M_DEVBUF); 429 err = rman_init(&sc->mem_rman); 430 if (err) 431 return (err); 432 433 sc->io_rman.rm_type = RMAN_ARRAY; 434 snprintf(buf, sizeof(buf), "%s I/O space", 435 device_get_nameunit(sc->dev)); 436 sc->io_rman.rm_descr = strdup(buf, M_DEVBUF); 437 err = rman_init(&sc->io_rman); 438 if (err) { 439 rman_fini(&sc->mem_rman); 440 return (err); 441 } 442 443 err = rman_manage_region(&sc->pref_mem_rman, 444 sc->pref_mem_range.host_addr, 445 sc->pref_mem_range.host_addr + sc->pref_mem_range.size - 1); 446 if (err) 447 goto error; 448 err = rman_manage_region(&sc->mem_rman, 449 sc->mem_range.host_addr, 450 sc->mem_range.host_addr + sc->mem_range.size - 1); 451 if (err) 452 goto error; 453 err = rman_manage_region(&sc->io_rman, 454 sc->io_range.pci_addr, 455 sc->io_range.pci_addr + sc->io_range.size - 1); 456 if (err) 457 goto error; 458 return (0); 459 460 error: 461 rman_fini(&sc->pref_mem_rman); 462 rman_fini(&sc->mem_rman); 463 rman_fini(&sc->io_rman); 464 return (err); 465 } 466 467 static struct rman * 468 tegra_pcib_rman(struct tegra_pcib_softc *sc, int type, u_int flags) 469 { 470 471 switch (type) { 472 case SYS_RES_IOPORT: 473 return (&sc->io_rman); 474 case SYS_RES_MEMORY: 475 if (flags & RF_PREFETCHABLE) 476 return (&sc->pref_mem_rman); 477 else 478 return (&sc->mem_rman); 479 default: 480 break; 481 } 482 483 return (NULL); 484 } 485 486 static struct resource * 487 tegra_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 488 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 489 { 490 struct tegra_pcib_softc *sc; 491 struct rman *rm; 492 struct resource *res; 493 494 debugf("%s: enter %d start %#jx end %#jx count %#jx\n", __func__, 495 type, start, end, count); 496 sc = device_get_softc(dev); 497 498 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 499 if (type == PCI_RES_BUS) { 500 return (pci_domain_alloc_bus(0, child, rid, start, end, count, 501 flags)); 502 } 503 #endif 504 505 rm = tegra_pcib_rman(sc, type, flags); 506 507 if (rm == NULL) { 508 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 509 type, rid, start, end, count, flags); 510 511 return (res); 512 } 513 514 if (bootverbose) { 515 device_printf(dev, 516 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 517 start, end, count); 518 } 519 520 res = rman_reserve_resource(rm, start, end, count, flags, child); 521 if (res == NULL) 522 goto fail; 523 rman_set_rid(res, *rid); 524 if (flags & RF_ACTIVE) { 525 if (bus_activate_resource(child, type, *rid, res)) { 526 rman_release_resource(res); 527 goto fail; 528 } 529 } 530 return (res); 531 532 fail: 533 if (bootverbose) { 534 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 535 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 536 __func__, type, *rid, start, end, count, flags); 537 } 538 539 return (NULL); 540 } 541 542 static int 543 tegra_pcib_release_resource(device_t dev, device_t child, int type, int rid, 544 struct resource *res) 545 { 546 struct tegra_pcib_softc *sc; 547 struct rman *rm; 548 549 sc = device_get_softc(dev); 550 debugf("%s: %d rid %x\n", __func__, type, rid); 551 552 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 553 if (type == PCI_RES_BUS) 554 return (pci_domain_release_bus(0, child, rid, res)); 555 #endif 556 557 rm = tegra_pcib_rman(sc, type, rman_get_flags(res)); 558 if (rm != NULL) { 559 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 560 rman_release_resource(res); 561 } 562 563 return (bus_generic_release_resource(dev, child, type, rid, res)); 564 } 565 566 static int 567 tegra_pcib_adjust_resource(device_t dev, device_t child, int type, 568 struct resource *res, rman_res_t start, rman_res_t end) 569 { 570 struct tegra_pcib_softc *sc; 571 struct rman *rm; 572 573 sc = device_get_softc(dev); 574 debugf("%s: %d start %jx end %jx \n", __func__, type, start, end); 575 576 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 577 if (type == PCI_RES_BUS) 578 return (pci_domain_adjust_bus(0, child, res, start, end)); 579 #endif 580 581 rm = tegra_pcib_rman(sc, type, rman_get_flags(res)); 582 if (rm != NULL) 583 return (rman_adjust_resource(res, start, end)); 584 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 585 } 586 extern bus_space_tag_t fdtbus_bs_tag; 587 static int 588 tegra_pcib_pcie_activate_resource(device_t dev, device_t child, int type, 589 int rid, struct resource *r) 590 { 591 struct tegra_pcib_softc *sc; 592 vm_offset_t start; 593 void *p; 594 int rv; 595 596 sc = device_get_softc(dev); 597 rv = rman_activate_resource(r); 598 if (rv != 0) 599 return (rv); 600 switch(type) { 601 case SYS_RES_IOPORT: 602 start = rman_get_start(r) + sc->io_range.host_addr; 603 break; 604 default: 605 start = rman_get_start(r); 606 rman_get_start(r); 607 break; 608 } 609 610 if (bootverbose) 611 printf("%s: start %zx, len %jd\n", __func__, start, 612 rman_get_size(r)); 613 614 p = pmap_mapdev(start, (vm_size_t)rman_get_size(r)); 615 rman_set_virtual(r, p); 616 rman_set_bustag(r, fdtbus_bs_tag); 617 rman_set_bushandle(r, (u_long)p); 618 return (0); 619 } 620 621 /* ------------------------------------------------------------------------- */ 622 /* 623 * IVARs 624 */ 625 static int 626 tegra_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 627 { 628 struct tegra_pcib_softc *sc = device_get_softc(dev); 629 630 switch (which) { 631 case PCIB_IVAR_BUS: 632 *result = sc->busnr; 633 return (0); 634 case PCIB_IVAR_DOMAIN: 635 *result = device_get_unit(dev); 636 return (0); 637 } 638 639 return (ENOENT); 640 } 641 642 static int 643 tegra_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 644 { 645 struct tegra_pcib_softc *sc = device_get_softc(dev); 646 647 switch (which) { 648 case PCIB_IVAR_BUS: 649 sc->busnr = value; 650 return (0); 651 } 652 653 return (ENOENT); 654 } 655 656 static int 657 tegra_pcib_maxslots(device_t dev) 658 { 659 return (16); 660 } 661 662 663 static int 664 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 665 { 666 struct tegra_pcib_softc *sc; 667 668 sc = device_get_softc(bus); 669 device_printf(bus, "route pin %d for device %d.%d to %ju\n", 670 pin, pci_get_slot(dev), pci_get_function(dev), 671 rman_get_start(sc->irq_res)); 672 673 return (rman_get_start(sc->irq_res)); 674 } 675 676 static int 677 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 678 u_int func, u_int reg) 679 { 680 bus_size_t offs; 681 int rv; 682 683 offs = sc->cfg_base_addr; 684 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 685 PCI_CFG_EXT_REG(reg); 686 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 687 return (0); 688 if (sc->cfg_handle != 0) 689 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 690 691 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 692 if (rv != 0) 693 device_printf(sc->dev, "Cannot map config space\n"); 694 else 695 sc->cfg_cur_offs = offs; 696 return (rv); 697 } 698 699 static uint32_t 700 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 701 u_int reg, int bytes) 702 { 703 struct tegra_pcib_softc *sc; 704 bus_space_handle_t hndl; 705 uint32_t off; 706 uint32_t val; 707 int rv, i; 708 709 sc = device_get_softc(dev); 710 if (bus == 0) { 711 if (func != 0) 712 return (0xFFFFFFFF); 713 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 714 if ((sc->ports[i] != NULL) && 715 (sc->ports[i]->port_idx == slot)) { 716 hndl = sc->ports[i]->cfg_handle; 717 off = reg & 0xFFF; 718 break; 719 } 720 } 721 if (i >= TEGRA_PCIB_MAX_PORTS) 722 return (0xFFFFFFFF); 723 } else { 724 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 725 if (rv != 0) 726 return (0xFFFFFFFF); 727 hndl = sc->cfg_handle; 728 off = PCI_CFG_BASE_REG(reg); 729 } 730 731 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 732 switch (bytes) { 733 case 4: 734 break; 735 case 2: 736 if (off & 3) 737 val >>= 16; 738 val &= 0xffff; 739 break; 740 case 1: 741 val >>= ((off & 3) << 3); 742 val &= 0xff; 743 break; 744 } 745 return val; 746 } 747 748 static void 749 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 750 u_int reg, uint32_t val, int bytes) 751 { 752 struct tegra_pcib_softc *sc; 753 bus_space_handle_t hndl; 754 uint32_t off; 755 uint32_t val2; 756 int rv, i; 757 758 sc = device_get_softc(dev); 759 if (bus == 0) { 760 if (func != 0) 761 return; 762 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 763 if ((sc->ports[i] != NULL) && 764 (sc->ports[i]->port_idx == slot)) { 765 hndl = sc->ports[i]->cfg_handle; 766 off = reg & 0xFFF; 767 break; 768 } 769 } 770 if (i >= TEGRA_PCIB_MAX_PORTS) 771 return; 772 } else { 773 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 774 if (rv != 0) 775 return; 776 hndl = sc->cfg_handle; 777 off = PCI_CFG_BASE_REG(reg); 778 } 779 780 switch (bytes) { 781 case 4: 782 bus_space_write_4(sc->bus_tag, hndl, off, val); 783 break; 784 case 2: 785 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 786 val2 &= ~(0xffff << ((off & 3) << 3)); 787 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 788 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 789 break; 790 case 1: 791 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 792 val2 &= ~(0xff << ((off & 3) << 3)); 793 val2 |= ((val & 0xff) << ((off & 3) << 3)); 794 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 795 break; 796 } 797 } 798 799 static int tegra_pci_intr(void *arg) 800 { 801 struct tegra_pcib_softc *sc = arg; 802 uint32_t code, signature; 803 804 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 805 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 806 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 807 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 808 return(FILTER_STRAY); 809 810 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 811 return (FILTER_HANDLED); 812 } 813 814 #if defined(TEGRA_PCI_MSI) 815 static int 816 tegra_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 817 uint32_t *data) 818 { 819 struct tegra_pcib_softc *sc; 820 821 sc = device_get_softc(dev); 822 irq = irq - MSI_IRQ; 823 824 /* validate parameters */ 825 if (isclr(&sc->msi_bitmap, irq)) { 826 device_printf(dev, "invalid MSI 0x%x\n", irq); 827 return (EINVAL); 828 } 829 830 tegra_msi_data(irq, addr, data); 831 832 debugf("%s: irq: %d addr: %jx data: %x\n", 833 __func__, irq, *addr, *data); 834 835 return (0); 836 } 837 838 static int 839 tegra_pcib_alloc_msi(device_t dev, device_t child, int count, 840 int maxcount __unused, int *irqs) 841 { 842 struct tegra_pcib_softc *sc; 843 u_int start = 0, i; 844 845 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 846 return (EINVAL); 847 848 sc = device_get_softc(dev); 849 mtx_lock(&sc->mtx); 850 851 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 852 for (i = start; i < start + count; i++) { 853 if (isset(&sc->msi_bitmap, i)) 854 break; 855 } 856 if (i == start + count) 857 break; 858 } 859 860 if ((start + count) == MSI_IRQ_NUM) { 861 mtx_unlock(&sc->mtx); 862 return (ENXIO); 863 } 864 865 for (i = start; i < start + count; i++) { 866 setbit(&sc->msi_bitmap, i); 867 irqs[i] = MSI_IRQ + i; 868 } 869 debugf("%s: start: %x count: %x\n", __func__, start, count); 870 871 mtx_unlock(&sc->mtx); 872 return (0); 873 } 874 875 static int 876 tegra_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 877 { 878 struct tegra_pcib_softc *sc; 879 u_int i; 880 881 sc = device_get_softc(dev); 882 mtx_lock(&sc->mtx); 883 884 for (i = 0; i < count; i++) 885 clrbit(&sc->msi_bitmap, irqs[i] - MSI_IRQ); 886 887 mtx_unlock(&sc->mtx); 888 return (0); 889 } 890 #endif 891 892 static bus_size_t 893 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 894 { 895 if (port >= TEGRA_PCIB_MAX_PORTS) 896 panic("invalid port number: %d\n", port); 897 898 if (port == 0) 899 return (AFI_PEX0_CTRL); 900 else if (port == 1) 901 return (AFI_PEX1_CTRL); 902 else if (port == 2) 903 return (AFI_PEX2_CTRL); 904 else 905 panic("invalid port number: %d\n", port); 906 } 907 908 static int 909 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 910 { 911 int rv; 912 913 rv = hwreset_assert(sc->hwreset_pcie_x); 914 if (rv != 0) { 915 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 916 return (rv); 917 } 918 rv = hwreset_assert(sc->hwreset_afi); 919 if (rv != 0) { 920 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 921 return (rv); 922 } 923 rv = hwreset_assert(sc->hwreset_pex); 924 if (rv != 0) { 925 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 926 return (rv); 927 } 928 929 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 930 931 /* Power supplies. */ 932 rv = regulator_enable(sc->supply_avddio_pex); 933 if (rv != 0) { 934 device_printf(sc->dev, 935 "Cannot enable 'avddio_pex' regulator\n"); 936 return (rv); 937 } 938 rv = regulator_enable(sc->supply_dvddio_pex); 939 if (rv != 0) { 940 device_printf(sc->dev, 941 "Cannot enable 'dvddio_pex' regulator\n"); 942 return (rv); 943 } 944 rv = regulator_enable(sc->supply_avdd_pex_pll); 945 if (rv != 0) { 946 device_printf(sc->dev, 947 "Cannot enable 'avdd-pex-pll' regulator\n"); 948 return (rv); 949 } 950 951 rv = regulator_enable(sc->supply_hvdd_pex); 952 if (rv != 0) { 953 device_printf(sc->dev, 954 "Cannot enable 'hvdd-pex-supply' regulator\n"); 955 return (rv); 956 } 957 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 958 if (rv != 0) { 959 device_printf(sc->dev, 960 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 961 return (rv); 962 } 963 rv = regulator_enable(sc->supply_vddio_pex_ctl); 964 if (rv != 0) { 965 device_printf(sc->dev, 966 "Cannot enable 'vddio-pex-ctl' regulator\n"); 967 return (rv); 968 } 969 rv = regulator_enable(sc->supply_avdd_pll_erefe); 970 if (rv != 0) { 971 device_printf(sc->dev, 972 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 973 return (rv); 974 } 975 976 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 977 sc->clk_pex, sc->hwreset_pex); 978 if (rv != 0) { 979 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 980 return (rv); 981 } 982 983 rv = hwreset_deassert(sc->hwreset_afi); 984 if (rv != 0) { 985 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 986 return (rv); 987 } 988 989 rv = clk_enable(sc->clk_afi); 990 if (rv != 0) { 991 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 992 return (rv); 993 } 994 995 rv = clk_enable(sc->clk_cml); 996 if (rv != 0) { 997 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 998 return (rv); 999 } 1000 1001 rv = clk_enable(sc->clk_pll_e); 1002 if (rv != 0) { 1003 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 1004 return (rv); 1005 } 1006 return (0); 1007 } 1008 1009 static struct tegra_pcib_port * 1010 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 1011 { 1012 struct tegra_pcib_port *port; 1013 uint32_t tmp[5]; 1014 char tmpstr[6]; 1015 int rv; 1016 1017 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 1018 1019 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 1020 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 1021 strcmp(tmpstr, "ok") == 0) 1022 port->enabled = 1; 1023 else 1024 port->enabled = 0; 1025 1026 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 1027 if (rv != sizeof(tmp)) { 1028 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 1029 rv); 1030 goto fail; 1031 } 1032 port->rp_base_addr = tmp[2]; 1033 port->rp_size = tmp[4]; 1034 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 1035 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 1036 device_printf(sc->dev, "Invalid port index: %d\n", 1037 port->port_idx); 1038 goto fail; 1039 } 1040 /* XXX - TODO: 1041 * Implement proper function for parsing pci "reg" property: 1042 * - it have PCI bus format 1043 * - its relative to matching "assigned-addresses" 1044 */ 1045 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 1046 if (rv != sizeof(tmp)) { 1047 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 1048 goto fail; 1049 } 1050 port->rp_base_addr += tmp[2]; 1051 1052 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 1053 sizeof(port->num_lanes)); 1054 if (rv != sizeof(port->num_lanes)) { 1055 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 1056 rv); 1057 goto fail; 1058 } 1059 if (port->num_lanes > 4) { 1060 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 1061 port->num_lanes); 1062 goto fail; 1063 } 1064 1065 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 1066 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 1067 1068 return (port); 1069 fail: 1070 free(port, M_DEVBUF); 1071 return (NULL); 1072 } 1073 1074 1075 static int 1076 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 1077 { 1078 phandle_t child; 1079 struct tegra_pcib_port *port; 1080 int rv; 1081 1082 /* Power supplies. */ 1083 rv = regulator_get_by_ofw_property(sc->dev, "avddio-pex-supply", 1084 &sc->supply_avddio_pex); 1085 if (rv != 0) { 1086 device_printf(sc->dev, 1087 "Cannot get 'avddio-pex' regulator\n"); 1088 return (ENXIO); 1089 } 1090 rv = regulator_get_by_ofw_property(sc->dev, "dvddio-pex-supply", 1091 &sc->supply_dvddio_pex); 1092 if (rv != 0) { 1093 device_printf(sc->dev, 1094 "Cannot get 'dvddio-pex' regulator\n"); 1095 return (ENXIO); 1096 } 1097 rv = regulator_get_by_ofw_property(sc->dev, "avdd-pex-pll-supply", 1098 &sc->supply_avdd_pex_pll); 1099 if (rv != 0) { 1100 device_printf(sc->dev, 1101 "Cannot get 'avdd-pex-pll' regulator\n"); 1102 return (ENXIO); 1103 } 1104 rv = regulator_get_by_ofw_property(sc->dev, "hvdd-pex-supply", 1105 &sc->supply_hvdd_pex); 1106 if (rv != 0) { 1107 device_printf(sc->dev, 1108 "Cannot get 'hvdd-pex' regulator\n"); 1109 return (ENXIO); 1110 } 1111 rv = regulator_get_by_ofw_property(sc->dev, "hvdd-pex-pll-e-supply", 1112 &sc->supply_hvdd_pex_pll_e); 1113 if (rv != 0) { 1114 device_printf(sc->dev, 1115 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1116 return (ENXIO); 1117 } 1118 rv = regulator_get_by_ofw_property(sc->dev, "vddio-pex-ctl-supply", 1119 &sc->supply_vddio_pex_ctl); 1120 if (rv != 0) { 1121 device_printf(sc->dev, 1122 "Cannot get 'vddio-pex-ctl' regulator\n"); 1123 return (ENXIO); 1124 } 1125 rv = regulator_get_by_ofw_property(sc->dev, "avdd-pll-erefe-supply", 1126 &sc->supply_avdd_pll_erefe); 1127 if (rv != 0) { 1128 device_printf(sc->dev, 1129 "Cannot get 'avdd-pll-erefe' regulator\n"); 1130 return (ENXIO); 1131 } 1132 1133 /* Resets. */ 1134 rv = hwreset_get_by_ofw_name(sc->dev, "pex", &sc->hwreset_pex); 1135 if (rv != 0) { 1136 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1137 return (ENXIO); 1138 } 1139 rv = hwreset_get_by_ofw_name(sc->dev, "afi", &sc->hwreset_afi); 1140 if (rv != 0) { 1141 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1142 return (ENXIO); 1143 } 1144 rv = hwreset_get_by_ofw_name(sc->dev, "pcie_x", &sc->hwreset_pcie_x); 1145 if (rv != 0) { 1146 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1147 return (ENXIO); 1148 } 1149 1150 /* Clocks. */ 1151 rv = clk_get_by_ofw_name(sc->dev, "pex", &sc->clk_pex); 1152 if (rv != 0) { 1153 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1154 return (ENXIO); 1155 } 1156 rv = clk_get_by_ofw_name(sc->dev, "afi", &sc->clk_afi); 1157 if (rv != 0) { 1158 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1159 return (ENXIO); 1160 } 1161 rv = clk_get_by_ofw_name(sc->dev, "pll_e", &sc->clk_pll_e); 1162 if (rv != 0) { 1163 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1164 return (ENXIO); 1165 } 1166 rv = clk_get_by_ofw_name(sc->dev, "cml", &sc->clk_cml); 1167 if (rv != 0) { 1168 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1169 return (ENXIO); 1170 } 1171 1172 /* Phy. */ 1173 rv = phy_get_by_ofw_name(sc->dev, "pcie", &sc->phy); 1174 if (rv != 0) { 1175 device_printf(sc->dev, "Cannot get 'pcie' phy\n"); 1176 return (ENXIO); 1177 } 1178 1179 /* Ports */ 1180 sc->num_ports = 0; 1181 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1182 port = tegra_pcib_parse_port(sc, child); 1183 if (port == NULL) { 1184 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1185 return (ENXIO); 1186 } 1187 sc->ports[sc->num_ports++] = port; 1188 } 1189 1190 return (0); 1191 } 1192 1193 static int 1194 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1195 struct tegra_pci_range *ranges, int nranges) 1196 { 1197 int i; 1198 1199 for (i = 2; i < nranges; i++) { 1200 if (ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_IO) { 1201 if (sc->io_range.size != 0) { 1202 device_printf(sc->dev, 1203 "Duplicated IO range found in DT\n"); 1204 return (ENXIO); 1205 } 1206 sc->io_range = ranges[i]; 1207 } 1208 if ((ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_MEM32) && 1209 !ranges[i].prefetchable) { 1210 if (sc->mem_range.size != 0) { 1211 device_printf(sc->dev, 1212 "Duplicated memory range found in DT\n"); 1213 return (ENXIO); 1214 } 1215 sc->mem_range = ranges[i]; 1216 } 1217 if ((ranges[i].space_code == OFW_PCI_PHYS_HI_SPACE_MEM32) && 1218 ranges[i].prefetchable) { 1219 if (sc->pref_mem_range.size != 0) { 1220 device_printf(sc->dev, 1221 "Duplicated memory range found in DT\n"); 1222 return (ENXIO); 1223 } 1224 sc->pref_mem_range = ranges[i]; 1225 } 1226 } 1227 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1228 || (sc->pref_mem_range.size == 0)) { 1229 device_printf(sc->dev, 1230 " Not all required ranges are found in DT\n"); 1231 return (ENXIO); 1232 } 1233 return (0); 1234 } 1235 1236 /* 1237 * Hardware config. 1238 */ 1239 static int 1240 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1241 struct tegra_pcib_port *port) 1242 { 1243 uint32_t reg; 1244 int i; 1245 1246 1247 /* Setup link detection. */ 1248 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1249 RP_PRIV_MISC, 4); 1250 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1251 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1252 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1253 RP_PRIV_MISC, reg, 4); 1254 1255 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1256 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1257 RP_VEND_XP, 4); 1258 if (reg & RP_VEND_XP_DL_UP) 1259 break; 1260 1261 } 1262 if (i <= 0) 1263 return (ETIMEDOUT); 1264 1265 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1266 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1267 RP_LINK_CONTROL_STATUS, 4); 1268 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1269 break; 1270 1271 } 1272 if (i <= 0) 1273 return (ETIMEDOUT); 1274 return (0); 1275 } 1276 1277 static void 1278 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1279 { 1280 struct tegra_pcib_port *port; 1281 uint32_t reg; 1282 int rv; 1283 1284 port = sc->ports[port_num]; 1285 1286 /* Put port to reset. */ 1287 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1288 reg &= ~AFI_PEX_CTRL_RST_L; 1289 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1290 AFI_RD4(sc, port->afi_pex_ctrl); 1291 DELAY(10); 1292 1293 /* Enable clocks. */ 1294 reg |= AFI_PEX_CTRL_REFCLK_EN; 1295 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1296 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1297 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1298 AFI_RD4(sc, port->afi_pex_ctrl); 1299 DELAY(100); 1300 1301 /* Release reset. */ 1302 reg |= AFI_PEX_CTRL_RST_L; 1303 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1304 1305 rv = tegra_pcib_wait_for_link(sc, port); 1306 if (bootverbose) 1307 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1308 port->port_idx, port->num_lanes, 1309 port->num_lanes > 1 ? "s": "", 1310 rv == 0 ? "up": "down"); 1311 } 1312 1313 1314 static void 1315 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1316 { 1317 struct tegra_pcib_port *port; 1318 uint32_t reg; 1319 1320 port = sc->ports[port_num]; 1321 1322 /* Put port to reset. */ 1323 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1324 reg &= ~AFI_PEX_CTRL_RST_L; 1325 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1326 AFI_RD4(sc, port->afi_pex_ctrl); 1327 DELAY(10); 1328 1329 /* Disable clocks. */ 1330 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1331 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1332 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1333 1334 if (bootverbose) 1335 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1336 port->port_idx, port->num_lanes, 1337 port->num_lanes > 1 ? "s": ""); 1338 } 1339 1340 static void 1341 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1342 uint64_t fpci, uint32_t size, int is_memory) 1343 { 1344 uint32_t fpci_reg; 1345 uint32_t axi_reg; 1346 uint32_t size_reg; 1347 1348 axi_reg = axi & ~0xFFF; 1349 size_reg = size >> 12; 1350 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1351 fpci_reg |= is_memory ? 0x1 : 0x0; 1352 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1353 AFI_WR4(sc, bars[bar].size, size_reg); 1354 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1355 } 1356 1357 static int 1358 tegra_pcib_enable(struct tegra_pcib_softc *sc, uint32_t port) 1359 { 1360 int rv; 1361 int i; 1362 uint32_t reg; 1363 1364 rv = tegra_pcib_enable_fdt_resources(sc); 1365 if (rv != 0) { 1366 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1367 return (rv); 1368 } 1369 /* Enable PLLE control. */ 1370 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1371 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1372 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1373 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1374 1375 /* Set bias pad. */ 1376 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1377 1378 /* Configure mode and ports. */ 1379 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1380 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1381 if (sc->lanes_cfg == 0x14) { 1382 if (bootverbose) 1383 device_printf(sc->dev, 1384 "Using x1,x4 configuration\n"); 1385 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1386 } else if (sc->lanes_cfg == 0x12) { 1387 if (bootverbose) 1388 device_printf(sc->dev, 1389 "Using x1,x2 configuration\n"); 1390 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1391 } else { 1392 device_printf(sc->dev, 1393 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1394 } 1395 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1396 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1397 if ((sc->ports[i] != NULL)) 1398 reg &= 1399 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1400 } 1401 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1402 1403 /* Enable Gen2 support. */ 1404 reg = AFI_RD4(sc, AFI_FUSE); 1405 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1406 AFI_WR4(sc, AFI_FUSE, reg); 1407 1408 /* Enable PCIe phy. */ 1409 rv = phy_enable(sc->dev, sc->phy); 1410 if (rv != 0) { 1411 device_printf(sc->dev, "Cannot enable phy\n"); 1412 return (rv); 1413 } 1414 1415 rv = hwreset_deassert(sc->hwreset_pcie_x); 1416 if (rv != 0) { 1417 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1418 return (rv); 1419 } 1420 1421 /* Enable config space. */ 1422 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1423 reg |= AFI_CONFIGURATION_EN_FPCI; 1424 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1425 1426 /* Enable AFI errors. */ 1427 reg = 0; 1428 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1429 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1430 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1431 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1432 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1433 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1434 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1435 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1436 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1437 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1438 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1439 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1440 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1441 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1442 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1443 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1444 1445 /* Enable INT, disable MSI. */ 1446 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1447 1448 /* Mask all FPCI errors. */ 1449 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1450 1451 /* Setup AFI translation windows. */ 1452 /* BAR 0 - type 1 extended configuration. */ 1453 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1454 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1455 1456 /* BAR 1 - downstream I/O. */ 1457 tegra_pcib_set_bar(sc, 1, sc->io_range.host_addr, FPCI_MAP_IO, 1458 sc->io_range.size, 0); 1459 1460 /* BAR 2 - downstream prefetchable memory 1:1. */ 1461 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host_addr, 1462 sc->pref_mem_range.host_addr, sc->pref_mem_range.size, 1); 1463 1464 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1465 tegra_pcib_set_bar(sc, 3, sc->mem_range.host_addr, 1466 sc->mem_range.host_addr, sc->mem_range.size, 1); 1467 1468 /* BAR 3-8 clear. */ 1469 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1470 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1471 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1472 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1473 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1474 1475 /* MSI BAR - clear. */ 1476 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1477 return(0); 1478 } 1479 1480 static int 1481 tegra_pcib_probe(device_t dev) 1482 { 1483 if (!ofw_bus_status_okay(dev)) 1484 return (ENXIO); 1485 1486 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1487 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1488 return (BUS_PROBE_DEFAULT); 1489 } 1490 return (ENXIO); 1491 } 1492 1493 static int 1494 tegra_pcib_attach(device_t dev) 1495 { 1496 struct tegra_pcib_softc *sc; 1497 phandle_t node; 1498 uint32_t unit; 1499 int rv; 1500 int rid; 1501 int nranges; 1502 struct tegra_pci_range *ranges; 1503 struct tegra_pcib_port *port; 1504 int i; 1505 1506 sc = device_get_softc(dev); 1507 sc->dev = dev; 1508 unit = fdt_get_unit(dev); 1509 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1510 1511 1512 node = ofw_bus_get_node(dev); 1513 1514 rv = tegra_pcib_parse_fdt_resources(sc, node); 1515 if (rv != 0) { 1516 device_printf(dev, "Cannot get FDT resources\n"); 1517 return (rv); 1518 } 1519 1520 nranges = tegra_pci_get_ranges(node, &ranges); 1521 if (nranges != 5) { 1522 device_printf(sc->dev, "Unexpected number of ranges: %d\n", 1523 nranges); 1524 rv = ENXIO; 1525 goto out; 1526 } 1527 1528 /* Allocate bus_space resources. */ 1529 rid = 0; 1530 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1531 RF_ACTIVE); 1532 if (sc->pads_mem_res == NULL) { 1533 device_printf(dev, "Cannot allocate PADS register\n"); 1534 rv = ENXIO; 1535 goto out; 1536 } 1537 /* 1538 * XXX - FIXME 1539 * tag for config space is not filled when RF_ALLOCATED flag is used. 1540 */ 1541 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1542 1543 rid = 1; 1544 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1545 RF_ACTIVE); 1546 if (sc->afi_mem_res == NULL) { 1547 device_printf(dev, "Cannot allocate AFI register\n"); 1548 rv = ENXIO; 1549 goto out; 1550 } 1551 1552 rid = 2; 1553 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1554 RF_ALLOCATED); 1555 if (sc->cfg_mem_res == NULL) { 1556 device_printf(dev, "Cannot allocate config space memory\n"); 1557 rv = ENXIO; 1558 goto out; 1559 } 1560 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1561 1562 1563 /* Map RP slots */ 1564 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1565 if (sc->ports[i] == NULL) 1566 continue; 1567 port = sc->ports[i]; 1568 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1569 port->rp_size, 0, &port->cfg_handle); 1570 if (rv != 0) { 1571 device_printf(sc->dev, "Cannot allocate memory for " 1572 "port: %d\n", i); 1573 rv = ENXIO; 1574 goto out; 1575 } 1576 } 1577 1578 /* 1579 * Get PCI interrupt info. 1580 */ 1581 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(pcell_t)); 1582 rid = 0; 1583 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1584 RF_ACTIVE | RF_SHAREABLE); 1585 if (sc->irq_res == NULL) { 1586 device_printf(dev, "Cannot allocate IRQ resources\n"); 1587 rv = ENXIO; 1588 goto out; 1589 } 1590 1591 rid = 1; 1592 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1593 RF_ACTIVE); 1594 if (sc->irq_res == NULL) { 1595 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1596 rv = ENXIO; 1597 goto out; 1598 } 1599 1600 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1601 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1602 device_printf(dev, "cannot setup interrupt handler\n"); 1603 rv = ENXIO; 1604 goto out; 1605 } 1606 1607 /* Memory management. */ 1608 rv = tegra_pcib_decode_ranges(sc, ranges, nranges); 1609 if (rv != 0) 1610 goto out; 1611 1612 rv = tegra_pcib_rman_init(sc); 1613 if (rv != 0) 1614 goto out; 1615 free(ranges, M_DEVBUF); 1616 ranges = NULL; 1617 1618 /* 1619 * Enable PCIE device. 1620 */ 1621 rv = tegra_pcib_enable(sc, unit); 1622 if (rv != 0) 1623 goto out; 1624 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1625 if (sc->ports[i] == NULL) 1626 continue; 1627 if (sc->ports[i]->enabled) 1628 tegra_pcib_port_enable(sc, i); 1629 else 1630 tegra_pcib_port_disable(sc, i); 1631 } 1632 1633 device_add_child(dev, "pci", -1); 1634 1635 return (bus_generic_attach(dev)); 1636 1637 out: 1638 if (ranges != NULL) 1639 free(ranges, M_DEVBUF); 1640 1641 return (rv); 1642 } 1643 1644 1645 static device_method_t tegra_pcib_methods[] = { 1646 /* Device interface */ 1647 DEVMETHOD(device_probe, tegra_pcib_probe), 1648 DEVMETHOD(device_attach, tegra_pcib_attach), 1649 1650 /* Bus interface */ 1651 DEVMETHOD(bus_read_ivar, tegra_pcib_read_ivar), 1652 DEVMETHOD(bus_write_ivar, tegra_pcib_write_ivar), 1653 DEVMETHOD(bus_alloc_resource, tegra_pcib_alloc_resource), 1654 DEVMETHOD(bus_adjust_resource, tegra_pcib_adjust_resource), 1655 DEVMETHOD(bus_release_resource, tegra_pcib_release_resource), 1656 DEVMETHOD(bus_activate_resource, tegra_pcib_pcie_activate_resource), 1657 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1658 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1659 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1660 1661 /* pcib interface */ 1662 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1663 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1664 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1665 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1666 1667 #if defined(TEGRA_PCI_MSI) 1668 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1669 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1670 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1671 #endif 1672 1673 /* OFW bus interface */ 1674 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1675 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1676 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1677 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1678 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1679 1680 DEVMETHOD_END 1681 }; 1682 1683 static driver_t tegra_pcib_driver = { 1684 "pcib", 1685 tegra_pcib_methods, 1686 sizeof(struct tegra_pcib_softc), 1687 }; 1688 1689 devclass_t pcib_devclass; 1690 1691 DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 0, 0);