1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/intr.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 #include <vm/pmap.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/phy/phy.h> 55 #include <dev/extres/regulator/regulator.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofwpci.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcib_private.h> 63 64 #include <machine/resource.h> 65 #include <machine/bus.h> 66 67 #include <arm/nvidia/tegra_pmc.h> 68 69 #include "ofw_bus_if.h" 70 #include "msi_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #define AFI_AXI_BAR0_SZ 0x000 75 #define AFI_AXI_BAR1_SZ 0x004 76 #define AFI_AXI_BAR2_SZ 0x008 77 #define AFI_AXI_BAR3_SZ 0x00c 78 #define AFI_AXI_BAR4_SZ 0x010 79 #define AFI_AXI_BAR5_SZ 0x014 80 #define AFI_AXI_BAR0_START 0x018 81 #define AFI_AXI_BAR1_START 0x01c 82 #define AFI_AXI_BAR2_START 0x020 83 #define AFI_AXI_BAR3_START 0x024 84 #define AFI_AXI_BAR4_START 0x028 85 #define AFI_AXI_BAR5_START 0x02c 86 #define AFI_FPCI_BAR0 0x030 87 #define AFI_FPCI_BAR1 0x034 88 #define AFI_FPCI_BAR2 0x038 89 #define AFI_FPCI_BAR3 0x03c 90 #define AFI_FPCI_BAR4 0x040 91 #define AFI_FPCI_BAR5 0x044 92 #define AFI_MSI_BAR_SZ 0x060 93 #define AFI_MSI_FPCI_BAR_ST 0x064 94 #define AFI_MSI_AXI_BAR_ST 0x068 95 #define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 96 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 97 #define AFI_MSI_INTR_IN_REG 32 98 #define AFI_MSI_REGS 8 99 100 #define AFI_CONFIGURATION 0x0ac 101 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 102 103 #define AFI_FPCI_ERROR_MASKS 0x0b0 104 #define AFI_INTR_MASK 0x0b4 105 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 106 #define AFI_INTR_MASK_INT_MASK (1 << 0) 107 108 #define AFI_INTR_CODE 0x0b8 109 #define AFI_INTR_CODE_MASK 0xf 110 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 111 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 112 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 113 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 114 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 115 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 116 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 117 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 118 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 119 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 120 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 121 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 122 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 123 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 124 125 #define AFI_INTR_SIGNATURE 0x0bc 126 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 127 #define AFI_SM_INTR_ENABLE 0x0c4 128 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 129 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 130 #define AFI_SM_INTR_HOTPLUG (1 << 12) 131 #define AFI_SM_INTR_PME (1 << 11) 132 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 133 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 134 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 135 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 136 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 137 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 138 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 139 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 140 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 141 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 142 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 143 144 #define AFI_AFI_INTR_ENABLE 0x0c8 145 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 146 147 #define AFI_PCIE_CONFIG 0x0f8 148 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 149 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 153 154 #define AFI_FUSE 0x104 155 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 156 157 #define AFI_PEX0_CTRL 0x110 158 #define AFI_PEX1_CTRL 0x118 159 #define AFI_PEX2_CTRL 0x128 160 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 161 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 162 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 163 #define AFI_PEX_CTRL_RST_L (1 << 0) 164 165 #define AFI_AXI_BAR6_SZ 0x134 166 #define AFI_AXI_BAR7_SZ 0x138 167 #define AFI_AXI_BAR8_SZ 0x13c 168 #define AFI_AXI_BAR6_START 0x140 169 #define AFI_AXI_BAR7_START 0x144 170 #define AFI_AXI_BAR8_START 0x148 171 #define AFI_FPCI_BAR6 0x14c 172 #define AFI_FPCI_BAR7 0x150 173 #define AFI_FPCI_BAR8 0x154 174 #define AFI_PLLE_CONTROL 0x160 175 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 176 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 177 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 178 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 179 180 #define AFI_PEXBIAS_CTRL 0x168 181 182 /* Configuration space */ 183 #define RP_VEND_XP 0x0F00 184 #define RP_VEND_XP_DL_UP (1 << 30) 185 186 #define RP_VEND_CTL2 0x0fa8 187 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 188 189 #define RP_PRIV_MISC 0x0FE0 190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 192 193 #define RP_LINK_CONTROL_STATUS 0x0090 194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 196 197 /* PADS space */ 198 #define PADS_REFCLK_CFG0 0x000c8 199 #define PADS_REFCLK_CFG1 0x000cc 200 201 202 /* Wait 50 ms (per port) for link. */ 203 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000 204 205 /* FPCI Address space */ 206 #define FPCI_MAP_IO 0xFDFC000000ULL 207 #define FPCI_MAP_TYPE0_CONFIG 0xFDFC000000ULL 208 #define FPCI_MAP_TYPE1_CONFIG 0xFDFF000000ULL 209 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xFE00000000ULL 210 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xFE10000000ULL 211 212 #define TEGRA_PCIB_MSI_ENABLE 213 214 #define DEBUG 215 #ifdef DEBUG 216 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 217 #else 218 #define debugf(fmt, args...) 219 #endif 220 221 /* 222 * Configuration space format: 223 * [27:24] extended register 224 * [23:16] bus 225 * [15:11] slot (device) 226 * [10: 8] function 227 * [ 7: 0] register 228 */ 229 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 230 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 231 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 232 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 233 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 234 235 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v)) 236 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 237 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 238 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 239 240 static struct { 241 bus_size_t axi_start; 242 bus_size_t fpci_start; 243 bus_size_t size; 244 } bars[] = { 245 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 246 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 247 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 248 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 249 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 250 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 251 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 252 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 253 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 254 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 255 }; 256 257 258 struct pcie_soc { 259 char **regulator_names; 260 bool cml_clk; 261 bool pca_enable; 262 uint32_t pads_refclk_cfg0; 263 uint32_t pads_refclk_cfg1; 264 }; 265 266 /* Tegra 124 config. */ 267 static char *tegra124_reg_names[] = { 268 "avddio-pex-supply", 269 "dvddio-pex-supply", 270 "avdd-pex-pll-supply", 271 "hvdd-pex-supply", 272 "hvdd-pex-pll-e-supply", 273 "vddio-pex-ctl-supply", 274 "avdd-pll-erefe-supply", 275 NULL 276 }; 277 278 static struct pcie_soc tegra124_soc = { 279 .regulator_names = tegra124_reg_names, 280 .cml_clk = true, 281 .pca_enable = false, 282 .pads_refclk_cfg0 = 0x44ac44ac, 283 }; 284 285 /* Tegra 210 config. */ 286 static char *tegra210_reg_names[] = { 287 "avdd-pll-uerefe-supply", 288 "hvddio-pex-supply", 289 "dvddio-pex-supply", 290 "dvdd-pex-pll-supply", 291 "hvdd-pex-pll-e-supply", 292 "vddio-pex-ctl-supply", 293 NULL 294 }; 295 296 static struct pcie_soc tegra210_soc = { 297 .regulator_names = tegra210_reg_names, 298 .cml_clk = true, 299 .pca_enable = true, 300 .pads_refclk_cfg0 = 0x90b890b8, 301 }; 302 303 /* Compatible devices. */ 304 static struct ofw_compat_data compat_data[] = { 305 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc}, 306 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc}, 307 {NULL, 0}, 308 }; 309 310 #define TEGRA_FLAG_MSI_USED 0x0001 311 struct tegra_pcib_irqsrc { 312 struct intr_irqsrc isrc; 313 u_int irq; 314 u_int flags; 315 }; 316 317 struct tegra_pcib_port { 318 int enabled; 319 int port_idx; /* chip port index */ 320 int num_lanes; /* number of lanes */ 321 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 322 phy_t phy; /* port phy */ 323 324 /* Config space properties. */ 325 bus_addr_t rp_base_addr; /* PA of config window */ 326 bus_size_t rp_size; /* size of config window */ 327 bus_space_handle_t cfg_handle; /* handle of config window */ 328 }; 329 330 #define TEGRA_PCIB_MAX_PORTS 3 331 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 332 struct tegra_pcib_softc { 333 struct ofw_pci_softc ofw_pci; 334 device_t dev; 335 struct pcie_soc *soc; 336 struct mtx mtx; 337 struct resource *pads_mem_res; 338 struct resource *afi_mem_res; 339 struct resource *cfg_mem_res; 340 struct resource *irq_res; 341 struct resource *msi_irq_res; 342 void *intr_cookie; 343 void *msi_intr_cookie; 344 345 struct ofw_pci_range mem_range; 346 struct ofw_pci_range pref_mem_range; 347 struct ofw_pci_range io_range; 348 349 clk_t clk_pex; 350 clk_t clk_afi; 351 clk_t clk_pll_e; 352 clk_t clk_cml; 353 hwreset_t hwreset_pex; 354 hwreset_t hwreset_afi; 355 hwreset_t hwreset_pcie_x; 356 regulator_t regulators[16]; /* Safe maximum */ 357 358 vm_offset_t msi_page; /* VA of MSI page */ 359 bus_addr_t cfg_base_addr; /* base address of config */ 360 bus_size_t cfg_cur_offs; /* currently mapped window */ 361 bus_space_handle_t cfg_handle; /* handle of config window */ 362 bus_space_tag_t bus_tag; /* tag of config window */ 363 int lanes_cfg; 364 int num_ports; 365 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 366 struct tegra_pcib_irqsrc *isrcs; 367 }; 368 369 static int 370 tegra_pcib_maxslots(device_t dev) 371 { 372 return (16); 373 } 374 375 static int 376 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 377 { 378 struct tegra_pcib_softc *sc; 379 u_int irq; 380 381 sc = device_get_softc(bus); 382 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 383 device_printf(bus, "route pin %d for device %d.%d to %u\n", 384 pin, pci_get_slot(dev), pci_get_function(dev), 385 irq); 386 387 return (irq); 388 } 389 390 static int 391 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 392 u_int func, u_int reg) 393 { 394 bus_size_t offs; 395 int flags, rv; 396 397 offs = sc->cfg_base_addr; 398 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 399 PCI_CFG_EXT_REG(reg); 400 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 401 return (0); 402 if (sc->cfg_handle != 0) 403 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 404 405 #if defined(BUS_SPACE_MAP_NONPOSTED) 406 flags = BUS_SPACE_MAP_NONPOSTED; 407 #else 408 flags = 0; 409 #endif 410 rv = bus_space_map(sc->bus_tag, offs, 0x800, flags, &sc->cfg_handle); 411 if (rv != 0) 412 device_printf(sc->dev, "Cannot map config space\n"); 413 else 414 sc->cfg_cur_offs = offs; 415 return (rv); 416 } 417 418 static uint32_t 419 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 420 u_int reg, int bytes) 421 { 422 struct tegra_pcib_softc *sc; 423 bus_space_handle_t hndl; 424 uint32_t off; 425 uint32_t val; 426 int rv, i; 427 428 sc = device_get_softc(dev); 429 if (bus == 0) { 430 if (func != 0) 431 return (0xFFFFFFFF); 432 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 433 if ((sc->ports[i] != NULL) && 434 (sc->ports[i]->port_idx == slot)) { 435 hndl = sc->ports[i]->cfg_handle; 436 off = reg & 0xFFF; 437 break; 438 } 439 } 440 if (i >= TEGRA_PCIB_MAX_PORTS) 441 return (0xFFFFFFFF); 442 } else { 443 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 444 if (rv != 0) 445 return (0xFFFFFFFF); 446 hndl = sc->cfg_handle; 447 off = PCI_CFG_BASE_REG(reg); 448 } 449 450 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 451 switch (bytes) { 452 case 4: 453 break; 454 case 2: 455 if (off & 3) 456 val >>= 16; 457 val &= 0xffff; 458 break; 459 case 1: 460 val >>= ((off & 3) << 3); 461 val &= 0xff; 462 break; 463 } 464 return val; 465 } 466 467 static void 468 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 469 u_int reg, uint32_t val, int bytes) 470 { 471 struct tegra_pcib_softc *sc; 472 bus_space_handle_t hndl; 473 uint32_t off; 474 uint32_t val2; 475 int rv, i; 476 477 sc = device_get_softc(dev); 478 if (bus == 0) { 479 if (func != 0) 480 return; 481 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 482 if ((sc->ports[i] != NULL) && 483 (sc->ports[i]->port_idx == slot)) { 484 hndl = sc->ports[i]->cfg_handle; 485 off = reg & 0xFFF; 486 break; 487 } 488 } 489 if (i >= TEGRA_PCIB_MAX_PORTS) 490 return; 491 } else { 492 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 493 if (rv != 0) 494 return; 495 hndl = sc->cfg_handle; 496 off = PCI_CFG_BASE_REG(reg); 497 } 498 499 switch (bytes) { 500 case 4: 501 bus_space_write_4(sc->bus_tag, hndl, off, val); 502 break; 503 case 2: 504 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 505 val2 &= ~(0xffff << ((off & 3) << 3)); 506 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 507 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 508 break; 509 case 1: 510 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 511 val2 &= ~(0xff << ((off & 3) << 3)); 512 val2 |= ((val & 0xff) << ((off & 3) << 3)); 513 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 514 break; 515 } 516 } 517 518 static int tegra_pci_intr(void *arg) 519 { 520 struct tegra_pcib_softc *sc = arg; 521 uint32_t code, signature; 522 523 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 524 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 525 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 526 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 527 return(FILTER_STRAY); 528 529 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 530 return (FILTER_HANDLED); 531 } 532 533 /* ----------------------------------------------------------------------- 534 * 535 * PCI MSI interface 536 */ 537 static int 538 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 539 int *irqs) 540 { 541 phandle_t msi_parent; 542 543 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 544 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 545 NULL); 546 */ 547 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 548 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 549 irqs)); 550 } 551 552 static int 553 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 554 { 555 phandle_t msi_parent; 556 557 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 558 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 559 NULL); 560 */ 561 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 562 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 563 } 564 565 static int 566 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 567 uint32_t *data) 568 { 569 phandle_t msi_parent; 570 571 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 572 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 573 NULL); 574 */ 575 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 576 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 577 } 578 579 #ifdef TEGRA_PCIB_MSI_ENABLE 580 581 /* -------------------------------------------------------------------------- 582 * 583 * Interrupts 584 * 585 */ 586 587 static inline void 588 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 589 struct tegra_pcib_irqsrc *tgi, uint32_t val) 590 { 591 uint32_t reg; 592 int offs, bit; 593 594 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 595 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 596 597 if (val != 0) 598 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 599 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 600 if (val != 0) 601 reg |= bit; 602 else 603 reg &= ~bit; 604 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 605 } 606 607 static int 608 tegra_pcib_msi_intr(void *arg) 609 { 610 u_int irq, i, bit, reg; 611 struct tegra_pcib_softc *sc; 612 struct trapframe *tf; 613 struct tegra_pcib_irqsrc *tgi; 614 615 sc = (struct tegra_pcib_softc *)arg; 616 tf = curthread->td_intr_frame; 617 618 for (i = 0; i < AFI_MSI_REGS; i++) { 619 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 620 /* Handle one vector. */ 621 while (reg != 0) { 622 bit = ffs(reg) - 1; 623 /* Send EOI */ 624 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 625 irq = i * AFI_MSI_INTR_IN_REG + bit; 626 tgi = &sc->isrcs[irq]; 627 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 628 /* Disable stray. */ 629 tegra_pcib_isrc_mask(sc, tgi, 0); 630 device_printf(sc->dev, 631 "Stray irq %u disabled\n", irq); 632 } 633 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 634 } 635 } 636 return (FILTER_HANDLED); 637 } 638 639 static int 640 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 641 { 642 int error; 643 uint32_t irq; 644 const char *name; 645 646 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 647 M_WAITOK | M_ZERO); 648 649 name = device_get_nameunit(sc->dev); 650 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 651 sc->isrcs[irq].irq = irq; 652 error = intr_isrc_register(&sc->isrcs[irq].isrc, 653 sc->dev, 0, "%s,%u", name, irq); 654 if (error != 0) 655 return (error); /* XXX deregister ISRCs */ 656 } 657 if (intr_msi_register(sc->dev, 658 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 659 return (ENXIO); 660 661 return (0); 662 } 663 664 static int 665 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 666 { 667 668 /* 669 * There has not been established any procedure yet 670 * how to detach PIC from living system correctly. 671 */ 672 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 673 return (EBUSY); 674 } 675 676 static void 677 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 678 { 679 struct tegra_pcib_softc *sc; 680 struct tegra_pcib_irqsrc *tgi; 681 682 sc = device_get_softc(dev); 683 tgi = (struct tegra_pcib_irqsrc *)isrc; 684 tegra_pcib_isrc_mask(sc, tgi, 0); 685 } 686 687 static void 688 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 689 { 690 struct tegra_pcib_softc *sc; 691 struct tegra_pcib_irqsrc *tgi; 692 693 sc = device_get_softc(dev); 694 tgi = (struct tegra_pcib_irqsrc *)isrc; 695 tegra_pcib_isrc_mask(sc, tgi, 1); 696 } 697 698 /* MSI interrupts are edge trigered -> do nothing */ 699 static void 700 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 701 { 702 } 703 704 static void 705 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 706 { 707 } 708 709 static void 710 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 711 { 712 } 713 714 static int 715 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 716 struct resource *res, struct intr_map_data *data) 717 { 718 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 719 return (ENOTSUP); 720 721 if (isrc->isrc_handlers == 0) 722 tegra_pcib_msi_enable_intr(dev, isrc); 723 724 return (0); 725 } 726 727 static int 728 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 729 struct resource *res, struct intr_map_data *data) 730 { 731 struct tegra_pcib_softc *sc; 732 struct tegra_pcib_irqsrc *tgi; 733 734 sc = device_get_softc(dev); 735 tgi = (struct tegra_pcib_irqsrc *)isrc; 736 737 if (isrc->isrc_handlers == 0) 738 tegra_pcib_isrc_mask(sc, tgi, 0); 739 return (0); 740 } 741 742 static int 743 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 744 device_t *pic, struct intr_irqsrc **srcs) 745 { 746 struct tegra_pcib_softc *sc; 747 int i, irq, end_irq; 748 bool found; 749 750 KASSERT(powerof2(count), ("%s: bad count", __func__)); 751 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 752 753 sc = device_get_softc(dev); 754 mtx_lock(&sc->mtx); 755 756 found = false; 757 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { 758 /* Start on an aligned interrupt */ 759 if ((irq & (maxcount - 1)) != 0) 760 continue; 761 762 /* Assume we found a valid range until shown otherwise */ 763 found = true; 764 765 /* Check this range is valid */ 766 for (end_irq = irq; end_irq < irq + count; end_irq++) { 767 /* This is already used */ 768 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == 769 TEGRA_FLAG_MSI_USED) { 770 found = false; 771 break; 772 } 773 } 774 775 if (found) 776 break; 777 } 778 779 /* Not enough interrupts were found */ 780 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 781 mtx_unlock(&sc->mtx); 782 return (ENXIO); 783 } 784 785 for (i = 0; i < count; i++) { 786 /* Mark the interrupt as used */ 787 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 788 } 789 mtx_unlock(&sc->mtx); 790 791 for (i = 0; i < count; i++) 792 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 793 *pic = device_get_parent(dev); 794 return (0); 795 } 796 797 static int 798 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 799 struct intr_irqsrc **isrc) 800 { 801 struct tegra_pcib_softc *sc; 802 struct tegra_pcib_irqsrc *ti; 803 int i; 804 805 sc = device_get_softc(dev); 806 mtx_lock(&sc->mtx); 807 for (i = 0; i < count; i++) { 808 ti = (struct tegra_pcib_irqsrc *)isrc[i]; 809 810 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 811 ("%s: Trying to release an unused MSI-X interrupt", 812 __func__)); 813 814 ti->flags &= ~TEGRA_FLAG_MSI_USED; 815 } 816 mtx_unlock(&sc->mtx); 817 return (0); 818 } 819 820 static int 821 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 822 uint64_t *addr, uint32_t *data) 823 { 824 struct tegra_pcib_softc *sc = device_get_softc(dev); 825 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 826 827 *addr = vtophys(sc->msi_page); 828 *data = ti->irq; 829 return (0); 830 } 831 #endif 832 833 /* ------------------------------------------------------------------- */ 834 static bus_size_t 835 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 836 { 837 switch (port) { 838 case 0: 839 return (AFI_PEX0_CTRL); 840 case 1: 841 return (AFI_PEX1_CTRL); 842 case 2: 843 return (AFI_PEX2_CTRL); 844 default: 845 panic("invalid port number: %d\n", port); 846 } 847 } 848 849 static int 850 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 851 { 852 int i, rv; 853 854 rv = hwreset_assert(sc->hwreset_pcie_x); 855 if (rv != 0) { 856 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 857 return (rv); 858 } 859 rv = hwreset_assert(sc->hwreset_afi); 860 if (rv != 0) { 861 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 862 return (rv); 863 } 864 rv = hwreset_assert(sc->hwreset_pex); 865 if (rv != 0) { 866 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 867 return (rv); 868 } 869 870 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 871 872 /* Regulators. */ 873 for (i = 0; i < nitems(sc->regulators); i++) { 874 if (sc->regulators[i] == NULL) 875 continue; 876 rv = regulator_enable(sc->regulators[i]); 877 if (rv != 0) { 878 device_printf(sc->dev, 879 "Cannot enable '%s' regulator\n", 880 sc->soc->regulator_names[i]); 881 return (rv); 882 } 883 } 884 885 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 886 sc->clk_pex, sc->hwreset_pex); 887 if (rv != 0) { 888 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 889 return (rv); 890 } 891 892 rv = hwreset_deassert(sc->hwreset_afi); 893 if (rv != 0) { 894 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 895 return (rv); 896 } 897 898 rv = clk_enable(sc->clk_afi); 899 if (rv != 0) { 900 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 901 return (rv); 902 } 903 if (sc->soc->cml_clk) { 904 rv = clk_enable(sc->clk_cml); 905 if (rv != 0) { 906 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 907 return (rv); 908 } 909 } 910 rv = clk_enable(sc->clk_pll_e); 911 if (rv != 0) { 912 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 913 return (rv); 914 } 915 916 return (0); 917 } 918 919 static struct tegra_pcib_port * 920 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 921 { 922 struct tegra_pcib_port *port; 923 uint32_t tmp[5]; 924 char tmpstr[6]; 925 int rv; 926 927 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 928 929 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 930 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 931 strcmp(tmpstr, "ok") == 0) 932 port->enabled = 1; 933 else 934 port->enabled = 0; 935 936 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 937 if (rv != sizeof(tmp)) { 938 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 939 rv); 940 goto fail; 941 } 942 port->rp_base_addr = tmp[2]; 943 port->rp_size = tmp[4]; 944 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 945 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 946 device_printf(sc->dev, "Invalid port index: %d\n", 947 port->port_idx); 948 goto fail; 949 } 950 /* XXX - TODO: 951 * Implement proper function for parsing pci "reg" property: 952 * - it have PCI bus format 953 * - its relative to matching "assigned-addresses" 954 */ 955 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 956 if (rv != sizeof(tmp)) { 957 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 958 goto fail; 959 } 960 port->rp_base_addr += tmp[2]; 961 962 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 963 sizeof(port->num_lanes)); 964 if (rv != sizeof(port->num_lanes)) { 965 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 966 rv); 967 goto fail; 968 } 969 if (port->num_lanes > 4) { 970 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 971 port->num_lanes); 972 goto fail; 973 } 974 975 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 976 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 977 978 /* Phy. */ 979 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 980 if (rv != 0) { 981 device_printf(sc->dev, 982 "Cannot get 'pcie-0' phy for port %d\n", 983 port->port_idx); 984 goto fail; 985 } 986 987 return (port); 988 fail: 989 free(port, M_DEVBUF); 990 return (NULL); 991 } 992 993 static int 994 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 995 { 996 phandle_t child; 997 struct tegra_pcib_port *port; 998 int i, rv; 999 1000 /* Regulators. */ 1001 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 1002 if (i >= nitems(sc->regulators)) { 1003 device_printf(sc->dev, 1004 "Too many regulators present in DT.\n"); 1005 return (EOVERFLOW); 1006 } 1007 rv = regulator_get_by_ofw_property(sc->dev, 0, 1008 sc->soc->regulator_names[i], sc->regulators + i); 1009 if (rv != 0) { 1010 device_printf(sc->dev, 1011 "Cannot get '%s' regulator\n", 1012 sc->soc->regulator_names[i]); 1013 return (ENXIO); 1014 } 1015 } 1016 1017 /* Resets. */ 1018 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1019 if (rv != 0) { 1020 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1021 return (ENXIO); 1022 } 1023 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1024 if (rv != 0) { 1025 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1026 return (ENXIO); 1027 } 1028 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1029 if (rv != 0) { 1030 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1031 return (ENXIO); 1032 } 1033 1034 /* Clocks. */ 1035 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1036 if (rv != 0) { 1037 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1038 return (ENXIO); 1039 } 1040 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1041 if (rv != 0) { 1042 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1043 return (ENXIO); 1044 } 1045 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1046 if (rv != 0) { 1047 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1048 return (ENXIO); 1049 } 1050 if (sc->soc->cml_clk) { 1051 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1052 if (rv != 0) { 1053 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1054 return (ENXIO); 1055 } 1056 } 1057 1058 /* Ports */ 1059 sc->num_ports = 0; 1060 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1061 port = tegra_pcib_parse_port(sc, child); 1062 if (port == NULL) { 1063 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1064 return (ENXIO); 1065 } 1066 sc->ports[sc->num_ports++] = port; 1067 } 1068 1069 return (0); 1070 } 1071 1072 static int 1073 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1074 struct ofw_pci_range *ranges, int nranges) 1075 { 1076 int i; 1077 1078 for (i = 2; i < nranges; i++) { 1079 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1080 OFW_PCI_PHYS_HI_SPACE_IO) { 1081 if (sc->io_range.size != 0) { 1082 device_printf(sc->dev, 1083 "Duplicated IO range found in DT\n"); 1084 return (ENXIO); 1085 } 1086 sc->io_range = ranges[i]; 1087 } 1088 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1089 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1090 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1091 if (sc->pref_mem_range.size != 0) { 1092 device_printf(sc->dev, 1093 "Duplicated memory range found " 1094 "in DT\n"); 1095 return (ENXIO); 1096 } 1097 sc->pref_mem_range = ranges[i]; 1098 } else { 1099 if (sc->mem_range.size != 0) { 1100 device_printf(sc->dev, 1101 "Duplicated memory range found " 1102 "in DT\n"); 1103 return (ENXIO); 1104 } 1105 sc->mem_range = ranges[i]; 1106 } 1107 } 1108 } 1109 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1110 || (sc->pref_mem_range.size == 0)) { 1111 device_printf(sc->dev, 1112 " Not all required ranges are found in DT\n"); 1113 return (ENXIO); 1114 } 1115 return (0); 1116 } 1117 1118 /* 1119 * Hardware config. 1120 */ 1121 static int 1122 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1123 struct tegra_pcib_port *port) 1124 { 1125 uint32_t reg; 1126 int i; 1127 1128 /* Setup link detection. */ 1129 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1130 RP_PRIV_MISC, 4); 1131 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1132 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1133 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1134 RP_PRIV_MISC, reg, 4); 1135 1136 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1137 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1138 RP_VEND_XP, 4); 1139 if (reg & RP_VEND_XP_DL_UP) 1140 break; 1141 DELAY(1); 1142 } 1143 if (i <= 0) 1144 return (ETIMEDOUT); 1145 1146 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1147 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1148 RP_LINK_CONTROL_STATUS, 4); 1149 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1150 break; 1151 1152 DELAY(1); 1153 } 1154 if (i <= 0) 1155 return (ETIMEDOUT); 1156 return (0); 1157 } 1158 1159 static void 1160 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1161 { 1162 struct tegra_pcib_port *port; 1163 uint32_t reg; 1164 int rv; 1165 1166 port = sc->ports[port_num]; 1167 1168 /* Put port to reset. */ 1169 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1170 reg &= ~AFI_PEX_CTRL_RST_L; 1171 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1172 AFI_RD4(sc, port->afi_pex_ctrl); 1173 DELAY(10); 1174 1175 /* Enable clocks. */ 1176 reg |= AFI_PEX_CTRL_REFCLK_EN; 1177 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1178 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1179 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1180 AFI_RD4(sc, port->afi_pex_ctrl); 1181 DELAY(100); 1182 1183 /* Release reset. */ 1184 reg |= AFI_PEX_CTRL_RST_L; 1185 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1186 1187 if (sc->soc->pca_enable) { 1188 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1189 RP_VEND_CTL2, 4); 1190 reg |= RP_VEND_CTL2_PCA_ENABLE; 1191 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1192 RP_VEND_CTL2, reg, 4); 1193 } 1194 1195 rv = tegra_pcib_wait_for_link(sc, port); 1196 if (bootverbose) 1197 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1198 port->port_idx, port->num_lanes, 1199 port->num_lanes > 1 ? "s": "", 1200 rv == 0 ? "up": "down"); 1201 } 1202 1203 static void 1204 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1205 { 1206 struct tegra_pcib_port *port; 1207 uint32_t reg; 1208 1209 port = sc->ports[port_num]; 1210 1211 /* Put port to reset. */ 1212 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1213 reg &= ~AFI_PEX_CTRL_RST_L; 1214 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1215 AFI_RD4(sc, port->afi_pex_ctrl); 1216 DELAY(10); 1217 1218 /* Disable clocks. */ 1219 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1220 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1221 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1222 1223 if (bootverbose) 1224 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1225 port->port_idx, port->num_lanes, 1226 port->num_lanes > 1 ? "s": ""); 1227 } 1228 1229 static void 1230 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1231 uint64_t fpci, uint32_t size, int is_memory) 1232 { 1233 uint32_t fpci_reg; 1234 uint32_t axi_reg; 1235 uint32_t size_reg; 1236 1237 axi_reg = axi & ~0xFFF; 1238 size_reg = size >> 12; 1239 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1240 fpci_reg |= is_memory ? 0x1 : 0x0; 1241 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1242 AFI_WR4(sc, bars[bar].size, size_reg); 1243 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1244 } 1245 1246 static int 1247 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1248 { 1249 int rv; 1250 int i; 1251 uint32_t reg; 1252 1253 rv = tegra_pcib_enable_fdt_resources(sc); 1254 if (rv != 0) { 1255 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1256 return (rv); 1257 } 1258 1259 /* Enable PLLE control. */ 1260 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1261 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1262 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1263 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1264 1265 /* Set bias pad. */ 1266 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1267 1268 /* Configure mode and ports. */ 1269 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1270 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1271 if (sc->lanes_cfg == 0x14) { 1272 if (bootverbose) 1273 device_printf(sc->dev, 1274 "Using x1,x4 configuration\n"); 1275 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1276 } else if (sc->lanes_cfg == 0x12) { 1277 if (bootverbose) 1278 device_printf(sc->dev, 1279 "Using x1,x2 configuration\n"); 1280 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1281 } else { 1282 device_printf(sc->dev, 1283 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1284 } 1285 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1286 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1287 if ((sc->ports[i] != NULL)) 1288 reg &= 1289 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1290 } 1291 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1292 1293 /* Enable Gen2 support. */ 1294 reg = AFI_RD4(sc, AFI_FUSE); 1295 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1296 AFI_WR4(sc, AFI_FUSE, reg); 1297 1298 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1299 if (sc->ports[i] != NULL) { 1300 rv = phy_enable(sc->ports[i]->phy); 1301 if (rv != 0) { 1302 device_printf(sc->dev, 1303 "Cannot enable phy for port %d\n", 1304 sc->ports[i]->port_idx); 1305 return (rv); 1306 } 1307 } 1308 } 1309 1310 /* Configure PCIe reference clock */ 1311 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0); 1312 if (sc->num_ports > 2) 1313 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1); 1314 1315 rv = hwreset_deassert(sc->hwreset_pcie_x); 1316 if (rv != 0) { 1317 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1318 return (rv); 1319 } 1320 1321 /* Enable config space. */ 1322 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1323 reg |= AFI_CONFIGURATION_EN_FPCI; 1324 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1325 1326 /* Enable AFI errors. */ 1327 reg = 0; 1328 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1329 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1330 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1331 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1342 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1343 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1344 1345 /* Enable INT, disable MSI. */ 1346 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1347 1348 /* Mask all FPCI errors. */ 1349 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1350 1351 /* Setup AFI translation windows. */ 1352 /* BAR 0 - type 1 extended configuration. */ 1353 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1354 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1355 1356 /* BAR 1 - downstream I/O. */ 1357 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1358 sc->io_range.size, 0); 1359 1360 /* BAR 2 - downstream prefetchable memory 1:1. */ 1361 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1362 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1363 1364 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1365 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1366 sc->mem_range.host, sc->mem_range.size, 1); 1367 1368 /* BAR 3-8 clear. */ 1369 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1370 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1371 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1372 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1373 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1374 1375 /* MSI BAR - clear. */ 1376 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1377 return(0); 1378 } 1379 1380 #ifdef TEGRA_PCIB_MSI_ENABLE 1381 static int 1382 tegra_pcib_attach_msi(device_t dev) 1383 { 1384 struct tegra_pcib_softc *sc; 1385 uint32_t reg; 1386 int i, rv; 1387 1388 sc = device_get_softc(dev); 1389 1390 sc->msi_page = (uintptr_t)kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0, 1391 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1392 1393 /* MSI BAR */ 1394 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1395 PAGE_SIZE, 0); 1396 1397 /* Disable and clear all interrupts. */ 1398 for (i = 0; i < AFI_MSI_REGS; i++) { 1399 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1400 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1401 } 1402 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1403 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1404 if (rv != 0) { 1405 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1406 rv = ENXIO; 1407 goto out; 1408 } 1409 1410 if (tegra_pcib_msi_attach(sc) != 0) { 1411 device_printf(dev, "WARNING: unable to attach PIC\n"); 1412 tegra_pcib_msi_detach(sc); 1413 goto out; 1414 } 1415 1416 /* Unmask MSI interrupt. */ 1417 reg = AFI_RD4(sc, AFI_INTR_MASK); 1418 reg |= AFI_INTR_MASK_MSI_MASK; 1419 AFI_WR4(sc, AFI_INTR_MASK, reg); 1420 1421 out: 1422 return (rv); 1423 } 1424 #endif 1425 1426 static int 1427 tegra_pcib_probe(device_t dev) 1428 { 1429 if (!ofw_bus_status_okay(dev)) 1430 return (ENXIO); 1431 1432 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1433 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1434 return (BUS_PROBE_DEFAULT); 1435 } 1436 return (ENXIO); 1437 } 1438 1439 static int 1440 tegra_pcib_attach(device_t dev) 1441 { 1442 struct tegra_pcib_softc *sc; 1443 phandle_t node; 1444 int rv; 1445 int rid; 1446 struct tegra_pcib_port *port; 1447 int i; 1448 1449 sc = device_get_softc(dev); 1450 sc->dev = dev; 1451 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1452 1453 node = ofw_bus_get_node(dev); 1454 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev, 1455 compat_data)->ocd_data; 1456 1457 rv = tegra_pcib_parse_fdt_resources(sc, node); 1458 if (rv != 0) { 1459 device_printf(dev, "Cannot get FDT resources\n"); 1460 return (rv); 1461 } 1462 1463 /* Allocate bus_space resources. */ 1464 rid = 0; 1465 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1466 RF_ACTIVE); 1467 if (sc->pads_mem_res == NULL) { 1468 device_printf(dev, "Cannot allocate PADS register\n"); 1469 rv = ENXIO; 1470 goto out; 1471 } 1472 /* 1473 * XXX - FIXME 1474 * tag for config space is not filled when RF_ALLOCATED flag is used. 1475 */ 1476 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1477 1478 rid = 1; 1479 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1480 RF_ACTIVE); 1481 if (sc->afi_mem_res == NULL) { 1482 device_printf(dev, "Cannot allocate AFI register\n"); 1483 rv = ENXIO; 1484 goto out; 1485 } 1486 1487 rid = 2; 1488 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1489 RF_ALLOCATED); 1490 if (sc->cfg_mem_res == NULL) { 1491 device_printf(dev, "Cannot allocate config space memory\n"); 1492 rv = ENXIO; 1493 goto out; 1494 } 1495 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1496 1497 /* Map RP slots */ 1498 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1499 if (sc->ports[i] == NULL) 1500 continue; 1501 port = sc->ports[i]; 1502 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1503 port->rp_size, 0, &port->cfg_handle); 1504 if (rv != 0) { 1505 device_printf(sc->dev, "Cannot allocate memory for " 1506 "port: %d\n", i); 1507 rv = ENXIO; 1508 goto out; 1509 } 1510 } 1511 1512 /* 1513 * Get PCI interrupt 1514 */ 1515 rid = 0; 1516 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1517 RF_ACTIVE | RF_SHAREABLE); 1518 if (sc->irq_res == NULL) { 1519 device_printf(dev, "Cannot allocate IRQ resources\n"); 1520 rv = ENXIO; 1521 goto out; 1522 } 1523 1524 rid = 1; 1525 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1526 RF_ACTIVE); 1527 if (sc->irq_res == NULL) { 1528 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1529 rv = ENXIO; 1530 goto out; 1531 } 1532 1533 sc->ofw_pci.sc_range_mask = 0x3; 1534 rv = ofw_pcib_init(dev); 1535 if (rv != 0) 1536 goto out; 1537 1538 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1539 sc->ofw_pci.sc_nrange); 1540 if (rv != 0) 1541 goto out; 1542 1543 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1544 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1545 device_printf(dev, "cannot setup interrupt handler\n"); 1546 rv = ENXIO; 1547 goto out; 1548 } 1549 1550 /* 1551 * Enable PCIE device. 1552 */ 1553 rv = tegra_pcib_enable(sc); 1554 if (rv != 0) 1555 goto out; 1556 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1557 if (sc->ports[i] == NULL) 1558 continue; 1559 if (sc->ports[i]->enabled) 1560 tegra_pcib_port_enable(sc, i); 1561 else 1562 tegra_pcib_port_disable(sc, i); 1563 } 1564 1565 #ifdef TEGRA_PCIB_MSI_ENABLE 1566 rv = tegra_pcib_attach_msi(dev); 1567 if (rv != 0) 1568 goto out; 1569 #endif 1570 device_add_child(dev, "pci", -1); 1571 1572 return (bus_generic_attach(dev)); 1573 1574 out: 1575 1576 return (rv); 1577 } 1578 1579 static device_method_t tegra_pcib_methods[] = { 1580 /* Device interface */ 1581 DEVMETHOD(device_probe, tegra_pcib_probe), 1582 DEVMETHOD(device_attach, tegra_pcib_attach), 1583 1584 /* Bus interface */ 1585 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1586 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1587 1588 /* pcib interface */ 1589 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1590 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1591 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1592 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1593 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1594 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1595 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1596 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 1597 1598 #ifdef TEGRA_PCIB_MSI_ENABLE 1599 /* MSI/MSI-X */ 1600 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1601 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1602 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1603 1604 /* Interrupt controller interface */ 1605 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1606 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1607 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1608 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1609 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1610 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1611 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1612 #endif 1613 1614 /* OFW bus interface */ 1615 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1616 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1617 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1618 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1619 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1620 1621 DEVMETHOD_END 1622 }; 1623 1624 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1625 sizeof(struct tegra_pcib_softc), ofw_pcib_driver); 1626 DRIVER_MODULE(tegra_pcib, simplebus, tegra_pcib_driver, NULL, NULL); 1627