1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * Nvidia Integrated PCI/PCI-Express controller driver. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/devmap.h> 36 #include <sys/proc.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 43 #include <machine/intr.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_extern.h> 47 #include <vm/vm_kern.h> 48 #include <vm/pmap.h> 49 50 #include <dev/clk/clk.h> 51 #include <dev/hwreset/hwreset.h> 52 #include <dev/phy/phy.h> 53 #include <dev/regulator/regulator.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 #include <dev/ofw/ofwpci.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 62 #include <machine/resource.h> 63 #include <machine/bus.h> 64 65 #include <arm/nvidia/tegra_pmc.h> 66 67 #include "ofw_bus_if.h" 68 #include "msi_if.h" 69 #include "pcib_if.h" 70 #include "pic_if.h" 71 72 #define AFI_AXI_BAR0_SZ 0x000 73 #define AFI_AXI_BAR1_SZ 0x004 74 #define AFI_AXI_BAR2_SZ 0x008 75 #define AFI_AXI_BAR3_SZ 0x00c 76 #define AFI_AXI_BAR4_SZ 0x010 77 #define AFI_AXI_BAR5_SZ 0x014 78 #define AFI_AXI_BAR0_START 0x018 79 #define AFI_AXI_BAR1_START 0x01c 80 #define AFI_AXI_BAR2_START 0x020 81 #define AFI_AXI_BAR3_START 0x024 82 #define AFI_AXI_BAR4_START 0x028 83 #define AFI_AXI_BAR5_START 0x02c 84 #define AFI_FPCI_BAR0 0x030 85 #define AFI_FPCI_BAR1 0x034 86 #define AFI_FPCI_BAR2 0x038 87 #define AFI_FPCI_BAR3 0x03c 88 #define AFI_FPCI_BAR4 0x040 89 #define AFI_FPCI_BAR5 0x044 90 #define AFI_MSI_BAR_SZ 0x060 91 #define AFI_MSI_FPCI_BAR_ST 0x064 92 #define AFI_MSI_AXI_BAR_ST 0x068 93 #define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 94 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 95 #define AFI_MSI_INTR_IN_REG 32 96 #define AFI_MSI_REGS 8 97 98 #define AFI_CONFIGURATION 0x0ac 99 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 100 101 #define AFI_FPCI_ERROR_MASKS 0x0b0 102 #define AFI_INTR_MASK 0x0b4 103 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 104 #define AFI_INTR_MASK_INT_MASK (1 << 0) 105 106 #define AFI_INTR_CODE 0x0b8 107 #define AFI_INTR_CODE_MASK 0xf 108 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 109 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 110 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 111 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 112 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 113 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 114 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 115 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 116 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 117 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 118 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 119 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 120 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 121 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 122 123 #define AFI_INTR_SIGNATURE 0x0bc 124 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 125 #define AFI_SM_INTR_ENABLE 0x0c4 126 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 127 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 128 #define AFI_SM_INTR_HOTPLUG (1 << 12) 129 #define AFI_SM_INTR_PME (1 << 11) 130 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 131 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 132 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 133 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 134 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 135 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 136 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 137 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 138 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 139 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 140 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 141 142 #define AFI_AFI_INTR_ENABLE 0x0c8 143 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 144 145 #define AFI_PCIE_CONFIG 0x0f8 146 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 147 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 148 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 149 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 151 152 #define AFI_FUSE 0x104 153 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 154 155 #define AFI_PEX0_CTRL 0x110 156 #define AFI_PEX1_CTRL 0x118 157 #define AFI_PEX2_CTRL 0x128 158 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 159 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 160 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 161 #define AFI_PEX_CTRL_RST_L (1 << 0) 162 163 #define AFI_AXI_BAR6_SZ 0x134 164 #define AFI_AXI_BAR7_SZ 0x138 165 #define AFI_AXI_BAR8_SZ 0x13c 166 #define AFI_AXI_BAR6_START 0x140 167 #define AFI_AXI_BAR7_START 0x144 168 #define AFI_AXI_BAR8_START 0x148 169 #define AFI_FPCI_BAR6 0x14c 170 #define AFI_FPCI_BAR7 0x150 171 #define AFI_FPCI_BAR8 0x154 172 #define AFI_PLLE_CONTROL 0x160 173 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 174 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 175 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 176 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 177 178 #define AFI_PEXBIAS_CTRL 0x168 179 180 /* Configuration space */ 181 #define RP_VEND_XP 0x0F00 182 #define RP_VEND_XP_DL_UP (1 << 30) 183 184 #define RP_VEND_CTL2 0x0fa8 185 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7) 186 187 #define RP_PRIV_MISC 0x0FE0 188 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 189 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 190 191 #define RP_LINK_CONTROL_STATUS 0x0090 192 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 193 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 194 195 /* PADS space */ 196 #define PADS_REFCLK_CFG0 0x000c8 197 #define PADS_REFCLK_CFG1 0x000cc 198 199 200 /* Wait 50 ms (per port) for link. */ 201 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000 202 203 /* FPCI Address space */ 204 #define FPCI_MAP_IO 0xFDFC000000ULL 205 #define FPCI_MAP_TYPE0_CONFIG 0xFDFC000000ULL 206 #define FPCI_MAP_TYPE1_CONFIG 0xFDFF000000ULL 207 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xFE00000000ULL 208 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xFE10000000ULL 209 210 #define TEGRA_PCIB_MSI_ENABLE 211 212 #define DEBUG 213 #ifdef DEBUG 214 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 215 #else 216 #define debugf(fmt, args...) 217 #endif 218 219 /* 220 * Configuration space format: 221 * [27:24] extended register 222 * [23:16] bus 223 * [15:11] slot (device) 224 * [10: 8] function 225 * [ 7: 0] register 226 */ 227 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 228 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 229 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 230 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 231 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 232 233 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v)) 234 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 235 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 236 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 237 238 static struct { 239 bus_size_t axi_start; 240 bus_size_t fpci_start; 241 bus_size_t size; 242 } bars[] = { 243 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 244 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 245 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 246 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 247 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 248 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 249 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 250 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 251 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 252 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 253 }; 254 255 256 struct pcie_soc { 257 char **regulator_names; 258 bool cml_clk; 259 bool pca_enable; 260 uint32_t pads_refclk_cfg0; 261 uint32_t pads_refclk_cfg1; 262 }; 263 264 /* Tegra 124 config. */ 265 static char *tegra124_reg_names[] = { 266 "avddio-pex-supply", 267 "dvddio-pex-supply", 268 "avdd-pex-pll-supply", 269 "hvdd-pex-supply", 270 "hvdd-pex-pll-e-supply", 271 "vddio-pex-ctl-supply", 272 "avdd-pll-erefe-supply", 273 NULL 274 }; 275 276 static struct pcie_soc tegra124_soc = { 277 .regulator_names = tegra124_reg_names, 278 .cml_clk = true, 279 .pca_enable = false, 280 .pads_refclk_cfg0 = 0x44ac44ac, 281 }; 282 283 /* Tegra 210 config. */ 284 static char *tegra210_reg_names[] = { 285 "avdd-pll-uerefe-supply", 286 "hvddio-pex-supply", 287 "dvddio-pex-supply", 288 "dvdd-pex-pll-supply", 289 "hvdd-pex-pll-e-supply", 290 "vddio-pex-ctl-supply", 291 NULL 292 }; 293 294 static struct pcie_soc tegra210_soc = { 295 .regulator_names = tegra210_reg_names, 296 .cml_clk = true, 297 .pca_enable = true, 298 .pads_refclk_cfg0 = 0x90b890b8, 299 }; 300 301 /* Compatible devices. */ 302 static struct ofw_compat_data compat_data[] = { 303 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc}, 304 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc}, 305 {NULL, 0}, 306 }; 307 308 #define TEGRA_FLAG_MSI_USED 0x0001 309 struct tegra_pcib_irqsrc { 310 struct intr_irqsrc isrc; 311 u_int irq; 312 u_int flags; 313 }; 314 315 struct tegra_pcib_port { 316 int enabled; 317 int port_idx; /* chip port index */ 318 int num_lanes; /* number of lanes */ 319 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 320 phy_t phy; /* port phy */ 321 322 /* Config space properties. */ 323 bus_addr_t rp_base_addr; /* PA of config window */ 324 bus_size_t rp_size; /* size of config window */ 325 bus_space_handle_t cfg_handle; /* handle of config window */ 326 }; 327 328 #define TEGRA_PCIB_MAX_PORTS 3 329 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 330 struct tegra_pcib_softc { 331 struct ofw_pci_softc ofw_pci; 332 device_t dev; 333 struct pcie_soc *soc; 334 struct mtx mtx; 335 struct resource *pads_mem_res; 336 struct resource *afi_mem_res; 337 struct resource *cfg_mem_res; 338 struct resource *irq_res; 339 struct resource *msi_irq_res; 340 void *intr_cookie; 341 void *msi_intr_cookie; 342 343 struct ofw_pci_range mem_range; 344 struct ofw_pci_range pref_mem_range; 345 struct ofw_pci_range io_range; 346 347 clk_t clk_pex; 348 clk_t clk_afi; 349 clk_t clk_pll_e; 350 clk_t clk_cml; 351 hwreset_t hwreset_pex; 352 hwreset_t hwreset_afi; 353 hwreset_t hwreset_pcie_x; 354 regulator_t regulators[16]; /* Safe maximum */ 355 356 vm_offset_t msi_page; /* VA of MSI page */ 357 bus_addr_t cfg_base_addr; /* base address of config */ 358 bus_size_t cfg_cur_offs; /* currently mapped window */ 359 bus_space_handle_t cfg_handle; /* handle of config window */ 360 bus_space_tag_t bus_tag; /* tag of config window */ 361 int lanes_cfg; 362 int num_ports; 363 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 364 struct tegra_pcib_irqsrc *isrcs; 365 }; 366 367 static int 368 tegra_pcib_maxslots(device_t dev) 369 { 370 return (16); 371 } 372 373 static int 374 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 375 { 376 struct tegra_pcib_softc *sc; 377 u_int irq; 378 379 sc = device_get_softc(bus); 380 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 381 device_printf(bus, "route pin %d for device %d.%d to %u\n", 382 pin, pci_get_slot(dev), pci_get_function(dev), 383 irq); 384 385 return (irq); 386 } 387 388 static int 389 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 390 u_int func, u_int reg) 391 { 392 bus_size_t offs; 393 int flags, rv; 394 395 offs = sc->cfg_base_addr; 396 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 397 PCI_CFG_EXT_REG(reg); 398 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 399 return (0); 400 if (sc->cfg_handle != 0) 401 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 402 403 #if defined(BUS_SPACE_MAP_NONPOSTED) 404 flags = BUS_SPACE_MAP_NONPOSTED; 405 #else 406 flags = 0; 407 #endif 408 rv = bus_space_map(sc->bus_tag, offs, 0x800, flags, &sc->cfg_handle); 409 if (rv != 0) 410 device_printf(sc->dev, "Cannot map config space\n"); 411 else 412 sc->cfg_cur_offs = offs; 413 return (rv); 414 } 415 416 static uint32_t 417 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 418 u_int reg, int bytes) 419 { 420 struct tegra_pcib_softc *sc; 421 bus_space_handle_t hndl; 422 uint32_t off; 423 uint32_t val; 424 int rv, i; 425 426 sc = device_get_softc(dev); 427 if (bus == 0) { 428 if (func != 0) 429 return (0xFFFFFFFF); 430 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 431 if ((sc->ports[i] != NULL) && 432 (sc->ports[i]->port_idx == slot)) { 433 hndl = sc->ports[i]->cfg_handle; 434 off = reg & 0xFFF; 435 break; 436 } 437 } 438 if (i >= TEGRA_PCIB_MAX_PORTS) 439 return (0xFFFFFFFF); 440 } else { 441 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 442 if (rv != 0) 443 return (0xFFFFFFFF); 444 hndl = sc->cfg_handle; 445 off = PCI_CFG_BASE_REG(reg); 446 } 447 448 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 449 switch (bytes) { 450 case 4: 451 break; 452 case 2: 453 if (off & 3) 454 val >>= 16; 455 val &= 0xffff; 456 break; 457 case 1: 458 val >>= ((off & 3) << 3); 459 val &= 0xff; 460 break; 461 } 462 return val; 463 } 464 465 static void 466 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 467 u_int reg, uint32_t val, int bytes) 468 { 469 struct tegra_pcib_softc *sc; 470 bus_space_handle_t hndl; 471 uint32_t off; 472 uint32_t val2; 473 int rv, i; 474 475 sc = device_get_softc(dev); 476 if (bus == 0) { 477 if (func != 0) 478 return; 479 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 480 if ((sc->ports[i] != NULL) && 481 (sc->ports[i]->port_idx == slot)) { 482 hndl = sc->ports[i]->cfg_handle; 483 off = reg & 0xFFF; 484 break; 485 } 486 } 487 if (i >= TEGRA_PCIB_MAX_PORTS) 488 return; 489 } else { 490 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 491 if (rv != 0) 492 return; 493 hndl = sc->cfg_handle; 494 off = PCI_CFG_BASE_REG(reg); 495 } 496 497 switch (bytes) { 498 case 4: 499 bus_space_write_4(sc->bus_tag, hndl, off, val); 500 break; 501 case 2: 502 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 503 val2 &= ~(0xffff << ((off & 3) << 3)); 504 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 505 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 506 break; 507 case 1: 508 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 509 val2 &= ~(0xff << ((off & 3) << 3)); 510 val2 |= ((val & 0xff) << ((off & 3) << 3)); 511 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 512 break; 513 } 514 } 515 516 static int tegra_pci_intr(void *arg) 517 { 518 struct tegra_pcib_softc *sc = arg; 519 uint32_t code, signature; 520 521 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 522 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 523 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 524 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 525 return(FILTER_STRAY); 526 527 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 528 return (FILTER_HANDLED); 529 } 530 531 /* ----------------------------------------------------------------------- 532 * 533 * PCI MSI interface 534 */ 535 static int 536 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 537 int *irqs) 538 { 539 phandle_t msi_parent; 540 541 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 542 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 543 NULL); 544 */ 545 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 546 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 547 irqs)); 548 } 549 550 static int 551 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 552 { 553 phandle_t msi_parent; 554 555 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 556 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 557 NULL); 558 */ 559 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 560 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 561 } 562 563 static int 564 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 565 uint32_t *data) 566 { 567 phandle_t msi_parent; 568 569 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 570 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 571 NULL); 572 */ 573 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 574 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 575 } 576 577 #ifdef TEGRA_PCIB_MSI_ENABLE 578 579 /* -------------------------------------------------------------------------- 580 * 581 * Interrupts 582 * 583 */ 584 585 static inline void 586 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 587 struct tegra_pcib_irqsrc *tgi, uint32_t val) 588 { 589 uint32_t reg; 590 int offs, bit; 591 592 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 593 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 594 595 if (val != 0) 596 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 597 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 598 if (val != 0) 599 reg |= bit; 600 else 601 reg &= ~bit; 602 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 603 } 604 605 static int 606 tegra_pcib_msi_intr(void *arg) 607 { 608 u_int irq, i, bit, reg; 609 struct tegra_pcib_softc *sc; 610 struct trapframe *tf; 611 struct tegra_pcib_irqsrc *tgi; 612 613 sc = (struct tegra_pcib_softc *)arg; 614 tf = curthread->td_intr_frame; 615 616 for (i = 0; i < AFI_MSI_REGS; i++) { 617 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 618 /* Handle one vector. */ 619 while (reg != 0) { 620 bit = ffs(reg) - 1; 621 /* Send EOI */ 622 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 623 irq = i * AFI_MSI_INTR_IN_REG + bit; 624 tgi = &sc->isrcs[irq]; 625 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 626 /* Disable stray. */ 627 tegra_pcib_isrc_mask(sc, tgi, 0); 628 device_printf(sc->dev, 629 "Stray irq %u disabled\n", irq); 630 } 631 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 632 } 633 } 634 return (FILTER_HANDLED); 635 } 636 637 static int 638 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 639 { 640 int error; 641 uint32_t irq; 642 const char *name; 643 644 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 645 M_WAITOK | M_ZERO); 646 647 name = device_get_nameunit(sc->dev); 648 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 649 sc->isrcs[irq].irq = irq; 650 error = intr_isrc_register(&sc->isrcs[irq].isrc, 651 sc->dev, 0, "%s,%u", name, irq); 652 if (error != 0) 653 return (error); /* XXX deregister ISRCs */ 654 } 655 if (intr_msi_register(sc->dev, 656 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 657 return (ENXIO); 658 659 return (0); 660 } 661 662 static int 663 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 664 { 665 666 /* 667 * There has not been established any procedure yet 668 * how to detach PIC from living system correctly. 669 */ 670 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 671 return (EBUSY); 672 } 673 674 static void 675 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 676 { 677 struct tegra_pcib_softc *sc; 678 struct tegra_pcib_irqsrc *tgi; 679 680 sc = device_get_softc(dev); 681 tgi = (struct tegra_pcib_irqsrc *)isrc; 682 tegra_pcib_isrc_mask(sc, tgi, 0); 683 } 684 685 static void 686 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 687 { 688 struct tegra_pcib_softc *sc; 689 struct tegra_pcib_irqsrc *tgi; 690 691 sc = device_get_softc(dev); 692 tgi = (struct tegra_pcib_irqsrc *)isrc; 693 tegra_pcib_isrc_mask(sc, tgi, 1); 694 } 695 696 /* MSI interrupts are edge trigered -> do nothing */ 697 static void 698 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 699 { 700 } 701 702 static void 703 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 704 { 705 } 706 707 static void 708 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 709 { 710 } 711 712 static int 713 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 714 struct resource *res, struct intr_map_data *data) 715 { 716 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 717 return (ENOTSUP); 718 719 if (isrc->isrc_handlers == 0) 720 tegra_pcib_msi_enable_intr(dev, isrc); 721 722 return (0); 723 } 724 725 static int 726 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 727 struct resource *res, struct intr_map_data *data) 728 { 729 struct tegra_pcib_softc *sc; 730 struct tegra_pcib_irqsrc *tgi; 731 732 sc = device_get_softc(dev); 733 tgi = (struct tegra_pcib_irqsrc *)isrc; 734 735 if (isrc->isrc_handlers == 0) 736 tegra_pcib_isrc_mask(sc, tgi, 0); 737 return (0); 738 } 739 740 static int 741 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 742 device_t *pic, struct intr_irqsrc **srcs) 743 { 744 struct tegra_pcib_softc *sc; 745 int i, irq, end_irq; 746 bool found; 747 748 KASSERT(powerof2(count), ("%s: bad count", __func__)); 749 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 750 751 sc = device_get_softc(dev); 752 mtx_lock(&sc->mtx); 753 754 found = false; 755 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { 756 /* Start on an aligned interrupt */ 757 if ((irq & (maxcount - 1)) != 0) 758 continue; 759 760 /* Assume we found a valid range until shown otherwise */ 761 found = true; 762 763 /* Check this range is valid */ 764 for (end_irq = irq; end_irq < irq + count; end_irq++) { 765 /* This is already used */ 766 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == 767 TEGRA_FLAG_MSI_USED) { 768 found = false; 769 break; 770 } 771 } 772 773 if (found) 774 break; 775 } 776 777 /* Not enough interrupts were found */ 778 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 779 mtx_unlock(&sc->mtx); 780 return (ENXIO); 781 } 782 783 for (i = 0; i < count; i++) { 784 /* Mark the interrupt as used */ 785 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 786 } 787 mtx_unlock(&sc->mtx); 788 789 for (i = 0; i < count; i++) 790 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 791 *pic = device_get_parent(dev); 792 return (0); 793 } 794 795 static int 796 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 797 struct intr_irqsrc **isrc) 798 { 799 struct tegra_pcib_softc *sc; 800 struct tegra_pcib_irqsrc *ti; 801 int i; 802 803 sc = device_get_softc(dev); 804 mtx_lock(&sc->mtx); 805 for (i = 0; i < count; i++) { 806 ti = (struct tegra_pcib_irqsrc *)isrc[i]; 807 808 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 809 ("%s: Trying to release an unused MSI-X interrupt", 810 __func__)); 811 812 ti->flags &= ~TEGRA_FLAG_MSI_USED; 813 } 814 mtx_unlock(&sc->mtx); 815 return (0); 816 } 817 818 static int 819 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 820 uint64_t *addr, uint32_t *data) 821 { 822 struct tegra_pcib_softc *sc = device_get_softc(dev); 823 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 824 825 *addr = vtophys(sc->msi_page); 826 *data = ti->irq; 827 return (0); 828 } 829 #endif 830 831 /* ------------------------------------------------------------------- */ 832 static bus_size_t 833 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 834 { 835 switch (port) { 836 case 0: 837 return (AFI_PEX0_CTRL); 838 case 1: 839 return (AFI_PEX1_CTRL); 840 case 2: 841 return (AFI_PEX2_CTRL); 842 default: 843 panic("invalid port number: %d\n", port); 844 } 845 } 846 847 static int 848 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 849 { 850 int i, rv; 851 852 rv = hwreset_assert(sc->hwreset_pcie_x); 853 if (rv != 0) { 854 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 855 return (rv); 856 } 857 rv = hwreset_assert(sc->hwreset_afi); 858 if (rv != 0) { 859 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 860 return (rv); 861 } 862 rv = hwreset_assert(sc->hwreset_pex); 863 if (rv != 0) { 864 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 865 return (rv); 866 } 867 868 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 869 870 /* Regulators. */ 871 for (i = 0; i < nitems(sc->regulators); i++) { 872 if (sc->regulators[i] == NULL) 873 continue; 874 rv = regulator_enable(sc->regulators[i]); 875 if (rv != 0) { 876 device_printf(sc->dev, 877 "Cannot enable '%s' regulator\n", 878 sc->soc->regulator_names[i]); 879 return (rv); 880 } 881 } 882 883 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 884 sc->clk_pex, sc->hwreset_pex); 885 if (rv != 0) { 886 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 887 return (rv); 888 } 889 890 rv = hwreset_deassert(sc->hwreset_afi); 891 if (rv != 0) { 892 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 893 return (rv); 894 } 895 896 rv = clk_enable(sc->clk_afi); 897 if (rv != 0) { 898 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 899 return (rv); 900 } 901 if (sc->soc->cml_clk) { 902 rv = clk_enable(sc->clk_cml); 903 if (rv != 0) { 904 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 905 return (rv); 906 } 907 } 908 rv = clk_enable(sc->clk_pll_e); 909 if (rv != 0) { 910 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 911 return (rv); 912 } 913 914 return (0); 915 } 916 917 static struct tegra_pcib_port * 918 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 919 { 920 struct tegra_pcib_port *port; 921 uint32_t tmp[5]; 922 char tmpstr[6]; 923 int rv; 924 925 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 926 927 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 928 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 929 strcmp(tmpstr, "ok") == 0) 930 port->enabled = 1; 931 else 932 port->enabled = 0; 933 934 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 935 if (rv != sizeof(tmp)) { 936 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 937 rv); 938 goto fail; 939 } 940 port->rp_base_addr = tmp[2]; 941 port->rp_size = tmp[4]; 942 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 943 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 944 device_printf(sc->dev, "Invalid port index: %d\n", 945 port->port_idx); 946 goto fail; 947 } 948 /* XXX - TODO: 949 * Implement proper function for parsing pci "reg" property: 950 * - it have PCI bus format 951 * - its relative to matching "assigned-addresses" 952 */ 953 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 954 if (rv != sizeof(tmp)) { 955 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 956 goto fail; 957 } 958 port->rp_base_addr += tmp[2]; 959 960 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 961 sizeof(port->num_lanes)); 962 if (rv != sizeof(port->num_lanes)) { 963 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 964 rv); 965 goto fail; 966 } 967 if (port->num_lanes > 4) { 968 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 969 port->num_lanes); 970 goto fail; 971 } 972 973 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 974 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 975 976 /* Phy. */ 977 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 978 if (rv != 0) { 979 device_printf(sc->dev, 980 "Cannot get 'pcie-0' phy for port %d\n", 981 port->port_idx); 982 goto fail; 983 } 984 985 return (port); 986 fail: 987 free(port, M_DEVBUF); 988 return (NULL); 989 } 990 991 static int 992 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 993 { 994 phandle_t child; 995 struct tegra_pcib_port *port; 996 int i, rv; 997 998 /* Regulators. */ 999 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 1000 if (i >= nitems(sc->regulators)) { 1001 device_printf(sc->dev, 1002 "Too many regulators present in DT.\n"); 1003 return (EOVERFLOW); 1004 } 1005 rv = regulator_get_by_ofw_property(sc->dev, 0, 1006 sc->soc->regulator_names[i], sc->regulators + i); 1007 if (rv != 0) { 1008 device_printf(sc->dev, 1009 "Cannot get '%s' regulator\n", 1010 sc->soc->regulator_names[i]); 1011 return (ENXIO); 1012 } 1013 } 1014 1015 /* Resets. */ 1016 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1017 if (rv != 0) { 1018 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1019 return (ENXIO); 1020 } 1021 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1022 if (rv != 0) { 1023 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1024 return (ENXIO); 1025 } 1026 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1027 if (rv != 0) { 1028 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1029 return (ENXIO); 1030 } 1031 1032 /* Clocks. */ 1033 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1034 if (rv != 0) { 1035 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1036 return (ENXIO); 1037 } 1038 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1039 if (rv != 0) { 1040 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1041 return (ENXIO); 1042 } 1043 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1044 if (rv != 0) { 1045 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1046 return (ENXIO); 1047 } 1048 if (sc->soc->cml_clk) { 1049 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1050 if (rv != 0) { 1051 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1052 return (ENXIO); 1053 } 1054 } 1055 1056 /* Ports */ 1057 sc->num_ports = 0; 1058 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1059 port = tegra_pcib_parse_port(sc, child); 1060 if (port == NULL) { 1061 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1062 return (ENXIO); 1063 } 1064 sc->ports[sc->num_ports++] = port; 1065 } 1066 1067 return (0); 1068 } 1069 1070 static int 1071 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1072 struct ofw_pci_range *ranges, int nranges) 1073 { 1074 int i; 1075 1076 for (i = 2; i < nranges; i++) { 1077 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1078 OFW_PCI_PHYS_HI_SPACE_IO) { 1079 if (sc->io_range.size != 0) { 1080 device_printf(sc->dev, 1081 "Duplicated IO range found in DT\n"); 1082 return (ENXIO); 1083 } 1084 sc->io_range = ranges[i]; 1085 } 1086 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1087 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1088 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1089 if (sc->pref_mem_range.size != 0) { 1090 device_printf(sc->dev, 1091 "Duplicated memory range found " 1092 "in DT\n"); 1093 return (ENXIO); 1094 } 1095 sc->pref_mem_range = ranges[i]; 1096 } else { 1097 if (sc->mem_range.size != 0) { 1098 device_printf(sc->dev, 1099 "Duplicated memory range found " 1100 "in DT\n"); 1101 return (ENXIO); 1102 } 1103 sc->mem_range = ranges[i]; 1104 } 1105 } 1106 } 1107 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1108 || (sc->pref_mem_range.size == 0)) { 1109 device_printf(sc->dev, 1110 " Not all required ranges are found in DT\n"); 1111 return (ENXIO); 1112 } 1113 return (0); 1114 } 1115 1116 /* 1117 * Hardware config. 1118 */ 1119 static int 1120 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1121 struct tegra_pcib_port *port) 1122 { 1123 uint32_t reg; 1124 int i; 1125 1126 /* Setup link detection. */ 1127 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1128 RP_PRIV_MISC, 4); 1129 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1130 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1131 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1132 RP_PRIV_MISC, reg, 4); 1133 1134 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1135 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1136 RP_VEND_XP, 4); 1137 if (reg & RP_VEND_XP_DL_UP) 1138 break; 1139 DELAY(1); 1140 } 1141 if (i <= 0) 1142 return (ETIMEDOUT); 1143 1144 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1145 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1146 RP_LINK_CONTROL_STATUS, 4); 1147 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1148 break; 1149 1150 DELAY(1); 1151 } 1152 if (i <= 0) 1153 return (ETIMEDOUT); 1154 return (0); 1155 } 1156 1157 static void 1158 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1159 { 1160 struct tegra_pcib_port *port; 1161 uint32_t reg; 1162 int rv; 1163 1164 port = sc->ports[port_num]; 1165 1166 /* Put port to reset. */ 1167 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1168 reg &= ~AFI_PEX_CTRL_RST_L; 1169 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1170 AFI_RD4(sc, port->afi_pex_ctrl); 1171 DELAY(10); 1172 1173 /* Enable clocks. */ 1174 reg |= AFI_PEX_CTRL_REFCLK_EN; 1175 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1176 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1177 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1178 AFI_RD4(sc, port->afi_pex_ctrl); 1179 DELAY(100); 1180 1181 /* Release reset. */ 1182 reg |= AFI_PEX_CTRL_RST_L; 1183 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1184 1185 if (sc->soc->pca_enable) { 1186 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1187 RP_VEND_CTL2, 4); 1188 reg |= RP_VEND_CTL2_PCA_ENABLE; 1189 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1190 RP_VEND_CTL2, reg, 4); 1191 } 1192 1193 rv = tegra_pcib_wait_for_link(sc, port); 1194 if (bootverbose) 1195 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1196 port->port_idx, port->num_lanes, 1197 port->num_lanes > 1 ? "s": "", 1198 rv == 0 ? "up": "down"); 1199 } 1200 1201 static void 1202 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1203 { 1204 struct tegra_pcib_port *port; 1205 uint32_t reg; 1206 1207 port = sc->ports[port_num]; 1208 1209 /* Put port to reset. */ 1210 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1211 reg &= ~AFI_PEX_CTRL_RST_L; 1212 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1213 AFI_RD4(sc, port->afi_pex_ctrl); 1214 DELAY(10); 1215 1216 /* Disable clocks. */ 1217 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1218 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1219 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1220 1221 if (bootverbose) 1222 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1223 port->port_idx, port->num_lanes, 1224 port->num_lanes > 1 ? "s": ""); 1225 } 1226 1227 static void 1228 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1229 uint64_t fpci, uint32_t size, int is_memory) 1230 { 1231 uint32_t fpci_reg; 1232 uint32_t axi_reg; 1233 uint32_t size_reg; 1234 1235 axi_reg = axi & ~0xFFF; 1236 size_reg = size >> 12; 1237 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1238 fpci_reg |= is_memory ? 0x1 : 0x0; 1239 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1240 AFI_WR4(sc, bars[bar].size, size_reg); 1241 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1242 } 1243 1244 static int 1245 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1246 { 1247 int rv; 1248 int i; 1249 uint32_t reg; 1250 1251 rv = tegra_pcib_enable_fdt_resources(sc); 1252 if (rv != 0) { 1253 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1254 return (rv); 1255 } 1256 1257 /* Enable PLLE control. */ 1258 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1259 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1260 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1261 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1262 1263 /* Set bias pad. */ 1264 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1265 1266 /* Configure mode and ports. */ 1267 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1268 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1269 if (sc->lanes_cfg == 0x14) { 1270 if (bootverbose) 1271 device_printf(sc->dev, 1272 "Using x1,x4 configuration\n"); 1273 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1274 } else if (sc->lanes_cfg == 0x12) { 1275 if (bootverbose) 1276 device_printf(sc->dev, 1277 "Using x1,x2 configuration\n"); 1278 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1279 } else { 1280 device_printf(sc->dev, 1281 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1282 } 1283 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1284 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1285 if ((sc->ports[i] != NULL)) 1286 reg &= 1287 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1288 } 1289 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1290 1291 /* Enable Gen2 support. */ 1292 reg = AFI_RD4(sc, AFI_FUSE); 1293 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1294 AFI_WR4(sc, AFI_FUSE, reg); 1295 1296 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1297 if (sc->ports[i] != NULL) { 1298 rv = phy_enable(sc->ports[i]->phy); 1299 if (rv != 0) { 1300 device_printf(sc->dev, 1301 "Cannot enable phy for port %d\n", 1302 sc->ports[i]->port_idx); 1303 return (rv); 1304 } 1305 } 1306 } 1307 1308 /* Configure PCIe reference clock */ 1309 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0); 1310 if (sc->num_ports > 2) 1311 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1); 1312 1313 rv = hwreset_deassert(sc->hwreset_pcie_x); 1314 if (rv != 0) { 1315 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1316 return (rv); 1317 } 1318 1319 /* Enable config space. */ 1320 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1321 reg |= AFI_CONFIGURATION_EN_FPCI; 1322 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1323 1324 /* Enable AFI errors. */ 1325 reg = 0; 1326 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1327 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1328 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1329 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1330 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1331 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1340 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1341 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1342 1343 /* Enable INT, disable MSI. */ 1344 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1345 1346 /* Mask all FPCI errors. */ 1347 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1348 1349 /* Setup AFI translation windows. */ 1350 /* BAR 0 - type 1 extended configuration. */ 1351 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1352 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1353 1354 /* BAR 1 - downstream I/O. */ 1355 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1356 sc->io_range.size, 0); 1357 1358 /* BAR 2 - downstream prefetchable memory 1:1. */ 1359 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1360 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1361 1362 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1363 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1364 sc->mem_range.host, sc->mem_range.size, 1); 1365 1366 /* BAR 3-8 clear. */ 1367 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1368 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1369 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1370 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1371 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1372 1373 /* MSI BAR - clear. */ 1374 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1375 return(0); 1376 } 1377 1378 #ifdef TEGRA_PCIB_MSI_ENABLE 1379 static int 1380 tegra_pcib_attach_msi(device_t dev) 1381 { 1382 struct tegra_pcib_softc *sc; 1383 uint32_t reg; 1384 int i, rv; 1385 1386 sc = device_get_softc(dev); 1387 1388 sc->msi_page = (uintptr_t)kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0, 1389 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1390 1391 /* MSI BAR */ 1392 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1393 PAGE_SIZE, 0); 1394 1395 /* Disable and clear all interrupts. */ 1396 for (i = 0; i < AFI_MSI_REGS; i++) { 1397 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1398 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1399 } 1400 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1401 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1402 if (rv != 0) { 1403 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1404 rv = ENXIO; 1405 goto out; 1406 } 1407 1408 if (tegra_pcib_msi_attach(sc) != 0) { 1409 device_printf(dev, "WARNING: unable to attach PIC\n"); 1410 tegra_pcib_msi_detach(sc); 1411 goto out; 1412 } 1413 1414 /* Unmask MSI interrupt. */ 1415 reg = AFI_RD4(sc, AFI_INTR_MASK); 1416 reg |= AFI_INTR_MASK_MSI_MASK; 1417 AFI_WR4(sc, AFI_INTR_MASK, reg); 1418 1419 out: 1420 return (rv); 1421 } 1422 #endif 1423 1424 static int 1425 tegra_pcib_probe(device_t dev) 1426 { 1427 if (!ofw_bus_status_okay(dev)) 1428 return (ENXIO); 1429 1430 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1431 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1432 return (BUS_PROBE_DEFAULT); 1433 } 1434 return (ENXIO); 1435 } 1436 1437 static int 1438 tegra_pcib_attach(device_t dev) 1439 { 1440 struct tegra_pcib_softc *sc; 1441 phandle_t node; 1442 int rv; 1443 int rid; 1444 struct tegra_pcib_port *port; 1445 int i; 1446 1447 sc = device_get_softc(dev); 1448 sc->dev = dev; 1449 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1450 1451 node = ofw_bus_get_node(dev); 1452 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev, 1453 compat_data)->ocd_data; 1454 1455 rv = tegra_pcib_parse_fdt_resources(sc, node); 1456 if (rv != 0) { 1457 device_printf(dev, "Cannot get FDT resources\n"); 1458 return (rv); 1459 } 1460 1461 /* Allocate bus_space resources. */ 1462 rid = 0; 1463 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1464 RF_ACTIVE); 1465 if (sc->pads_mem_res == NULL) { 1466 device_printf(dev, "Cannot allocate PADS register\n"); 1467 rv = ENXIO; 1468 goto out; 1469 } 1470 /* 1471 * XXX - FIXME 1472 * tag for config space is not filled when RF_ALLOCATED flag is used. 1473 */ 1474 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1475 1476 rid = 1; 1477 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1478 RF_ACTIVE); 1479 if (sc->afi_mem_res == NULL) { 1480 device_printf(dev, "Cannot allocate AFI register\n"); 1481 rv = ENXIO; 1482 goto out; 1483 } 1484 1485 rid = 2; 1486 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1487 RF_ALLOCATED); 1488 if (sc->cfg_mem_res == NULL) { 1489 device_printf(dev, "Cannot allocate config space memory\n"); 1490 rv = ENXIO; 1491 goto out; 1492 } 1493 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1494 1495 /* Map RP slots */ 1496 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1497 if (sc->ports[i] == NULL) 1498 continue; 1499 port = sc->ports[i]; 1500 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1501 port->rp_size, 0, &port->cfg_handle); 1502 if (rv != 0) { 1503 device_printf(sc->dev, "Cannot allocate memory for " 1504 "port: %d\n", i); 1505 rv = ENXIO; 1506 goto out; 1507 } 1508 } 1509 1510 /* 1511 * Get PCI interrupt 1512 */ 1513 rid = 0; 1514 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1515 RF_ACTIVE | RF_SHAREABLE); 1516 if (sc->irq_res == NULL) { 1517 device_printf(dev, "Cannot allocate IRQ resources\n"); 1518 rv = ENXIO; 1519 goto out; 1520 } 1521 1522 rid = 1; 1523 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1524 RF_ACTIVE); 1525 if (sc->irq_res == NULL) { 1526 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1527 rv = ENXIO; 1528 goto out; 1529 } 1530 1531 sc->ofw_pci.sc_range_mask = 0x3; 1532 rv = ofw_pcib_init(dev); 1533 if (rv != 0) 1534 goto out; 1535 1536 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1537 sc->ofw_pci.sc_nrange); 1538 if (rv != 0) 1539 goto out; 1540 1541 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1542 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1543 device_printf(dev, "cannot setup interrupt handler\n"); 1544 rv = ENXIO; 1545 goto out; 1546 } 1547 1548 /* 1549 * Enable PCIE device. 1550 */ 1551 rv = tegra_pcib_enable(sc); 1552 if (rv != 0) 1553 goto out; 1554 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1555 if (sc->ports[i] == NULL) 1556 continue; 1557 if (sc->ports[i]->enabled) 1558 tegra_pcib_port_enable(sc, i); 1559 else 1560 tegra_pcib_port_disable(sc, i); 1561 } 1562 1563 #ifdef TEGRA_PCIB_MSI_ENABLE 1564 rv = tegra_pcib_attach_msi(dev); 1565 if (rv != 0) 1566 goto out; 1567 #endif 1568 device_add_child(dev, "pci", DEVICE_UNIT_ANY); 1569 1570 return (bus_generic_attach(dev)); 1571 1572 out: 1573 1574 return (rv); 1575 } 1576 1577 static device_method_t tegra_pcib_methods[] = { 1578 /* Device interface */ 1579 DEVMETHOD(device_probe, tegra_pcib_probe), 1580 DEVMETHOD(device_attach, tegra_pcib_attach), 1581 1582 /* Bus interface */ 1583 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1584 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1585 1586 /* pcib interface */ 1587 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1588 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1589 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1590 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1591 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1592 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1593 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1594 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 1595 1596 #ifdef TEGRA_PCIB_MSI_ENABLE 1597 /* MSI/MSI-X */ 1598 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1599 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1600 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1601 1602 /* Interrupt controller interface */ 1603 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1604 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1605 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1606 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1607 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1608 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1609 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1610 #endif 1611 1612 /* OFW bus interface */ 1613 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1614 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1615 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1616 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1617 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1618 1619 DEVMETHOD_END 1620 }; 1621 1622 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1623 sizeof(struct tegra_pcib_softc), ofw_pcib_driver); 1624 DRIVER_MODULE(tegra_pcib, simplebus, tegra_pcib_driver, NULL, NULL); 1625