1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/intr.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 #include <vm/pmap.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/phy/phy.h> 55 #include <dev/extres/regulator/regulator.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #include <dev/ofw/ofw_pci.h> 59 #include <dev/ofw/ofwpci.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcib_private.h> 63 64 #include <machine/resource.h> 65 #include <machine/bus.h> 66 67 #include <arm/nvidia/tegra_pmc.h> 68 69 #include "ofw_bus_if.h" 70 #include "msi_if.h" 71 #include "pcib_if.h" 72 #include "pic_if.h" 73 74 #define AFI_AXI_BAR0_SZ 0x000 75 #define AFI_AXI_BAR1_SZ 0x004 76 #define AFI_AXI_BAR2_SZ 0x008 77 #define AFI_AXI_BAR3_SZ 0x00c 78 #define AFI_AXI_BAR4_SZ 0x010 79 #define AFI_AXI_BAR5_SZ 0x014 80 #define AFI_AXI_BAR0_START 0x018 81 #define AFI_AXI_BAR1_START 0x01c 82 #define AFI_AXI_BAR2_START 0x020 83 #define AFI_AXI_BAR3_START 0x024 84 #define AFI_AXI_BAR4_START 0x028 85 #define AFI_AXI_BAR5_START 0x02c 86 #define AFI_FPCI_BAR0 0x030 87 #define AFI_FPCI_BAR1 0x034 88 #define AFI_FPCI_BAR2 0x038 89 #define AFI_FPCI_BAR3 0x03c 90 #define AFI_FPCI_BAR4 0x040 91 #define AFI_FPCI_BAR5 0x044 92 #define AFI_MSI_BAR_SZ 0x060 93 #define AFI_MSI_FPCI_BAR_ST 0x064 94 #define AFI_MSI_AXI_BAR_ST 0x068 95 #define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 96 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 97 #define AFI_MSI_INTR_IN_REG 32 98 #define AFI_MSI_REGS 8 99 100 #define AFI_CONFIGURATION 0x0ac 101 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 102 103 #define AFI_FPCI_ERROR_MASKS 0x0b0 104 #define AFI_INTR_MASK 0x0b4 105 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 106 #define AFI_INTR_MASK_INT_MASK (1 << 0) 107 108 #define AFI_INTR_CODE 0x0b8 109 #define AFI_INTR_CODE_MASK 0xf 110 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 111 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 112 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 113 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 114 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 115 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 116 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 117 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 118 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 119 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 120 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 121 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 122 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 123 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 124 125 #define AFI_INTR_SIGNATURE 0x0bc 126 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 127 #define AFI_SM_INTR_ENABLE 0x0c4 128 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 129 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 130 #define AFI_SM_INTR_HOTPLUG (1 << 12) 131 #define AFI_SM_INTR_PME (1 << 11) 132 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 133 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 134 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 135 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 136 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 137 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 138 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 139 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 140 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 141 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 142 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 143 144 #define AFI_AFI_INTR_ENABLE 0x0c8 145 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 146 147 #define AFI_PCIE_CONFIG 0x0f8 148 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 149 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 153 154 #define AFI_FUSE 0x104 155 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 156 157 #define AFI_PEX0_CTRL 0x110 158 #define AFI_PEX1_CTRL 0x118 159 #define AFI_PEX2_CTRL 0x128 160 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 161 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 162 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 163 #define AFI_PEX_CTRL_RST_L (1 << 0) 164 165 #define AFI_AXI_BAR6_SZ 0x134 166 #define AFI_AXI_BAR7_SZ 0x138 167 #define AFI_AXI_BAR8_SZ 0x13c 168 #define AFI_AXI_BAR6_START 0x140 169 #define AFI_AXI_BAR7_START 0x144 170 #define AFI_AXI_BAR8_START 0x148 171 #define AFI_FPCI_BAR6 0x14c 172 #define AFI_FPCI_BAR7 0x150 173 #define AFI_FPCI_BAR8 0x154 174 #define AFI_PLLE_CONTROL 0x160 175 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 176 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 177 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 178 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 179 180 #define AFI_PEXBIAS_CTRL 0x168 181 182 /* FPCI Address space */ 183 #define FPCI_MAP_IO 0xfdfc000000ULL 184 #define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 185 #define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 186 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 187 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 188 189 /* Configuration space */ 190 #define RP_VEND_XP 0x00000F00 191 #define RP_VEND_XP_DL_UP (1 << 30) 192 193 #define RP_PRIV_MISC 0x00000FE0 194 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 195 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 196 197 #define RP_LINK_CONTROL_STATUS 0x00000090 198 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 199 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 200 201 /* Wait 50 ms (per port) for link. */ 202 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000 203 204 #define TEGRA_PCIB_MSI_ENABLE 205 206 #define DEBUG 207 #ifdef DEBUG 208 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 209 #else 210 #define debugf(fmt, args...) 211 #endif 212 213 /* 214 * Configuration space format: 215 * [27:24] extended register 216 * [23:16] bus 217 * [15:11] slot (device) 218 * [10: 8] function 219 * [ 7: 0] register 220 */ 221 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 222 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 223 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 224 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 225 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 226 227 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 228 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 229 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 230 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 231 232 static struct { 233 bus_size_t axi_start; 234 bus_size_t fpci_start; 235 bus_size_t size; 236 } bars[] = { 237 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 238 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 239 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 240 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 241 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 242 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 243 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 244 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 245 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 246 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 247 }; 248 249 /* Compatible devices. */ 250 static struct ofw_compat_data compat_data[] = { 251 {"nvidia,tegra124-pcie", 1}, 252 {NULL, 0}, 253 }; 254 255 #define TEGRA_FLAG_MSI_USED 0x0001 256 struct tegra_pcib_irqsrc { 257 struct intr_irqsrc isrc; 258 u_int irq; 259 u_int flags; 260 }; 261 262 struct tegra_pcib_port { 263 int enabled; 264 int port_idx; /* chip port index */ 265 int num_lanes; /* number of lanes */ 266 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 267 phy_t phy; /* port phy */ 268 269 /* Config space properties. */ 270 bus_addr_t rp_base_addr; /* PA of config window */ 271 bus_size_t rp_size; /* size of config window */ 272 bus_space_handle_t cfg_handle; /* handle of config window */ 273 }; 274 275 #define TEGRA_PCIB_MAX_PORTS 3 276 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 277 struct tegra_pcib_softc { 278 struct ofw_pci_softc ofw_pci; 279 device_t dev; 280 struct mtx mtx; 281 struct resource *pads_mem_res; 282 struct resource *afi_mem_res; 283 struct resource *cfg_mem_res; 284 struct resource *irq_res; 285 struct resource *msi_irq_res; 286 void *intr_cookie; 287 void *msi_intr_cookie; 288 289 struct ofw_pci_range mem_range; 290 struct ofw_pci_range pref_mem_range; 291 struct ofw_pci_range io_range; 292 293 clk_t clk_pex; 294 clk_t clk_afi; 295 clk_t clk_pll_e; 296 clk_t clk_cml; 297 hwreset_t hwreset_pex; 298 hwreset_t hwreset_afi; 299 hwreset_t hwreset_pcie_x; 300 regulator_t supply_avddio_pex; 301 regulator_t supply_dvddio_pex; 302 regulator_t supply_avdd_pex_pll; 303 regulator_t supply_hvdd_pex; 304 regulator_t supply_hvdd_pex_pll_e; 305 regulator_t supply_vddio_pex_ctl; 306 regulator_t supply_avdd_pll_erefe; 307 308 vm_offset_t msi_page; /* VA of MSI page */ 309 bus_addr_t cfg_base_addr; /* base address of config */ 310 bus_size_t cfg_cur_offs; /* currently mapped window */ 311 bus_space_handle_t cfg_handle; /* handle of config window */ 312 bus_space_tag_t bus_tag; /* tag of config window */ 313 int lanes_cfg; 314 int num_ports; 315 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 316 struct tegra_pcib_irqsrc *isrcs; 317 }; 318 319 static int 320 tegra_pcib_maxslots(device_t dev) 321 { 322 return (16); 323 } 324 325 static int 326 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 327 { 328 struct tegra_pcib_softc *sc; 329 u_int irq; 330 331 sc = device_get_softc(bus); 332 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 333 device_printf(bus, "route pin %d for device %d.%d to %u\n", 334 pin, pci_get_slot(dev), pci_get_function(dev), 335 irq); 336 337 return (irq); 338 } 339 340 static int 341 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 342 u_int func, u_int reg) 343 { 344 bus_size_t offs; 345 int rv; 346 347 offs = sc->cfg_base_addr; 348 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 349 PCI_CFG_EXT_REG(reg); 350 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 351 return (0); 352 if (sc->cfg_handle != 0) 353 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 354 355 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 356 if (rv != 0) 357 device_printf(sc->dev, "Cannot map config space\n"); 358 else 359 sc->cfg_cur_offs = offs; 360 return (rv); 361 } 362 363 static uint32_t 364 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 365 u_int reg, int bytes) 366 { 367 struct tegra_pcib_softc *sc; 368 bus_space_handle_t hndl; 369 uint32_t off; 370 uint32_t val; 371 int rv, i; 372 373 sc = device_get_softc(dev); 374 if (bus == 0) { 375 if (func != 0) 376 return (0xFFFFFFFF); 377 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 378 if ((sc->ports[i] != NULL) && 379 (sc->ports[i]->port_idx == slot)) { 380 hndl = sc->ports[i]->cfg_handle; 381 off = reg & 0xFFF; 382 break; 383 } 384 } 385 if (i >= TEGRA_PCIB_MAX_PORTS) 386 return (0xFFFFFFFF); 387 } else { 388 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 389 if (rv != 0) 390 return (0xFFFFFFFF); 391 hndl = sc->cfg_handle; 392 off = PCI_CFG_BASE_REG(reg); 393 } 394 395 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 396 switch (bytes) { 397 case 4: 398 break; 399 case 2: 400 if (off & 3) 401 val >>= 16; 402 val &= 0xffff; 403 break; 404 case 1: 405 val >>= ((off & 3) << 3); 406 val &= 0xff; 407 break; 408 } 409 return val; 410 } 411 412 static void 413 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 414 u_int reg, uint32_t val, int bytes) 415 { 416 struct tegra_pcib_softc *sc; 417 bus_space_handle_t hndl; 418 uint32_t off; 419 uint32_t val2; 420 int rv, i; 421 422 sc = device_get_softc(dev); 423 if (bus == 0) { 424 if (func != 0) 425 return; 426 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 427 if ((sc->ports[i] != NULL) && 428 (sc->ports[i]->port_idx == slot)) { 429 hndl = sc->ports[i]->cfg_handle; 430 off = reg & 0xFFF; 431 break; 432 } 433 } 434 if (i >= TEGRA_PCIB_MAX_PORTS) 435 return; 436 } else { 437 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 438 if (rv != 0) 439 return; 440 hndl = sc->cfg_handle; 441 off = PCI_CFG_BASE_REG(reg); 442 } 443 444 switch (bytes) { 445 case 4: 446 bus_space_write_4(sc->bus_tag, hndl, off, val); 447 break; 448 case 2: 449 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 450 val2 &= ~(0xffff << ((off & 3) << 3)); 451 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 452 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 453 break; 454 case 1: 455 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 456 val2 &= ~(0xff << ((off & 3) << 3)); 457 val2 |= ((val & 0xff) << ((off & 3) << 3)); 458 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 459 break; 460 } 461 } 462 463 static int tegra_pci_intr(void *arg) 464 { 465 struct tegra_pcib_softc *sc = arg; 466 uint32_t code, signature; 467 468 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 469 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 470 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 471 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 472 return(FILTER_STRAY); 473 474 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 475 return (FILTER_HANDLED); 476 } 477 478 /* ----------------------------------------------------------------------- 479 * 480 * PCI MSI interface 481 */ 482 static int 483 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 484 int *irqs) 485 { 486 phandle_t msi_parent; 487 488 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 489 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 490 NULL); 491 */ 492 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 493 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 494 irqs)); 495 } 496 497 static int 498 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 499 { 500 phandle_t msi_parent; 501 502 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 503 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 504 NULL); 505 */ 506 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 507 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 508 } 509 510 static int 511 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 512 uint32_t *data) 513 { 514 phandle_t msi_parent; 515 516 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 517 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 518 NULL); 519 */ 520 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 521 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 522 } 523 524 #ifdef TEGRA_PCIB_MSI_ENABLE 525 526 /* -------------------------------------------------------------------------- 527 * 528 * Interrupts 529 * 530 */ 531 532 static inline void 533 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 534 struct tegra_pcib_irqsrc *tgi, uint32_t val) 535 { 536 uint32_t reg; 537 int offs, bit; 538 539 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 540 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 541 542 if (val != 0) 543 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 544 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 545 if (val != 0) 546 reg |= bit; 547 else 548 reg &= ~bit; 549 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 550 } 551 552 static int 553 tegra_pcib_msi_intr(void *arg) 554 { 555 u_int irq, i, bit, reg; 556 struct tegra_pcib_softc *sc; 557 struct trapframe *tf; 558 struct tegra_pcib_irqsrc *tgi; 559 560 sc = (struct tegra_pcib_softc *)arg; 561 tf = curthread->td_intr_frame; 562 563 for (i = 0; i < AFI_MSI_REGS; i++) { 564 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 565 /* Handle one vector. */ 566 while (reg != 0) { 567 bit = ffs(reg) - 1; 568 /* Send EOI */ 569 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 570 irq = i * AFI_MSI_INTR_IN_REG + bit; 571 tgi = &sc->isrcs[irq]; 572 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 573 /* Disable stray. */ 574 tegra_pcib_isrc_mask(sc, tgi, 0); 575 device_printf(sc->dev, 576 "Stray irq %u disabled\n", irq); 577 } 578 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 579 } 580 } 581 return (FILTER_HANDLED); 582 } 583 584 static int 585 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 586 { 587 int error; 588 uint32_t irq; 589 const char *name; 590 591 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 592 M_WAITOK | M_ZERO); 593 594 name = device_get_nameunit(sc->dev); 595 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 596 sc->isrcs[irq].irq = irq; 597 error = intr_isrc_register(&sc->isrcs[irq].isrc, 598 sc->dev, 0, "%s,%u", name, irq); 599 if (error != 0) 600 return (error); /* XXX deregister ISRCs */ 601 } 602 if (intr_msi_register(sc->dev, 603 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 604 return (ENXIO); 605 606 return (0); 607 } 608 609 static int 610 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 611 { 612 613 /* 614 * There has not been established any procedure yet 615 * how to detach PIC from living system correctly. 616 */ 617 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 618 return (EBUSY); 619 } 620 621 static void 622 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 623 { 624 struct tegra_pcib_softc *sc; 625 struct tegra_pcib_irqsrc *tgi; 626 627 sc = device_get_softc(dev); 628 tgi = (struct tegra_pcib_irqsrc *)isrc; 629 tegra_pcib_isrc_mask(sc, tgi, 0); 630 } 631 632 static void 633 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 634 { 635 struct tegra_pcib_softc *sc; 636 struct tegra_pcib_irqsrc *tgi; 637 638 sc = device_get_softc(dev); 639 tgi = (struct tegra_pcib_irqsrc *)isrc; 640 tegra_pcib_isrc_mask(sc, tgi, 1); 641 } 642 643 /* MSI interrupts are edge trigered -> do nothing */ 644 static void 645 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 646 { 647 } 648 649 static void 650 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 651 { 652 } 653 654 static void 655 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 656 { 657 } 658 659 static int 660 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 661 struct resource *res, struct intr_map_data *data) 662 { 663 struct tegra_pcib_softc *sc; 664 struct tegra_pcib_irqsrc *tgi; 665 666 sc = device_get_softc(dev); 667 tgi = (struct tegra_pcib_irqsrc *)isrc; 668 669 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 670 return (ENOTSUP); 671 672 if (isrc->isrc_handlers == 0) 673 tegra_pcib_msi_enable_intr(dev, isrc); 674 675 return (0); 676 } 677 678 static int 679 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 680 struct resource *res, struct intr_map_data *data) 681 { 682 struct tegra_pcib_softc *sc; 683 struct tegra_pcib_irqsrc *tgi; 684 685 sc = device_get_softc(dev); 686 tgi = (struct tegra_pcib_irqsrc *)isrc; 687 688 if (isrc->isrc_handlers == 0) 689 tegra_pcib_isrc_mask(sc, tgi, 0); 690 return (0); 691 } 692 693 static int 694 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 695 device_t *pic, struct intr_irqsrc **srcs) 696 { 697 struct tegra_pcib_softc *sc; 698 int i, irq, end_irq; 699 bool found; 700 701 KASSERT(powerof2(count), ("%s: bad count", __func__)); 702 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 703 704 sc = device_get_softc(dev); 705 mtx_lock(&sc->mtx); 706 707 found = false; 708 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { 709 /* Start on an aligned interrupt */ 710 if ((irq & (maxcount - 1)) != 0) 711 continue; 712 713 /* Assume we found a valid range until shown otherwise */ 714 found = true; 715 716 /* Check this range is valid */ 717 for (end_irq = irq; end_irq < irq + count; end_irq++) { 718 /* This is already used */ 719 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == 720 TEGRA_FLAG_MSI_USED) { 721 found = false; 722 break; 723 } 724 } 725 726 if (found) 727 break; 728 } 729 730 /* Not enough interrupts were found */ 731 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 732 mtx_unlock(&sc->mtx); 733 return (ENXIO); 734 } 735 736 for (i = 0; i < count; i++) { 737 /* Mark the interrupt as used */ 738 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 739 } 740 mtx_unlock(&sc->mtx); 741 742 for (i = 0; i < count; i++) 743 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 744 *pic = device_get_parent(dev); 745 return (0); 746 } 747 748 static int 749 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 750 struct intr_irqsrc **isrc) 751 { 752 struct tegra_pcib_softc *sc; 753 struct tegra_pcib_irqsrc *ti; 754 int i; 755 756 sc = device_get_softc(dev); 757 mtx_lock(&sc->mtx); 758 for (i = 0; i < count; i++) { 759 ti = (struct tegra_pcib_irqsrc *)isrc[i]; 760 761 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 762 ("%s: Trying to release an unused MSI-X interrupt", 763 __func__)); 764 765 ti->flags &= ~TEGRA_FLAG_MSI_USED; 766 } 767 mtx_unlock(&sc->mtx); 768 return (0); 769 } 770 771 static int 772 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 773 uint64_t *addr, uint32_t *data) 774 { 775 struct tegra_pcib_softc *sc = device_get_softc(dev); 776 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 777 778 *addr = vtophys(sc->msi_page); 779 *data = ti->irq; 780 return (0); 781 } 782 #endif 783 784 /* ------------------------------------------------------------------- */ 785 static bus_size_t 786 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 787 { 788 if (port >= TEGRA_PCIB_MAX_PORTS) 789 panic("invalid port number: %d\n", port); 790 791 if (port == 0) 792 return (AFI_PEX0_CTRL); 793 else if (port == 1) 794 return (AFI_PEX1_CTRL); 795 else if (port == 2) 796 return (AFI_PEX2_CTRL); 797 else 798 panic("invalid port number: %d\n", port); 799 } 800 801 static int 802 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 803 { 804 int rv; 805 806 rv = hwreset_assert(sc->hwreset_pcie_x); 807 if (rv != 0) { 808 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 809 return (rv); 810 } 811 rv = hwreset_assert(sc->hwreset_afi); 812 if (rv != 0) { 813 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 814 return (rv); 815 } 816 rv = hwreset_assert(sc->hwreset_pex); 817 if (rv != 0) { 818 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 819 return (rv); 820 } 821 822 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 823 824 /* Power supplies. */ 825 rv = regulator_enable(sc->supply_avddio_pex); 826 if (rv != 0) { 827 device_printf(sc->dev, 828 "Cannot enable 'avddio_pex' regulator\n"); 829 return (rv); 830 } 831 rv = regulator_enable(sc->supply_dvddio_pex); 832 if (rv != 0) { 833 device_printf(sc->dev, 834 "Cannot enable 'dvddio_pex' regulator\n"); 835 return (rv); 836 } 837 rv = regulator_enable(sc->supply_avdd_pex_pll); 838 if (rv != 0) { 839 device_printf(sc->dev, 840 "Cannot enable 'avdd-pex-pll' regulator\n"); 841 return (rv); 842 } 843 rv = regulator_enable(sc->supply_hvdd_pex); 844 if (rv != 0) { 845 device_printf(sc->dev, 846 "Cannot enable 'hvdd-pex-supply' regulator\n"); 847 return (rv); 848 } 849 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 850 if (rv != 0) { 851 device_printf(sc->dev, 852 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 853 return (rv); 854 } 855 rv = regulator_enable(sc->supply_vddio_pex_ctl); 856 if (rv != 0) { 857 device_printf(sc->dev, 858 "Cannot enable 'vddio-pex-ctl' regulator\n"); 859 return (rv); 860 } 861 rv = regulator_enable(sc->supply_avdd_pll_erefe); 862 if (rv != 0) { 863 device_printf(sc->dev, 864 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 865 return (rv); 866 } 867 868 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 869 sc->clk_pex, sc->hwreset_pex); 870 if (rv != 0) { 871 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 872 return (rv); 873 } 874 875 rv = hwreset_deassert(sc->hwreset_afi); 876 if (rv != 0) { 877 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 878 return (rv); 879 } 880 881 rv = clk_enable(sc->clk_afi); 882 if (rv != 0) { 883 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 884 return (rv); 885 } 886 rv = clk_enable(sc->clk_cml); 887 if (rv != 0) { 888 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 889 return (rv); 890 } 891 rv = clk_enable(sc->clk_pll_e); 892 if (rv != 0) { 893 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 894 return (rv); 895 } 896 return (0); 897 } 898 899 static struct tegra_pcib_port * 900 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 901 { 902 struct tegra_pcib_port *port; 903 uint32_t tmp[5]; 904 char tmpstr[6]; 905 int rv; 906 907 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 908 909 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 910 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 911 strcmp(tmpstr, "ok") == 0) 912 port->enabled = 1; 913 else 914 port->enabled = 0; 915 916 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 917 if (rv != sizeof(tmp)) { 918 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 919 rv); 920 goto fail; 921 } 922 port->rp_base_addr = tmp[2]; 923 port->rp_size = tmp[4]; 924 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 925 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 926 device_printf(sc->dev, "Invalid port index: %d\n", 927 port->port_idx); 928 goto fail; 929 } 930 /* XXX - TODO: 931 * Implement proper function for parsing pci "reg" property: 932 * - it have PCI bus format 933 * - its relative to matching "assigned-addresses" 934 */ 935 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 936 if (rv != sizeof(tmp)) { 937 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 938 goto fail; 939 } 940 port->rp_base_addr += tmp[2]; 941 942 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 943 sizeof(port->num_lanes)); 944 if (rv != sizeof(port->num_lanes)) { 945 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 946 rv); 947 goto fail; 948 } 949 if (port->num_lanes > 4) { 950 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 951 port->num_lanes); 952 goto fail; 953 } 954 955 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 956 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 957 958 /* Phy. */ 959 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 960 if (rv != 0) { 961 device_printf(sc->dev, 962 "Cannot get 'pcie-0' phy for port %d\n", 963 port->port_idx); 964 goto fail; 965 } 966 967 return (port); 968 fail: 969 free(port, M_DEVBUF); 970 return (NULL); 971 } 972 973 static int 974 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 975 { 976 phandle_t child; 977 struct tegra_pcib_port *port; 978 int rv; 979 980 /* Power supplies. */ 981 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 982 &sc->supply_avddio_pex); 983 if (rv != 0) { 984 device_printf(sc->dev, 985 "Cannot get 'avddio-pex' regulator\n"); 986 return (ENXIO); 987 } 988 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 989 &sc->supply_dvddio_pex); 990 if (rv != 0) { 991 device_printf(sc->dev, 992 "Cannot get 'dvddio-pex' regulator\n"); 993 return (ENXIO); 994 } 995 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 996 &sc->supply_avdd_pex_pll); 997 if (rv != 0) { 998 device_printf(sc->dev, 999 "Cannot get 'avdd-pex-pll' regulator\n"); 1000 return (ENXIO); 1001 } 1002 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 1003 &sc->supply_hvdd_pex); 1004 if (rv != 0) { 1005 device_printf(sc->dev, 1006 "Cannot get 'hvdd-pex' regulator\n"); 1007 return (ENXIO); 1008 } 1009 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 1010 &sc->supply_hvdd_pex_pll_e); 1011 if (rv != 0) { 1012 device_printf(sc->dev, 1013 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1014 return (ENXIO); 1015 } 1016 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 1017 &sc->supply_vddio_pex_ctl); 1018 if (rv != 0) { 1019 device_printf(sc->dev, 1020 "Cannot get 'vddio-pex-ctl' regulator\n"); 1021 return (ENXIO); 1022 } 1023 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 1024 &sc->supply_avdd_pll_erefe); 1025 if (rv != 0) { 1026 device_printf(sc->dev, 1027 "Cannot get 'avdd-pll-erefe' regulator\n"); 1028 return (ENXIO); 1029 } 1030 1031 /* Resets. */ 1032 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1033 if (rv != 0) { 1034 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1035 return (ENXIO); 1036 } 1037 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1038 if (rv != 0) { 1039 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1040 return (ENXIO); 1041 } 1042 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1043 if (rv != 0) { 1044 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1045 return (ENXIO); 1046 } 1047 1048 /* Clocks. */ 1049 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1050 if (rv != 0) { 1051 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1052 return (ENXIO); 1053 } 1054 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1055 if (rv != 0) { 1056 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1057 return (ENXIO); 1058 } 1059 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1060 if (rv != 0) { 1061 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1062 return (ENXIO); 1063 } 1064 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1065 if (rv != 0) { 1066 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1067 return (ENXIO); 1068 } 1069 1070 /* Ports */ 1071 sc->num_ports = 0; 1072 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1073 port = tegra_pcib_parse_port(sc, child); 1074 if (port == NULL) { 1075 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1076 return (ENXIO); 1077 } 1078 sc->ports[sc->num_ports++] = port; 1079 } 1080 1081 return (0); 1082 } 1083 1084 static int 1085 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1086 struct ofw_pci_range *ranges, int nranges) 1087 { 1088 int i; 1089 1090 for (i = 2; i < nranges; i++) { 1091 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1092 OFW_PCI_PHYS_HI_SPACE_IO) { 1093 if (sc->io_range.size != 0) { 1094 device_printf(sc->dev, 1095 "Duplicated IO range found in DT\n"); 1096 return (ENXIO); 1097 } 1098 sc->io_range = ranges[i]; 1099 } 1100 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1101 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1102 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1103 if (sc->pref_mem_range.size != 0) { 1104 device_printf(sc->dev, 1105 "Duplicated memory range found " 1106 "in DT\n"); 1107 return (ENXIO); 1108 } 1109 sc->pref_mem_range = ranges[i]; 1110 } else { 1111 if (sc->mem_range.size != 0) { 1112 device_printf(sc->dev, 1113 "Duplicated memory range found " 1114 "in DT\n"); 1115 return (ENXIO); 1116 } 1117 sc->mem_range = ranges[i]; 1118 } 1119 } 1120 } 1121 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1122 || (sc->pref_mem_range.size == 0)) { 1123 device_printf(sc->dev, 1124 " Not all required ranges are found in DT\n"); 1125 return (ENXIO); 1126 } 1127 return (0); 1128 } 1129 1130 /* 1131 * Hardware config. 1132 */ 1133 static int 1134 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1135 struct tegra_pcib_port *port) 1136 { 1137 uint32_t reg; 1138 int i; 1139 1140 /* Setup link detection. */ 1141 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1142 RP_PRIV_MISC, 4); 1143 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1144 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1145 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1146 RP_PRIV_MISC, reg, 4); 1147 1148 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1149 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1150 RP_VEND_XP, 4); 1151 if (reg & RP_VEND_XP_DL_UP) 1152 break; 1153 DELAY(1); 1154 } 1155 if (i <= 0) 1156 return (ETIMEDOUT); 1157 1158 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1159 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1160 RP_LINK_CONTROL_STATUS, 4); 1161 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1162 break; 1163 1164 DELAY(1); 1165 } 1166 if (i <= 0) 1167 return (ETIMEDOUT); 1168 return (0); 1169 } 1170 1171 static void 1172 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1173 { 1174 struct tegra_pcib_port *port; 1175 uint32_t reg; 1176 int rv; 1177 1178 port = sc->ports[port_num]; 1179 1180 /* Put port to reset. */ 1181 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1182 reg &= ~AFI_PEX_CTRL_RST_L; 1183 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1184 AFI_RD4(sc, port->afi_pex_ctrl); 1185 DELAY(10); 1186 1187 /* Enable clocks. */ 1188 reg |= AFI_PEX_CTRL_REFCLK_EN; 1189 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1190 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1191 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1192 AFI_RD4(sc, port->afi_pex_ctrl); 1193 DELAY(100); 1194 1195 /* Release reset. */ 1196 reg |= AFI_PEX_CTRL_RST_L; 1197 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1198 1199 rv = tegra_pcib_wait_for_link(sc, port); 1200 if (bootverbose) 1201 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1202 port->port_idx, port->num_lanes, 1203 port->num_lanes > 1 ? "s": "", 1204 rv == 0 ? "up": "down"); 1205 } 1206 1207 static void 1208 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1209 { 1210 struct tegra_pcib_port *port; 1211 uint32_t reg; 1212 1213 port = sc->ports[port_num]; 1214 1215 /* Put port to reset. */ 1216 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1217 reg &= ~AFI_PEX_CTRL_RST_L; 1218 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1219 AFI_RD4(sc, port->afi_pex_ctrl); 1220 DELAY(10); 1221 1222 /* Disable clocks. */ 1223 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1224 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1225 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1226 1227 if (bootverbose) 1228 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1229 port->port_idx, port->num_lanes, 1230 port->num_lanes > 1 ? "s": ""); 1231 } 1232 1233 static void 1234 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1235 uint64_t fpci, uint32_t size, int is_memory) 1236 { 1237 uint32_t fpci_reg; 1238 uint32_t axi_reg; 1239 uint32_t size_reg; 1240 1241 axi_reg = axi & ~0xFFF; 1242 size_reg = size >> 12; 1243 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1244 fpci_reg |= is_memory ? 0x1 : 0x0; 1245 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1246 AFI_WR4(sc, bars[bar].size, size_reg); 1247 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1248 } 1249 1250 static int 1251 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1252 { 1253 int rv; 1254 int i; 1255 uint32_t reg; 1256 1257 rv = tegra_pcib_enable_fdt_resources(sc); 1258 if (rv != 0) { 1259 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1260 return (rv); 1261 } 1262 /* Enable PLLE control. */ 1263 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1264 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1265 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1266 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1267 1268 /* Set bias pad. */ 1269 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1270 1271 /* Configure mode and ports. */ 1272 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1273 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1274 if (sc->lanes_cfg == 0x14) { 1275 if (bootverbose) 1276 device_printf(sc->dev, 1277 "Using x1,x4 configuration\n"); 1278 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1279 } else if (sc->lanes_cfg == 0x12) { 1280 if (bootverbose) 1281 device_printf(sc->dev, 1282 "Using x1,x2 configuration\n"); 1283 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1284 } else { 1285 device_printf(sc->dev, 1286 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1287 } 1288 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1289 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1290 if ((sc->ports[i] != NULL)) 1291 reg &= 1292 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1293 } 1294 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1295 1296 /* Enable Gen2 support. */ 1297 reg = AFI_RD4(sc, AFI_FUSE); 1298 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1299 AFI_WR4(sc, AFI_FUSE, reg); 1300 1301 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1302 if (sc->ports[i] != NULL) { 1303 rv = phy_enable(sc->ports[i]->phy); 1304 if (rv != 0) { 1305 device_printf(sc->dev, 1306 "Cannot enable phy for port %d\n", 1307 sc->ports[i]->port_idx); 1308 return (rv); 1309 } 1310 } 1311 } 1312 1313 rv = hwreset_deassert(sc->hwreset_pcie_x); 1314 if (rv != 0) { 1315 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1316 return (rv); 1317 } 1318 1319 /* Enable config space. */ 1320 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1321 reg |= AFI_CONFIGURATION_EN_FPCI; 1322 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1323 1324 /* Enable AFI errors. */ 1325 reg = 0; 1326 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1327 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1328 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1329 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1330 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1331 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1332 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1333 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1334 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1335 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1340 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1341 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1342 1343 /* Enable INT, disable MSI. */ 1344 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1345 1346 /* Mask all FPCI errors. */ 1347 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1348 1349 /* Setup AFI translation windows. */ 1350 /* BAR 0 - type 1 extended configuration. */ 1351 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1352 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1353 1354 /* BAR 1 - downstream I/O. */ 1355 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1356 sc->io_range.size, 0); 1357 1358 /* BAR 2 - downstream prefetchable memory 1:1. */ 1359 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1360 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1361 1362 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1363 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1364 sc->mem_range.host, sc->mem_range.size, 1); 1365 1366 /* BAR 3-8 clear. */ 1367 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1368 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1369 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1370 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1371 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1372 1373 /* MSI BAR - clear. */ 1374 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1375 return(0); 1376 } 1377 1378 #ifdef TEGRA_PCIB_MSI_ENABLE 1379 static int 1380 tegra_pcib_attach_msi(device_t dev) 1381 { 1382 struct tegra_pcib_softc *sc; 1383 uint32_t reg; 1384 int i, rv; 1385 1386 sc = device_get_softc(dev); 1387 1388 sc->msi_page = kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0, 1389 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1390 1391 /* MSI BAR */ 1392 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1393 PAGE_SIZE, 0); 1394 1395 /* Disble and clear all interrupts. */ 1396 for (i = 0; i < AFI_MSI_REGS; i++) { 1397 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1398 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1399 } 1400 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1401 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1402 if (rv != 0) { 1403 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1404 rv = ENXIO; 1405 goto out; 1406 } 1407 1408 if (tegra_pcib_msi_attach(sc) != 0) { 1409 device_printf(dev, "WARNING: unable to attach PIC\n"); 1410 tegra_pcib_msi_detach(sc); 1411 goto out; 1412 } 1413 1414 /* Unmask MSI interrupt. */ 1415 reg = AFI_RD4(sc, AFI_INTR_MASK); 1416 reg |= AFI_INTR_MASK_MSI_MASK; 1417 AFI_WR4(sc, AFI_INTR_MASK, reg); 1418 1419 out: 1420 return (rv); 1421 } 1422 #endif 1423 1424 static int 1425 tegra_pcib_probe(device_t dev) 1426 { 1427 if (!ofw_bus_status_okay(dev)) 1428 return (ENXIO); 1429 1430 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1431 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1432 return (BUS_PROBE_DEFAULT); 1433 } 1434 return (ENXIO); 1435 } 1436 1437 static int 1438 tegra_pcib_attach(device_t dev) 1439 { 1440 struct tegra_pcib_softc *sc; 1441 phandle_t node; 1442 int rv; 1443 int rid; 1444 struct tegra_pcib_port *port; 1445 int i; 1446 1447 sc = device_get_softc(dev); 1448 sc->dev = dev; 1449 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1450 1451 node = ofw_bus_get_node(dev); 1452 1453 rv = tegra_pcib_parse_fdt_resources(sc, node); 1454 if (rv != 0) { 1455 device_printf(dev, "Cannot get FDT resources\n"); 1456 return (rv); 1457 } 1458 1459 /* Allocate bus_space resources. */ 1460 rid = 0; 1461 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1462 RF_ACTIVE); 1463 if (sc->pads_mem_res == NULL) { 1464 device_printf(dev, "Cannot allocate PADS register\n"); 1465 rv = ENXIO; 1466 goto out; 1467 } 1468 /* 1469 * XXX - FIXME 1470 * tag for config space is not filled when RF_ALLOCATED flag is used. 1471 */ 1472 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1473 1474 rid = 1; 1475 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1476 RF_ACTIVE); 1477 if (sc->afi_mem_res == NULL) { 1478 device_printf(dev, "Cannot allocate AFI register\n"); 1479 rv = ENXIO; 1480 goto out; 1481 } 1482 1483 rid = 2; 1484 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1485 RF_ALLOCATED); 1486 if (sc->cfg_mem_res == NULL) { 1487 device_printf(dev, "Cannot allocate config space memory\n"); 1488 rv = ENXIO; 1489 goto out; 1490 } 1491 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1492 1493 /* Map RP slots */ 1494 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1495 if (sc->ports[i] == NULL) 1496 continue; 1497 port = sc->ports[i]; 1498 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1499 port->rp_size, 0, &port->cfg_handle); 1500 if (rv != 0) { 1501 device_printf(sc->dev, "Cannot allocate memory for " 1502 "port: %d\n", i); 1503 rv = ENXIO; 1504 goto out; 1505 } 1506 } 1507 1508 /* 1509 * Get PCI interrupt 1510 */ 1511 rid = 0; 1512 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1513 RF_ACTIVE | RF_SHAREABLE); 1514 if (sc->irq_res == NULL) { 1515 device_printf(dev, "Cannot allocate IRQ resources\n"); 1516 rv = ENXIO; 1517 goto out; 1518 } 1519 1520 rid = 1; 1521 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1522 RF_ACTIVE); 1523 if (sc->irq_res == NULL) { 1524 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1525 rv = ENXIO; 1526 goto out; 1527 } 1528 1529 sc->ofw_pci.sc_range_mask = 0x3; 1530 rv = ofw_pci_init(dev); 1531 if (rv != 0) 1532 goto out; 1533 1534 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1535 sc->ofw_pci.sc_nrange); 1536 if (rv != 0) 1537 goto out; 1538 1539 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1540 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1541 device_printf(dev, "cannot setup interrupt handler\n"); 1542 rv = ENXIO; 1543 goto out; 1544 } 1545 1546 /* 1547 * Enable PCIE device. 1548 */ 1549 rv = tegra_pcib_enable(sc); 1550 if (rv != 0) 1551 goto out; 1552 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1553 if (sc->ports[i] == NULL) 1554 continue; 1555 if (sc->ports[i]->enabled) 1556 tegra_pcib_port_enable(sc, i); 1557 else 1558 tegra_pcib_port_disable(sc, i); 1559 } 1560 1561 #ifdef TEGRA_PCIB_MSI_ENABLE 1562 rv = tegra_pcib_attach_msi(dev); 1563 if (rv != 0) 1564 goto out; 1565 #endif 1566 device_add_child(dev, "pci", -1); 1567 1568 return (bus_generic_attach(dev)); 1569 1570 out: 1571 1572 return (rv); 1573 } 1574 1575 static device_method_t tegra_pcib_methods[] = { 1576 /* Device interface */ 1577 DEVMETHOD(device_probe, tegra_pcib_probe), 1578 DEVMETHOD(device_attach, tegra_pcib_attach), 1579 1580 /* Bus interface */ 1581 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1582 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1583 1584 /* pcib interface */ 1585 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1586 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1587 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1588 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1589 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1590 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1591 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1592 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 1593 1594 #ifdef TEGRA_PCIB_MSI_ENABLE 1595 /* MSI/MSI-X */ 1596 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1597 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1598 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1599 1600 /* Interrupt controller interface */ 1601 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1602 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1603 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1604 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1605 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1606 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1607 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1608 #endif 1609 1610 /* OFW bus interface */ 1611 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1612 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1613 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1614 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1615 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1616 1617 DEVMETHOD_END 1618 }; 1619 1620 static devclass_t pcib_devclass; 1621 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1622 sizeof(struct tegra_pcib_softc), ofw_pci_driver); 1623 DRIVER_MODULE(tegra_pcib, simplebus, tegra_pcib_driver, pcib_devclass, 1624 NULL, NULL); 1625