1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/bus.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/devmap.h> 46 47 #include <machine/intr.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/phy/phy.h> 55 #include <dev/extres/regulator/regulator.h> 56 #include <dev/fdt/fdt_common.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 #include <dev/ofw/ofw_pci.h> 60 #include <dev/ofw/ofwpci.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include <machine/resource.h> 66 #include <machine/bus.h> 67 68 #include <arm/nvidia/tegra_pmc.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 74 75 #define AFI_AXI_BAR0_SZ 0x000 76 #define AFI_AXI_BAR1_SZ 0x004 77 #define AFI_AXI_BAR2_SZ 0x008 78 #define AFI_AXI_BAR3_SZ 0x00c 79 #define AFI_AXI_BAR4_SZ 0x010 80 #define AFI_AXI_BAR5_SZ 0x014 81 #define AFI_AXI_BAR0_START 0x018 82 #define AFI_AXI_BAR1_START 0x01c 83 #define AFI_AXI_BAR2_START 0x020 84 #define AFI_AXI_BAR3_START 0x024 85 #define AFI_AXI_BAR4_START 0x028 86 #define AFI_AXI_BAR5_START 0x02c 87 #define AFI_FPCI_BAR0 0x030 88 #define AFI_FPCI_BAR1 0x034 89 #define AFI_FPCI_BAR2 0x038 90 #define AFI_FPCI_BAR3 0x03c 91 #define AFI_FPCI_BAR4 0x040 92 #define AFI_FPCI_BAR5 0x044 93 #define AFI_MSI_BAR_SZ 0x060 94 #define AFI_MSI_FPCI_BAR_ST 0x064 95 #define AFI_MSI_AXI_BAR_ST 0x068 96 97 98 #define AFI_AXI_BAR6_SZ 0x134 99 #define AFI_AXI_BAR7_SZ 0x138 100 #define AFI_AXI_BAR8_SZ 0x13c 101 #define AFI_AXI_BAR6_START 0x140 102 #define AFI_AXI_BAR7_START 0x144 103 #define AFI_AXI_BAR8_START 0x148 104 #define AFI_FPCI_BAR6 0x14c 105 #define AFI_FPCI_BAR7 0x150 106 #define AFI_FPCI_BAR8 0x154 107 108 #define AFI_CONFIGURATION 0x0ac 109 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 110 111 #define AFI_FPCI_ERROR_MASKS 0x0b0 112 #define AFI_INTR_MASK 0x0b4 113 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 114 #define AFI_INTR_MASK_INT_MASK (1 << 0) 115 116 #define AFI_INTR_CODE 0x0b8 117 #define AFI_INTR_CODE_MASK 0xf 118 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 119 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 120 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 121 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 122 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 123 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 124 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 125 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 126 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 127 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 128 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 129 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 130 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 131 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 132 133 134 #define AFI_INTR_SIGNATURE 0x0bc 135 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 136 #define AFI_SM_INTR_ENABLE 0x0c4 137 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 138 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 139 #define AFI_SM_INTR_HOTPLUG (1 << 12) 140 #define AFI_SM_INTR_PME (1 << 11) 141 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 142 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 143 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 144 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 145 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 146 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 147 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 148 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 149 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 150 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 151 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 152 153 #define AFI_AFI_INTR_ENABLE 0x0c8 154 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 155 156 #define AFI_PCIE_CONFIG 0x0f8 157 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 158 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 159 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 162 163 #define AFI_FUSE 0x104 164 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 165 166 #define AFI_PEX0_CTRL 0x110 167 #define AFI_PEX1_CTRL 0x118 168 #define AFI_PEX2_CTRL 0x128 169 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 170 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 171 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 172 #define AFI_PEX_CTRL_RST_L (1 << 0) 173 174 #define AFI_AXI_BAR6_SZ 0x134 175 #define AFI_AXI_BAR7_SZ 0x138 176 #define AFI_AXI_BAR8_SZ 0x13c 177 #define AFI_AXI_BAR6_START 0x140 178 #define AFI_AXI_BAR7_START 0x144 179 #define AFI_AXI_BAR8_START 0x148 180 #define AFI_FPCI_BAR6 0x14c 181 #define AFI_FPCI_BAR7 0x150 182 #define AFI_FPCI_BAR8 0x154 183 #define AFI_PLLE_CONTROL 0x160 184 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 185 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 186 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 187 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 188 189 #define AFI_PEXBIAS_CTRL 0x168 190 191 /* FPCI Address space */ 192 #define FPCI_MAP_IO 0xfdfc000000ULL 193 #define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 194 #define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 195 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 196 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 197 198 /* Configuration space */ 199 #define RP_VEND_XP 0x00000F00 200 #define RP_VEND_XP_DL_UP (1 << 30) 201 202 #define RP_PRIV_MISC 0x00000FE0 203 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 204 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 205 206 #define RP_LINK_CONTROL_STATUS 0x00000090 207 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 208 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 209 210 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 211 212 #define DEBUG 213 #ifdef DEBUG 214 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 215 #else 216 #define debugf(fmt, args...) 217 #endif 218 219 /* 220 * Configuration space format: 221 * [27:24] extended register 222 * [23:16] bus 223 * [15:11] slot (device) 224 * [10: 8] function 225 * [ 7: 0] register 226 */ 227 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 228 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 229 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 230 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 231 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 232 233 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 234 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 235 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 236 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 237 238 static struct { 239 bus_size_t axi_start; 240 bus_size_t fpci_start; 241 bus_size_t size; 242 } bars[] = { 243 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 244 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 245 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 246 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 247 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 248 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 249 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 250 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 251 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 252 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 253 }; 254 255 /* Compatible devices. */ 256 static struct ofw_compat_data compat_data[] = { 257 {"nvidia,tegra124-pcie", 1}, 258 {NULL, 0}, 259 }; 260 261 struct tegra_pcib_port { 262 int enabled; 263 int port_idx; /* chip port index */ 264 int num_lanes; /* number of lanes */ 265 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 266 267 /* Config space properties. */ 268 bus_addr_t rp_base_addr; /* PA of config window */ 269 bus_size_t rp_size; /* size of config window */ 270 bus_space_handle_t cfg_handle; /* handle of config window */ 271 }; 272 273 #define TEGRA_PCIB_MAX_PORTS 3 274 struct tegra_pcib_softc { 275 struct ofw_pci_softc ofw_pci; 276 device_t dev; 277 struct mtx mtx; 278 struct resource *pads_mem_res; 279 struct resource *afi_mem_res; 280 struct resource *cfg_mem_res; 281 struct resource *irq_res; 282 struct resource *msi_irq_res; 283 void *intr_cookie; 284 void *msi_intr_cookie; 285 286 struct ofw_pci_range mem_range; 287 struct ofw_pci_range pref_mem_range; 288 struct ofw_pci_range io_range; 289 290 phy_t phy; 291 clk_t clk_pex; 292 clk_t clk_afi; 293 clk_t clk_pll_e; 294 clk_t clk_cml; 295 hwreset_t hwreset_pex; 296 hwreset_t hwreset_afi; 297 hwreset_t hwreset_pcie_x; 298 regulator_t supply_avddio_pex; 299 regulator_t supply_dvddio_pex; 300 regulator_t supply_avdd_pex_pll; 301 regulator_t supply_hvdd_pex; 302 regulator_t supply_hvdd_pex_pll_e; 303 regulator_t supply_vddio_pex_ctl; 304 regulator_t supply_avdd_pll_erefe; 305 306 uint32_t msi_bitmap; 307 bus_addr_t cfg_base_addr; /* base address of config */ 308 bus_size_t cfg_cur_offs; /* currently mapped window */ 309 bus_space_handle_t cfg_handle; /* handle of config window */ 310 bus_space_tag_t bus_tag; /* tag of config window */ 311 int lanes_cfg; 312 int num_ports; 313 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 314 }; 315 316 317 static int 318 tegra_pcib_maxslots(device_t dev) 319 { 320 return (16); 321 } 322 323 static int 324 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 325 { 326 struct tegra_pcib_softc *sc; 327 328 sc = device_get_softc(bus); 329 device_printf(bus, "route pin %d for device %d.%d to %ju\n", 330 pin, pci_get_slot(dev), pci_get_function(dev), 331 rman_get_start(sc->irq_res)); 332 333 return (rman_get_start(sc->irq_res)); 334 } 335 336 static int 337 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 338 u_int func, u_int reg) 339 { 340 bus_size_t offs; 341 int rv; 342 343 offs = sc->cfg_base_addr; 344 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 345 PCI_CFG_EXT_REG(reg); 346 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 347 return (0); 348 if (sc->cfg_handle != 0) 349 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 350 351 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 352 if (rv != 0) 353 device_printf(sc->dev, "Cannot map config space\n"); 354 else 355 sc->cfg_cur_offs = offs; 356 return (rv); 357 } 358 359 static uint32_t 360 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 361 u_int reg, int bytes) 362 { 363 struct tegra_pcib_softc *sc; 364 bus_space_handle_t hndl; 365 uint32_t off; 366 uint32_t val; 367 int rv, i; 368 369 sc = device_get_softc(dev); 370 if (bus == 0) { 371 if (func != 0) 372 return (0xFFFFFFFF); 373 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 374 if ((sc->ports[i] != NULL) && 375 (sc->ports[i]->port_idx == slot)) { 376 hndl = sc->ports[i]->cfg_handle; 377 off = reg & 0xFFF; 378 break; 379 } 380 } 381 if (i >= TEGRA_PCIB_MAX_PORTS) 382 return (0xFFFFFFFF); 383 } else { 384 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 385 if (rv != 0) 386 return (0xFFFFFFFF); 387 hndl = sc->cfg_handle; 388 off = PCI_CFG_BASE_REG(reg); 389 } 390 391 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 392 switch (bytes) { 393 case 4: 394 break; 395 case 2: 396 if (off & 3) 397 val >>= 16; 398 val &= 0xffff; 399 break; 400 case 1: 401 val >>= ((off & 3) << 3); 402 val &= 0xff; 403 break; 404 } 405 return val; 406 } 407 408 static void 409 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 410 u_int reg, uint32_t val, int bytes) 411 { 412 struct tegra_pcib_softc *sc; 413 bus_space_handle_t hndl; 414 uint32_t off; 415 uint32_t val2; 416 int rv, i; 417 418 sc = device_get_softc(dev); 419 if (bus == 0) { 420 if (func != 0) 421 return; 422 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 423 if ((sc->ports[i] != NULL) && 424 (sc->ports[i]->port_idx == slot)) { 425 hndl = sc->ports[i]->cfg_handle; 426 off = reg & 0xFFF; 427 break; 428 } 429 } 430 if (i >= TEGRA_PCIB_MAX_PORTS) 431 return; 432 } else { 433 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 434 if (rv != 0) 435 return; 436 hndl = sc->cfg_handle; 437 off = PCI_CFG_BASE_REG(reg); 438 } 439 440 switch (bytes) { 441 case 4: 442 bus_space_write_4(sc->bus_tag, hndl, off, val); 443 break; 444 case 2: 445 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 446 val2 &= ~(0xffff << ((off & 3) << 3)); 447 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 448 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 449 break; 450 case 1: 451 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 452 val2 &= ~(0xff << ((off & 3) << 3)); 453 val2 |= ((val & 0xff) << ((off & 3) << 3)); 454 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 455 break; 456 } 457 } 458 459 static int tegra_pci_intr(void *arg) 460 { 461 struct tegra_pcib_softc *sc = arg; 462 uint32_t code, signature; 463 464 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 465 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 466 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 467 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 468 return(FILTER_STRAY); 469 470 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 471 return (FILTER_HANDLED); 472 } 473 474 #if defined(TEGRA_PCI_MSI) 475 static int 476 tegra_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 477 uint32_t *data) 478 { 479 struct tegra_pcib_softc *sc; 480 481 sc = device_get_softc(dev); 482 irq = irq - MSI_IRQ; 483 484 /* validate parameters */ 485 if (isclr(&sc->msi_bitmap, irq)) { 486 device_printf(dev, "invalid MSI 0x%x\n", irq); 487 return (EINVAL); 488 } 489 490 tegra_msi_data(irq, addr, data); 491 492 debugf("%s: irq: %d addr: %jx data: %x\n", 493 __func__, irq, *addr, *data); 494 495 return (0); 496 } 497 498 static int 499 tegra_pcib_alloc_msi(device_t dev, device_t child, int count, 500 int maxcount __unused, int *irqs) 501 { 502 struct tegra_pcib_softc *sc; 503 u_int start = 0, i; 504 505 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 506 return (EINVAL); 507 508 sc = device_get_softc(dev); 509 mtx_lock(&sc->mtx); 510 511 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 512 for (i = start; i < start + count; i++) { 513 if (isset(&sc->msi_bitmap, i)) 514 break; 515 } 516 if (i == start + count) 517 break; 518 } 519 520 if ((start + count) == MSI_IRQ_NUM) { 521 mtx_unlock(&sc->mtx); 522 return (ENXIO); 523 } 524 525 for (i = start; i < start + count; i++) { 526 setbit(&sc->msi_bitmap, i); 527 irqs[i] = MSI_IRQ + i; 528 } 529 debugf("%s: start: %x count: %x\n", __func__, start, count); 530 531 mtx_unlock(&sc->mtx); 532 return (0); 533 } 534 535 static int 536 tegra_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 537 { 538 struct tegra_pcib_softc *sc; 539 u_int i; 540 541 sc = device_get_softc(dev); 542 mtx_lock(&sc->mtx); 543 544 for (i = 0; i < count; i++) 545 clrbit(&sc->msi_bitmap, irqs[i] - MSI_IRQ); 546 547 mtx_unlock(&sc->mtx); 548 return (0); 549 } 550 #endif 551 552 static bus_size_t 553 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 554 { 555 if (port >= TEGRA_PCIB_MAX_PORTS) 556 panic("invalid port number: %d\n", port); 557 558 if (port == 0) 559 return (AFI_PEX0_CTRL); 560 else if (port == 1) 561 return (AFI_PEX1_CTRL); 562 else if (port == 2) 563 return (AFI_PEX2_CTRL); 564 else 565 panic("invalid port number: %d\n", port); 566 } 567 568 static int 569 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 570 { 571 int rv; 572 573 rv = hwreset_assert(sc->hwreset_pcie_x); 574 if (rv != 0) { 575 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 576 return (rv); 577 } 578 rv = hwreset_assert(sc->hwreset_afi); 579 if (rv != 0) { 580 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 581 return (rv); 582 } 583 rv = hwreset_assert(sc->hwreset_pex); 584 if (rv != 0) { 585 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 586 return (rv); 587 } 588 589 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 590 591 /* Power supplies. */ 592 rv = regulator_enable(sc->supply_avddio_pex); 593 if (rv != 0) { 594 device_printf(sc->dev, 595 "Cannot enable 'avddio_pex' regulator\n"); 596 return (rv); 597 } 598 rv = regulator_enable(sc->supply_dvddio_pex); 599 if (rv != 0) { 600 device_printf(sc->dev, 601 "Cannot enable 'dvddio_pex' regulator\n"); 602 return (rv); 603 } 604 rv = regulator_enable(sc->supply_avdd_pex_pll); 605 if (rv != 0) { 606 device_printf(sc->dev, 607 "Cannot enable 'avdd-pex-pll' regulator\n"); 608 return (rv); 609 } 610 rv = regulator_enable(sc->supply_hvdd_pex); 611 if (rv != 0) { 612 device_printf(sc->dev, 613 "Cannot enable 'hvdd-pex-supply' regulator\n"); 614 return (rv); 615 } 616 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 617 if (rv != 0) { 618 device_printf(sc->dev, 619 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 620 return (rv); 621 } 622 rv = regulator_enable(sc->supply_vddio_pex_ctl); 623 if (rv != 0) { 624 device_printf(sc->dev, 625 "Cannot enable 'vddio-pex-ctl' regulator\n"); 626 return (rv); 627 } 628 rv = regulator_enable(sc->supply_avdd_pll_erefe); 629 if (rv != 0) { 630 device_printf(sc->dev, 631 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 632 return (rv); 633 } 634 635 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 636 sc->clk_pex, sc->hwreset_pex); 637 if (rv != 0) { 638 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 639 return (rv); 640 } 641 642 rv = hwreset_deassert(sc->hwreset_afi); 643 if (rv != 0) { 644 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 645 return (rv); 646 } 647 648 rv = clk_enable(sc->clk_afi); 649 if (rv != 0) { 650 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 651 return (rv); 652 } 653 rv = clk_enable(sc->clk_cml); 654 if (rv != 0) { 655 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 656 return (rv); 657 } 658 rv = clk_enable(sc->clk_pll_e); 659 if (rv != 0) { 660 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 661 return (rv); 662 } 663 return (0); 664 } 665 666 static struct tegra_pcib_port * 667 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 668 { 669 struct tegra_pcib_port *port; 670 uint32_t tmp[5]; 671 char tmpstr[6]; 672 int rv; 673 674 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 675 676 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 677 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 678 strcmp(tmpstr, "ok") == 0) 679 port->enabled = 1; 680 else 681 port->enabled = 0; 682 683 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 684 if (rv != sizeof(tmp)) { 685 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 686 rv); 687 goto fail; 688 } 689 port->rp_base_addr = tmp[2]; 690 port->rp_size = tmp[4]; 691 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 692 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 693 device_printf(sc->dev, "Invalid port index: %d\n", 694 port->port_idx); 695 goto fail; 696 } 697 /* XXX - TODO: 698 * Implement proper function for parsing pci "reg" property: 699 * - it have PCI bus format 700 * - its relative to matching "assigned-addresses" 701 */ 702 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 703 if (rv != sizeof(tmp)) { 704 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 705 goto fail; 706 } 707 port->rp_base_addr += tmp[2]; 708 709 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 710 sizeof(port->num_lanes)); 711 if (rv != sizeof(port->num_lanes)) { 712 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 713 rv); 714 goto fail; 715 } 716 if (port->num_lanes > 4) { 717 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 718 port->num_lanes); 719 goto fail; 720 } 721 722 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 723 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 724 725 return (port); 726 fail: 727 free(port, M_DEVBUF); 728 return (NULL); 729 } 730 731 732 static int 733 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 734 { 735 phandle_t child; 736 struct tegra_pcib_port *port; 737 int rv; 738 739 /* Power supplies. */ 740 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 741 &sc->supply_avddio_pex); 742 if (rv != 0) { 743 device_printf(sc->dev, 744 "Cannot get 'avddio-pex' regulator\n"); 745 return (ENXIO); 746 } 747 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 748 &sc->supply_dvddio_pex); 749 if (rv != 0) { 750 device_printf(sc->dev, 751 "Cannot get 'dvddio-pex' regulator\n"); 752 return (ENXIO); 753 } 754 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 755 &sc->supply_avdd_pex_pll); 756 if (rv != 0) { 757 device_printf(sc->dev, 758 "Cannot get 'avdd-pex-pll' regulator\n"); 759 return (ENXIO); 760 } 761 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 762 &sc->supply_hvdd_pex); 763 if (rv != 0) { 764 device_printf(sc->dev, 765 "Cannot get 'hvdd-pex' regulator\n"); 766 return (ENXIO); 767 } 768 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 769 &sc->supply_hvdd_pex_pll_e); 770 if (rv != 0) { 771 device_printf(sc->dev, 772 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 773 return (ENXIO); 774 } 775 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 776 &sc->supply_vddio_pex_ctl); 777 if (rv != 0) { 778 device_printf(sc->dev, 779 "Cannot get 'vddio-pex-ctl' regulator\n"); 780 return (ENXIO); 781 } 782 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 783 &sc->supply_avdd_pll_erefe); 784 if (rv != 0) { 785 device_printf(sc->dev, 786 "Cannot get 'avdd-pll-erefe' regulator\n"); 787 return (ENXIO); 788 } 789 790 /* Resets. */ 791 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 792 if (rv != 0) { 793 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 794 return (ENXIO); 795 } 796 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 797 if (rv != 0) { 798 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 799 return (ENXIO); 800 } 801 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 802 if (rv != 0) { 803 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 804 return (ENXIO); 805 } 806 807 /* Clocks. */ 808 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 809 if (rv != 0) { 810 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 811 return (ENXIO); 812 } 813 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 814 if (rv != 0) { 815 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 816 return (ENXIO); 817 } 818 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 819 if (rv != 0) { 820 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 821 return (ENXIO); 822 } 823 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 824 if (rv != 0) { 825 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 826 return (ENXIO); 827 } 828 829 /* Phy. */ 830 rv = phy_get_by_ofw_name(sc->dev, 0, "pcie", &sc->phy); 831 if (rv != 0) { 832 device_printf(sc->dev, "Cannot get 'pcie' phy\n"); 833 return (ENXIO); 834 } 835 836 /* Ports */ 837 sc->num_ports = 0; 838 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 839 port = tegra_pcib_parse_port(sc, child); 840 if (port == NULL) { 841 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 842 return (ENXIO); 843 } 844 sc->ports[sc->num_ports++] = port; 845 } 846 847 return (0); 848 } 849 850 static int 851 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 852 struct ofw_pci_range *ranges, int nranges) 853 { 854 int i; 855 856 for (i = 2; i < nranges; i++) { 857 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 858 OFW_PCI_PHYS_HI_SPACE_IO) { 859 if (sc->io_range.size != 0) { 860 device_printf(sc->dev, 861 "Duplicated IO range found in DT\n"); 862 return (ENXIO); 863 } 864 sc->io_range = ranges[i]; 865 } 866 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 867 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 868 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 869 if (sc->pref_mem_range.size != 0) { 870 device_printf(sc->dev, 871 "Duplicated memory range found " 872 "in DT\n"); 873 return (ENXIO); 874 } 875 sc->pref_mem_range = ranges[i]; 876 } else { 877 if (sc->mem_range.size != 0) { 878 device_printf(sc->dev, 879 "Duplicated memory range found " 880 "in DT\n"); 881 return (ENXIO); 882 } 883 sc->mem_range = ranges[i]; 884 } 885 } 886 } 887 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 888 || (sc->pref_mem_range.size == 0)) { 889 device_printf(sc->dev, 890 " Not all required ranges are found in DT\n"); 891 return (ENXIO); 892 } 893 return (0); 894 } 895 896 /* 897 * Hardware config. 898 */ 899 static int 900 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 901 struct tegra_pcib_port *port) 902 { 903 uint32_t reg; 904 int i; 905 906 907 /* Setup link detection. */ 908 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 909 RP_PRIV_MISC, 4); 910 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 911 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 912 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 913 RP_PRIV_MISC, reg, 4); 914 915 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 916 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 917 RP_VEND_XP, 4); 918 if (reg & RP_VEND_XP_DL_UP) 919 break; 920 921 } 922 if (i <= 0) 923 return (ETIMEDOUT); 924 925 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 926 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 927 RP_LINK_CONTROL_STATUS, 4); 928 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 929 break; 930 931 } 932 if (i <= 0) 933 return (ETIMEDOUT); 934 return (0); 935 } 936 937 static void 938 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 939 { 940 struct tegra_pcib_port *port; 941 uint32_t reg; 942 int rv; 943 944 port = sc->ports[port_num]; 945 946 /* Put port to reset. */ 947 reg = AFI_RD4(sc, port->afi_pex_ctrl); 948 reg &= ~AFI_PEX_CTRL_RST_L; 949 AFI_WR4(sc, port->afi_pex_ctrl, reg); 950 AFI_RD4(sc, port->afi_pex_ctrl); 951 DELAY(10); 952 953 /* Enable clocks. */ 954 reg |= AFI_PEX_CTRL_REFCLK_EN; 955 reg |= AFI_PEX_CTRL_CLKREQ_EN; 956 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 957 AFI_WR4(sc, port->afi_pex_ctrl, reg); 958 AFI_RD4(sc, port->afi_pex_ctrl); 959 DELAY(100); 960 961 /* Release reset. */ 962 reg |= AFI_PEX_CTRL_RST_L; 963 AFI_WR4(sc, port->afi_pex_ctrl, reg); 964 965 rv = tegra_pcib_wait_for_link(sc, port); 966 if (bootverbose) 967 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 968 port->port_idx, port->num_lanes, 969 port->num_lanes > 1 ? "s": "", 970 rv == 0 ? "up": "down"); 971 } 972 973 974 static void 975 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 976 { 977 struct tegra_pcib_port *port; 978 uint32_t reg; 979 980 port = sc->ports[port_num]; 981 982 /* Put port to reset. */ 983 reg = AFI_RD4(sc, port->afi_pex_ctrl); 984 reg &= ~AFI_PEX_CTRL_RST_L; 985 AFI_WR4(sc, port->afi_pex_ctrl, reg); 986 AFI_RD4(sc, port->afi_pex_ctrl); 987 DELAY(10); 988 989 /* Disable clocks. */ 990 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 991 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 992 AFI_WR4(sc, port->afi_pex_ctrl, reg); 993 994 if (bootverbose) 995 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 996 port->port_idx, port->num_lanes, 997 port->num_lanes > 1 ? "s": ""); 998 } 999 1000 static void 1001 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1002 uint64_t fpci, uint32_t size, int is_memory) 1003 { 1004 uint32_t fpci_reg; 1005 uint32_t axi_reg; 1006 uint32_t size_reg; 1007 1008 axi_reg = axi & ~0xFFF; 1009 size_reg = size >> 12; 1010 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1011 fpci_reg |= is_memory ? 0x1 : 0x0; 1012 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1013 AFI_WR4(sc, bars[bar].size, size_reg); 1014 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1015 } 1016 1017 static int 1018 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1019 { 1020 int rv; 1021 int i; 1022 uint32_t reg; 1023 1024 rv = tegra_pcib_enable_fdt_resources(sc); 1025 if (rv != 0) { 1026 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1027 return (rv); 1028 } 1029 /* Enable PLLE control. */ 1030 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1031 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1032 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1033 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1034 1035 /* Set bias pad. */ 1036 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1037 1038 /* Configure mode and ports. */ 1039 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1040 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1041 if (sc->lanes_cfg == 0x14) { 1042 if (bootverbose) 1043 device_printf(sc->dev, 1044 "Using x1,x4 configuration\n"); 1045 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1046 } else if (sc->lanes_cfg == 0x12) { 1047 if (bootverbose) 1048 device_printf(sc->dev, 1049 "Using x1,x2 configuration\n"); 1050 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1051 } else { 1052 device_printf(sc->dev, 1053 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1054 } 1055 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1056 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1057 if ((sc->ports[i] != NULL)) 1058 reg &= 1059 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1060 } 1061 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1062 1063 /* Enable Gen2 support. */ 1064 reg = AFI_RD4(sc, AFI_FUSE); 1065 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1066 AFI_WR4(sc, AFI_FUSE, reg); 1067 1068 /* Enable PCIe phy. */ 1069 rv = phy_enable(sc->dev, sc->phy); 1070 if (rv != 0) { 1071 device_printf(sc->dev, "Cannot enable phy\n"); 1072 return (rv); 1073 } 1074 1075 rv = hwreset_deassert(sc->hwreset_pcie_x); 1076 if (rv != 0) { 1077 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1078 return (rv); 1079 } 1080 1081 /* Enable config space. */ 1082 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1083 reg |= AFI_CONFIGURATION_EN_FPCI; 1084 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1085 1086 /* Enable AFI errors. */ 1087 reg = 0; 1088 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1089 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1090 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1091 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1092 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1093 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1094 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1095 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1096 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1097 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1098 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1099 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1100 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1101 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1102 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1103 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1104 1105 /* Enable INT, disable MSI. */ 1106 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1107 1108 /* Mask all FPCI errors. */ 1109 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1110 1111 /* Setup AFI translation windows. */ 1112 /* BAR 0 - type 1 extended configuration. */ 1113 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1114 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1115 1116 /* BAR 1 - downstream I/O. */ 1117 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1118 sc->io_range.size, 0); 1119 1120 /* BAR 2 - downstream prefetchable memory 1:1. */ 1121 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1122 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1123 1124 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1125 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1126 sc->mem_range.host, sc->mem_range.size, 1); 1127 1128 /* BAR 3-8 clear. */ 1129 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1130 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1131 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1132 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1133 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1134 1135 /* MSI BAR - clear. */ 1136 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1137 return(0); 1138 } 1139 1140 static int 1141 tegra_pcib_probe(device_t dev) 1142 { 1143 if (!ofw_bus_status_okay(dev)) 1144 return (ENXIO); 1145 1146 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1147 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1148 return (BUS_PROBE_DEFAULT); 1149 } 1150 return (ENXIO); 1151 } 1152 1153 static int 1154 tegra_pcib_attach(device_t dev) 1155 { 1156 struct tegra_pcib_softc *sc; 1157 phandle_t node; 1158 int rv; 1159 int rid; 1160 struct tegra_pcib_port *port; 1161 int i; 1162 1163 sc = device_get_softc(dev); 1164 sc->dev = dev; 1165 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1166 1167 node = ofw_bus_get_node(dev); 1168 1169 rv = tegra_pcib_parse_fdt_resources(sc, node); 1170 if (rv != 0) { 1171 device_printf(dev, "Cannot get FDT resources\n"); 1172 return (rv); 1173 } 1174 1175 /* Allocate bus_space resources. */ 1176 rid = 0; 1177 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1178 RF_ACTIVE); 1179 if (sc->pads_mem_res == NULL) { 1180 device_printf(dev, "Cannot allocate PADS register\n"); 1181 rv = ENXIO; 1182 goto out; 1183 } 1184 /* 1185 * XXX - FIXME 1186 * tag for config space is not filled when RF_ALLOCATED flag is used. 1187 */ 1188 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1189 1190 rid = 1; 1191 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1192 RF_ACTIVE); 1193 if (sc->afi_mem_res == NULL) { 1194 device_printf(dev, "Cannot allocate AFI register\n"); 1195 rv = ENXIO; 1196 goto out; 1197 } 1198 1199 rid = 2; 1200 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1201 RF_ALLOCATED); 1202 if (sc->cfg_mem_res == NULL) { 1203 device_printf(dev, "Cannot allocate config space memory\n"); 1204 rv = ENXIO; 1205 goto out; 1206 } 1207 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1208 1209 1210 /* Map RP slots */ 1211 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1212 if (sc->ports[i] == NULL) 1213 continue; 1214 port = sc->ports[i]; 1215 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1216 port->rp_size, 0, &port->cfg_handle); 1217 if (rv != 0) { 1218 device_printf(sc->dev, "Cannot allocate memory for " 1219 "port: %d\n", i); 1220 rv = ENXIO; 1221 goto out; 1222 } 1223 } 1224 1225 /* 1226 * Get PCI interrupt 1227 */ 1228 rid = 0; 1229 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1230 RF_ACTIVE | RF_SHAREABLE); 1231 if (sc->irq_res == NULL) { 1232 device_printf(dev, "Cannot allocate IRQ resources\n"); 1233 rv = ENXIO; 1234 goto out; 1235 } 1236 1237 rid = 1; 1238 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1239 RF_ACTIVE); 1240 if (sc->irq_res == NULL) { 1241 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1242 rv = ENXIO; 1243 goto out; 1244 } 1245 1246 sc->ofw_pci.sc_range_mask = 0x3; 1247 rv = ofw_pci_init(dev); 1248 if (rv != 0) 1249 goto out; 1250 1251 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1252 sc->ofw_pci.sc_nrange); 1253 if (rv != 0) 1254 goto out; 1255 1256 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1257 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1258 device_printf(dev, "cannot setup interrupt handler\n"); 1259 rv = ENXIO; 1260 goto out; 1261 } 1262 1263 /* 1264 * Enable PCIE device. 1265 */ 1266 rv = tegra_pcib_enable(sc); 1267 if (rv != 0) 1268 goto out; 1269 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1270 if (sc->ports[i] == NULL) 1271 continue; 1272 if (sc->ports[i]->enabled) 1273 tegra_pcib_port_enable(sc, i); 1274 else 1275 tegra_pcib_port_disable(sc, i); 1276 } 1277 1278 device_add_child(dev, "pci", -1); 1279 1280 return (bus_generic_attach(dev)); 1281 1282 out: 1283 1284 return (rv); 1285 } 1286 1287 1288 static device_method_t tegra_pcib_methods[] = { 1289 /* Device interface */ 1290 DEVMETHOD(device_probe, tegra_pcib_probe), 1291 DEVMETHOD(device_attach, tegra_pcib_attach), 1292 1293 /* Bus interface */ 1294 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1295 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1296 1297 /* pcib interface */ 1298 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1299 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1300 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1301 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1302 1303 #if defined(TEGRA_PCI_MSI) 1304 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1305 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1306 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1307 #endif 1308 1309 /* OFW bus interface */ 1310 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1311 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1312 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1313 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1314 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1315 1316 DEVMETHOD_END 1317 }; 1318 1319 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1320 sizeof(struct tegra_pcib_softc), ofw_pci_driver); 1321 devclass_t pcib_devclass; 1322 DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 0, 0); 1323