1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/intr.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_extern.h> 49 #include <vm/vm_kern.h> 50 #include <vm/pmap.h> 51 52 #include <dev/extres/clk/clk.h> 53 #include <dev/extres/hwreset/hwreset.h> 54 #include <dev/extres/phy/phy.h> 55 #include <dev/extres/regulator/regulator.h> 56 #include <dev/fdt/fdt_common.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 #include <dev/ofw/ofw_pci.h> 60 #include <dev/ofw/ofwpci.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcib_private.h> 64 65 #include <machine/resource.h> 66 #include <machine/bus.h> 67 68 #include <arm/nvidia/tegra_pmc.h> 69 70 #include "ofw_bus_if.h" 71 #include "msi_if.h" 72 #include "pcib_if.h" 73 #include "pic_if.h" 74 75 76 #define AFI_AXI_BAR0_SZ 0x000 77 #define AFI_AXI_BAR1_SZ 0x004 78 #define AFI_AXI_BAR2_SZ 0x008 79 #define AFI_AXI_BAR3_SZ 0x00c 80 #define AFI_AXI_BAR4_SZ 0x010 81 #define AFI_AXI_BAR5_SZ 0x014 82 #define AFI_AXI_BAR0_START 0x018 83 #define AFI_AXI_BAR1_START 0x01c 84 #define AFI_AXI_BAR2_START 0x020 85 #define AFI_AXI_BAR3_START 0x024 86 #define AFI_AXI_BAR4_START 0x028 87 #define AFI_AXI_BAR5_START 0x02c 88 #define AFI_FPCI_BAR0 0x030 89 #define AFI_FPCI_BAR1 0x034 90 #define AFI_FPCI_BAR2 0x038 91 #define AFI_FPCI_BAR3 0x03c 92 #define AFI_FPCI_BAR4 0x040 93 #define AFI_FPCI_BAR5 0x044 94 #define AFI_MSI_BAR_SZ 0x060 95 #define AFI_MSI_FPCI_BAR_ST 0x064 96 #define AFI_MSI_AXI_BAR_ST 0x068 97 #define AFI_MSI_VEC(x) (0x06c + 4 * (x)) 98 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x)) 99 #define AFI_MSI_INTR_IN_REG 32 100 #define AFI_MSI_REGS 8 101 102 #define AFI_CONFIGURATION 0x0ac 103 #define AFI_CONFIGURATION_EN_FPCI (1 << 0) 104 105 #define AFI_FPCI_ERROR_MASKS 0x0b0 106 #define AFI_INTR_MASK 0x0b4 107 #define AFI_INTR_MASK_MSI_MASK (1 << 8) 108 #define AFI_INTR_MASK_INT_MASK (1 << 0) 109 110 #define AFI_INTR_CODE 0x0b8 111 #define AFI_INTR_CODE_MASK 0xf 112 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1 113 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2 114 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3 115 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4 116 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5 117 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6 118 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7 119 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8 120 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9 121 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10 122 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11 123 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12 124 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13 125 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14 126 127 128 #define AFI_INTR_SIGNATURE 0x0bc 129 #define AFI_UPPER_FPCI_ADDRESS 0x0c0 130 #define AFI_SM_INTR_ENABLE 0x0c4 131 #define AFI_SM_INTR_RP_DEASSERT (1 << 14) 132 #define AFI_SM_INTR_RP_ASSERT (1 << 13) 133 #define AFI_SM_INTR_HOTPLUG (1 << 12) 134 #define AFI_SM_INTR_PME (1 << 11) 135 #define AFI_SM_INTR_FATAL_ERROR (1 << 10) 136 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9) 137 #define AFI_SM_INTR_CORR_ERROR (1 << 8) 138 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7) 139 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6) 140 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5) 141 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4) 142 #define AFI_SM_INTR_INTD_ASSERT (1 << 3) 143 #define AFI_SM_INTR_INTC_ASSERT (1 << 2) 144 #define AFI_SM_INTR_INTB_ASSERT (1 << 1) 145 #define AFI_SM_INTR_INTA_ASSERT (1 << 0) 146 147 #define AFI_AFI_INTR_ENABLE 0x0c8 148 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code)) 149 150 #define AFI_PCIE_CONFIG 0x0f8 151 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) 152 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6 153 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20) 154 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20) 155 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20) 156 157 #define AFI_FUSE 0x104 158 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) 159 160 #define AFI_PEX0_CTRL 0x110 161 #define AFI_PEX1_CTRL 0x118 162 #define AFI_PEX2_CTRL 0x128 163 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4) 164 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) 165 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) 166 #define AFI_PEX_CTRL_RST_L (1 << 0) 167 168 #define AFI_AXI_BAR6_SZ 0x134 169 #define AFI_AXI_BAR7_SZ 0x138 170 #define AFI_AXI_BAR8_SZ 0x13c 171 #define AFI_AXI_BAR6_START 0x140 172 #define AFI_AXI_BAR7_START 0x144 173 #define AFI_AXI_BAR8_START 0x148 174 #define AFI_FPCI_BAR6 0x14c 175 #define AFI_FPCI_BAR7 0x150 176 #define AFI_FPCI_BAR8 0x154 177 #define AFI_PLLE_CONTROL 0x160 178 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9) 179 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8) 180 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1) 181 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0) 182 183 #define AFI_PEXBIAS_CTRL 0x168 184 185 /* FPCI Address space */ 186 #define FPCI_MAP_IO 0xfdfc000000ULL 187 #define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL 188 #define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL 189 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL 190 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL 191 192 /* Configuration space */ 193 #define RP_VEND_XP 0x00000F00 194 #define RP_VEND_XP_DL_UP (1 << 30) 195 196 #define RP_PRIV_MISC 0x00000FE0 197 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0) 198 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0) 199 200 #define RP_LINK_CONTROL_STATUS 0x00000090 201 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000 202 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 203 204 /* Wait 50 ms (per port) for link. */ 205 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000 206 207 #define TEGRA_PCIB_MSI_ENABLE 208 209 #define DEBUG 210 #ifdef DEBUG 211 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 212 #else 213 #define debugf(fmt, args...) 214 #endif 215 216 /* 217 * Configuration space format: 218 * [27:24] extended register 219 * [23:16] bus 220 * [15:11] slot (device) 221 * [10: 8] function 222 * [ 7: 0] register 223 */ 224 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24) 225 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 226 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 227 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8) 228 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff) 229 230 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v)) 231 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r)) 232 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v)) 233 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r)) 234 235 static struct { 236 bus_size_t axi_start; 237 bus_size_t fpci_start; 238 bus_size_t size; 239 } bars[] = { 240 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */ 241 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */ 242 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */ 243 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */ 244 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */ 245 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */ 246 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */ 247 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */ 248 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */ 249 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */ 250 }; 251 252 /* Compatible devices. */ 253 static struct ofw_compat_data compat_data[] = { 254 {"nvidia,tegra124-pcie", 1}, 255 {NULL, 0}, 256 }; 257 258 #define TEGRA_FLAG_MSI_USED 0x0001 259 struct tegra_pcib_irqsrc { 260 struct intr_irqsrc isrc; 261 u_int irq; 262 u_int flags; 263 }; 264 265 struct tegra_pcib_port { 266 int enabled; 267 int port_idx; /* chip port index */ 268 int num_lanes; /* number of lanes */ 269 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ 270 phy_t phy; /* port phy */ 271 272 /* Config space properties. */ 273 bus_addr_t rp_base_addr; /* PA of config window */ 274 bus_size_t rp_size; /* size of config window */ 275 bus_space_handle_t cfg_handle; /* handle of config window */ 276 }; 277 278 #define TEGRA_PCIB_MAX_PORTS 3 279 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS 280 struct tegra_pcib_softc { 281 struct ofw_pci_softc ofw_pci; 282 device_t dev; 283 struct mtx mtx; 284 struct resource *pads_mem_res; 285 struct resource *afi_mem_res; 286 struct resource *cfg_mem_res; 287 struct resource *irq_res; 288 struct resource *msi_irq_res; 289 void *intr_cookie; 290 void *msi_intr_cookie; 291 292 struct ofw_pci_range mem_range; 293 struct ofw_pci_range pref_mem_range; 294 struct ofw_pci_range io_range; 295 296 clk_t clk_pex; 297 clk_t clk_afi; 298 clk_t clk_pll_e; 299 clk_t clk_cml; 300 hwreset_t hwreset_pex; 301 hwreset_t hwreset_afi; 302 hwreset_t hwreset_pcie_x; 303 regulator_t supply_avddio_pex; 304 regulator_t supply_dvddio_pex; 305 regulator_t supply_avdd_pex_pll; 306 regulator_t supply_hvdd_pex; 307 regulator_t supply_hvdd_pex_pll_e; 308 regulator_t supply_vddio_pex_ctl; 309 regulator_t supply_avdd_pll_erefe; 310 311 vm_offset_t msi_page; /* VA of MSI page */ 312 bus_addr_t cfg_base_addr; /* base address of config */ 313 bus_size_t cfg_cur_offs; /* currently mapped window */ 314 bus_space_handle_t cfg_handle; /* handle of config window */ 315 bus_space_tag_t bus_tag; /* tag of config window */ 316 int lanes_cfg; 317 int num_ports; 318 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS]; 319 struct tegra_pcib_irqsrc *isrcs; 320 }; 321 322 static int 323 tegra_pcib_maxslots(device_t dev) 324 { 325 return (16); 326 } 327 328 static int 329 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin) 330 { 331 struct tegra_pcib_softc *sc; 332 u_int irq; 333 334 sc = device_get_softc(bus); 335 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); 336 device_printf(bus, "route pin %d for device %d.%d to %u\n", 337 pin, pci_get_slot(dev), pci_get_function(dev), 338 irq); 339 340 return (irq); 341 } 342 343 static int 344 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot, 345 u_int func, u_int reg) 346 { 347 bus_size_t offs; 348 int rv; 349 350 offs = sc->cfg_base_addr; 351 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) | 352 PCI_CFG_EXT_REG(reg); 353 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) 354 return (0); 355 if (sc->cfg_handle != 0) 356 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); 357 358 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle); 359 if (rv != 0) 360 device_printf(sc->dev, "Cannot map config space\n"); 361 else 362 sc->cfg_cur_offs = offs; 363 return (rv); 364 } 365 366 static uint32_t 367 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 368 u_int reg, int bytes) 369 { 370 struct tegra_pcib_softc *sc; 371 bus_space_handle_t hndl; 372 uint32_t off; 373 uint32_t val; 374 int rv, i; 375 376 sc = device_get_softc(dev); 377 if (bus == 0) { 378 if (func != 0) 379 return (0xFFFFFFFF); 380 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 381 if ((sc->ports[i] != NULL) && 382 (sc->ports[i]->port_idx == slot)) { 383 hndl = sc->ports[i]->cfg_handle; 384 off = reg & 0xFFF; 385 break; 386 } 387 } 388 if (i >= TEGRA_PCIB_MAX_PORTS) 389 return (0xFFFFFFFF); 390 } else { 391 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 392 if (rv != 0) 393 return (0xFFFFFFFF); 394 hndl = sc->cfg_handle; 395 off = PCI_CFG_BASE_REG(reg); 396 } 397 398 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 399 switch (bytes) { 400 case 4: 401 break; 402 case 2: 403 if (off & 3) 404 val >>= 16; 405 val &= 0xffff; 406 break; 407 case 1: 408 val >>= ((off & 3) << 3); 409 val &= 0xff; 410 break; 411 } 412 return val; 413 } 414 415 static void 416 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 417 u_int reg, uint32_t val, int bytes) 418 { 419 struct tegra_pcib_softc *sc; 420 bus_space_handle_t hndl; 421 uint32_t off; 422 uint32_t val2; 423 int rv, i; 424 425 sc = device_get_softc(dev); 426 if (bus == 0) { 427 if (func != 0) 428 return; 429 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 430 if ((sc->ports[i] != NULL) && 431 (sc->ports[i]->port_idx == slot)) { 432 hndl = sc->ports[i]->cfg_handle; 433 off = reg & 0xFFF; 434 break; 435 } 436 } 437 if (i >= TEGRA_PCIB_MAX_PORTS) 438 return; 439 } else { 440 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg); 441 if (rv != 0) 442 return; 443 hndl = sc->cfg_handle; 444 off = PCI_CFG_BASE_REG(reg); 445 } 446 447 switch (bytes) { 448 case 4: 449 bus_space_write_4(sc->bus_tag, hndl, off, val); 450 break; 451 case 2: 452 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 453 val2 &= ~(0xffff << ((off & 3) << 3)); 454 val2 |= ((val & 0xffff) << ((off & 3) << 3)); 455 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 456 break; 457 case 1: 458 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); 459 val2 &= ~(0xff << ((off & 3) << 3)); 460 val2 |= ((val & 0xff) << ((off & 3) << 3)); 461 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); 462 break; 463 } 464 } 465 466 static int tegra_pci_intr(void *arg) 467 { 468 struct tegra_pcib_softc *sc = arg; 469 uint32_t code, signature; 470 471 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; 472 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); 473 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); 474 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG) 475 return(FILTER_STRAY); 476 477 printf("tegra_pci_intr: code %x sig %x\n", code, signature); 478 return (FILTER_HANDLED); 479 } 480 481 /* ----------------------------------------------------------------------- 482 * 483 * PCI MSI interface 484 */ 485 static int 486 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount, 487 int *irqs) 488 { 489 phandle_t msi_parent; 490 491 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 492 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 493 NULL); 494 */ 495 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 496 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 497 irqs)); 498 } 499 500 static int 501 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs) 502 { 503 phandle_t msi_parent; 504 505 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 506 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 507 NULL); 508 */ 509 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 510 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 511 } 512 513 static int 514 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 515 uint32_t *data) 516 { 517 phandle_t msi_parent; 518 519 /* XXXX ofw_bus_msimap() don't works for Tegra DT. 520 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, 521 NULL); 522 */ 523 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci)); 524 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 525 } 526 527 #ifdef TEGRA_PCIB_MSI_ENABLE 528 529 /* -------------------------------------------------------------------------- 530 * 531 * Interrupts 532 * 533 */ 534 535 static inline void 536 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc, 537 struct tegra_pcib_irqsrc *tgi, uint32_t val) 538 { 539 uint32_t reg; 540 int offs, bit; 541 542 offs = tgi->irq / AFI_MSI_INTR_IN_REG; 543 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); 544 545 if (val != 0) 546 AFI_WR4(sc, AFI_MSI_VEC(offs), bit); 547 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs)); 548 if (val != 0) 549 reg |= bit; 550 else 551 reg &= ~bit; 552 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg); 553 } 554 555 static int 556 tegra_pcib_msi_intr(void *arg) 557 { 558 u_int irq, i, bit, reg; 559 struct tegra_pcib_softc *sc; 560 struct trapframe *tf; 561 struct tegra_pcib_irqsrc *tgi; 562 563 sc = (struct tegra_pcib_softc *)arg; 564 tf = curthread->td_intr_frame; 565 566 for (i = 0; i < AFI_MSI_REGS; i++) { 567 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 568 /* Handle one vector. */ 569 while (reg != 0) { 570 bit = ffs(reg) - 1; 571 /* Send EOI */ 572 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit); 573 irq = i * AFI_MSI_INTR_IN_REG + bit; 574 tgi = &sc->isrcs[irq]; 575 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 576 /* Disable stray. */ 577 tegra_pcib_isrc_mask(sc, tgi, 0); 578 device_printf(sc->dev, 579 "Stray irq %u disabled\n", irq); 580 } 581 reg = AFI_RD4(sc, AFI_MSI_VEC(i)); 582 } 583 } 584 return (FILTER_HANDLED); 585 } 586 587 static int 588 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc) 589 { 590 int error; 591 uint32_t irq; 592 const char *name; 593 594 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, 595 M_WAITOK | M_ZERO); 596 597 name = device_get_nameunit(sc->dev); 598 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) { 599 sc->isrcs[irq].irq = irq; 600 error = intr_isrc_register(&sc->isrcs[irq].isrc, 601 sc->dev, 0, "%s,%u", name, irq); 602 if (error != 0) 603 return (error); /* XXX deregister ISRCs */ 604 } 605 if (intr_msi_register(sc->dev, 606 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) 607 return (ENXIO); 608 609 return (0); 610 } 611 612 static int 613 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc) 614 { 615 616 /* 617 * There has not been established any procedure yet 618 * how to detach PIC from living system correctly. 619 */ 620 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 621 return (EBUSY); 622 } 623 624 625 static void 626 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc) 627 { 628 struct tegra_pcib_softc *sc; 629 struct tegra_pcib_irqsrc *tgi; 630 631 sc = device_get_softc(dev); 632 tgi = (struct tegra_pcib_irqsrc *)isrc; 633 tegra_pcib_isrc_mask(sc, tgi, 0); 634 } 635 636 static void 637 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc) 638 { 639 struct tegra_pcib_softc *sc; 640 struct tegra_pcib_irqsrc *tgi; 641 642 sc = device_get_softc(dev); 643 tgi = (struct tegra_pcib_irqsrc *)isrc; 644 tegra_pcib_isrc_mask(sc, tgi, 1); 645 } 646 647 /* MSI interrupts are edge trigered -> do nothing */ 648 static void 649 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc) 650 { 651 } 652 653 static void 654 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc) 655 { 656 } 657 658 static void 659 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 660 { 661 } 662 663 static int 664 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc, 665 struct resource *res, struct intr_map_data *data) 666 { 667 struct tegra_pcib_softc *sc; 668 struct tegra_pcib_irqsrc *tgi; 669 670 sc = device_get_softc(dev); 671 tgi = (struct tegra_pcib_irqsrc *)isrc; 672 673 if (data == NULL || data->type != INTR_MAP_DATA_MSI) 674 return (ENOTSUP); 675 676 if (isrc->isrc_handlers == 0) 677 tegra_pcib_msi_enable_intr(dev, isrc); 678 679 return (0); 680 } 681 682 static int 683 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 684 struct resource *res, struct intr_map_data *data) 685 { 686 struct tegra_pcib_softc *sc; 687 struct tegra_pcib_irqsrc *tgi; 688 689 sc = device_get_softc(dev); 690 tgi = (struct tegra_pcib_irqsrc *)isrc; 691 692 if (isrc->isrc_handlers == 0) 693 tegra_pcib_isrc_mask(sc, tgi, 0); 694 return (0); 695 } 696 697 698 static int 699 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount, 700 device_t *pic, struct intr_irqsrc **srcs) 701 { 702 struct tegra_pcib_softc *sc; 703 int i, irq, end_irq; 704 bool found; 705 706 KASSERT(powerof2(count), ("%s: bad count", __func__)); 707 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__)); 708 709 sc = device_get_softc(dev); 710 mtx_lock(&sc->mtx); 711 712 found = false; 713 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI && !found; irq++) { 714 /* Start on an aligned interrupt */ 715 if ((irq & (maxcount - 1)) != 0) 716 continue; 717 718 /* Assume we found a valid range until shown otherwise */ 719 found = true; 720 721 /* Check this range is valid */ 722 for (end_irq = irq; end_irq != irq + count - 1; end_irq++) { 723 /* No free interrupts */ 724 if (end_irq == (TEGRA_PCIB_MAX_MSI - 1)) { 725 found = false; 726 break; 727 } 728 729 /* This is already used */ 730 if ((sc->isrcs[irq].flags & TEGRA_FLAG_MSI_USED) == 731 TEGRA_FLAG_MSI_USED) { 732 found = false; 733 break; 734 } 735 } 736 } 737 738 /* Not enough interrupts were found */ 739 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { 740 mtx_unlock(&sc->mtx); 741 return (ENXIO); 742 } 743 744 for (i = 0; i < count; i++) { 745 /* Mark the interrupt as used */ 746 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; 747 748 } 749 mtx_unlock(&sc->mtx); 750 751 for (i = 0; i < count; i++) 752 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; 753 *pic = device_get_parent(dev); 754 return (0); 755 } 756 757 static int 758 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count, 759 struct intr_irqsrc **isrc) 760 { 761 struct tegra_pcib_softc *sc; 762 struct tegra_pcib_irqsrc *ti; 763 int i; 764 765 sc = device_get_softc(dev); 766 mtx_lock(&sc->mtx); 767 for (i = 0; i < count; i++) { 768 ti = (struct tegra_pcib_irqsrc *)isrc; 769 770 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, 771 ("%s: Trying to release an unused MSI-X interrupt", 772 __func__)); 773 774 ti->flags &= ~TEGRA_FLAG_MSI_USED; 775 mtx_unlock(&sc->mtx); 776 } 777 return (0); 778 } 779 780 static int 781 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, 782 uint64_t *addr, uint32_t *data) 783 { 784 struct tegra_pcib_softc *sc = device_get_softc(dev); 785 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc; 786 787 *addr = vtophys(sc->msi_page); 788 *data = ti->irq; 789 return (0); 790 } 791 #endif 792 793 /* ------------------------------------------------------------------- */ 794 static bus_size_t 795 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port) 796 { 797 if (port >= TEGRA_PCIB_MAX_PORTS) 798 panic("invalid port number: %d\n", port); 799 800 if (port == 0) 801 return (AFI_PEX0_CTRL); 802 else if (port == 1) 803 return (AFI_PEX1_CTRL); 804 else if (port == 2) 805 return (AFI_PEX2_CTRL); 806 else 807 panic("invalid port number: %d\n", port); 808 } 809 810 static int 811 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) 812 { 813 int rv; 814 815 rv = hwreset_assert(sc->hwreset_pcie_x); 816 if (rv != 0) { 817 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); 818 return (rv); 819 } 820 rv = hwreset_assert(sc->hwreset_afi); 821 if (rv != 0) { 822 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); 823 return (rv); 824 } 825 rv = hwreset_assert(sc->hwreset_pex); 826 if (rv != 0) { 827 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); 828 return (rv); 829 } 830 831 tegra_powergate_power_off(TEGRA_POWERGATE_PCX); 832 833 /* Power supplies. */ 834 rv = regulator_enable(sc->supply_avddio_pex); 835 if (rv != 0) { 836 device_printf(sc->dev, 837 "Cannot enable 'avddio_pex' regulator\n"); 838 return (rv); 839 } 840 rv = regulator_enable(sc->supply_dvddio_pex); 841 if (rv != 0) { 842 device_printf(sc->dev, 843 "Cannot enable 'dvddio_pex' regulator\n"); 844 return (rv); 845 } 846 rv = regulator_enable(sc->supply_avdd_pex_pll); 847 if (rv != 0) { 848 device_printf(sc->dev, 849 "Cannot enable 'avdd-pex-pll' regulator\n"); 850 return (rv); 851 } 852 rv = regulator_enable(sc->supply_hvdd_pex); 853 if (rv != 0) { 854 device_printf(sc->dev, 855 "Cannot enable 'hvdd-pex-supply' regulator\n"); 856 return (rv); 857 } 858 rv = regulator_enable(sc->supply_hvdd_pex_pll_e); 859 if (rv != 0) { 860 device_printf(sc->dev, 861 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n"); 862 return (rv); 863 } 864 rv = regulator_enable(sc->supply_vddio_pex_ctl); 865 if (rv != 0) { 866 device_printf(sc->dev, 867 "Cannot enable 'vddio-pex-ctl' regulator\n"); 868 return (rv); 869 } 870 rv = regulator_enable(sc->supply_avdd_pll_erefe); 871 if (rv != 0) { 872 device_printf(sc->dev, 873 "Cannot enable 'avdd-pll-erefe-supply' regulator\n"); 874 return (rv); 875 } 876 877 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, 878 sc->clk_pex, sc->hwreset_pex); 879 if (rv != 0) { 880 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); 881 return (rv); 882 } 883 884 rv = hwreset_deassert(sc->hwreset_afi); 885 if (rv != 0) { 886 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); 887 return (rv); 888 } 889 890 rv = clk_enable(sc->clk_afi); 891 if (rv != 0) { 892 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); 893 return (rv); 894 } 895 rv = clk_enable(sc->clk_cml); 896 if (rv != 0) { 897 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 898 return (rv); 899 } 900 rv = clk_enable(sc->clk_pll_e); 901 if (rv != 0) { 902 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); 903 return (rv); 904 } 905 return (0); 906 } 907 908 static struct tegra_pcib_port * 909 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node) 910 { 911 struct tegra_pcib_port *port; 912 uint32_t tmp[5]; 913 char tmpstr[6]; 914 int rv; 915 916 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK); 917 918 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr)); 919 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 || 920 strcmp(tmpstr, "ok") == 0) 921 port->enabled = 1; 922 else 923 port->enabled = 0; 924 925 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); 926 if (rv != sizeof(tmp)) { 927 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", 928 rv); 929 goto fail; 930 } 931 port->rp_base_addr = tmp[2]; 932 port->rp_size = tmp[4]; 933 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; 934 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { 935 device_printf(sc->dev, "Invalid port index: %d\n", 936 port->port_idx); 937 goto fail; 938 } 939 /* XXX - TODO: 940 * Implement proper function for parsing pci "reg" property: 941 * - it have PCI bus format 942 * - its relative to matching "assigned-addresses" 943 */ 944 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp)); 945 if (rv != sizeof(tmp)) { 946 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); 947 goto fail; 948 } 949 port->rp_base_addr += tmp[2]; 950 951 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, 952 sizeof(port->num_lanes)); 953 if (rv != sizeof(port->num_lanes)) { 954 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", 955 rv); 956 goto fail; 957 } 958 if (port->num_lanes > 4) { 959 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 960 port->num_lanes); 961 goto fail; 962 } 963 964 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 965 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 966 967 /* Phy. */ 968 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 969 if (rv != 0) { 970 device_printf(sc->dev, 971 "Cannot get 'pcie-0' phy for port %d\n", 972 port->port_idx); 973 goto fail; 974 } 975 976 return (port); 977 fail: 978 free(port, M_DEVBUF); 979 return (NULL); 980 } 981 982 983 static int 984 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node) 985 { 986 phandle_t child; 987 struct tegra_pcib_port *port; 988 int rv; 989 990 /* Power supplies. */ 991 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply", 992 &sc->supply_avddio_pex); 993 if (rv != 0) { 994 device_printf(sc->dev, 995 "Cannot get 'avddio-pex' regulator\n"); 996 return (ENXIO); 997 } 998 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply", 999 &sc->supply_dvddio_pex); 1000 if (rv != 0) { 1001 device_printf(sc->dev, 1002 "Cannot get 'dvddio-pex' regulator\n"); 1003 return (ENXIO); 1004 } 1005 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply", 1006 &sc->supply_avdd_pex_pll); 1007 if (rv != 0) { 1008 device_printf(sc->dev, 1009 "Cannot get 'avdd-pex-pll' regulator\n"); 1010 return (ENXIO); 1011 } 1012 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply", 1013 &sc->supply_hvdd_pex); 1014 if (rv != 0) { 1015 device_printf(sc->dev, 1016 "Cannot get 'hvdd-pex' regulator\n"); 1017 return (ENXIO); 1018 } 1019 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply", 1020 &sc->supply_hvdd_pex_pll_e); 1021 if (rv != 0) { 1022 device_printf(sc->dev, 1023 "Cannot get 'hvdd-pex-pll-e' regulator\n"); 1024 return (ENXIO); 1025 } 1026 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply", 1027 &sc->supply_vddio_pex_ctl); 1028 if (rv != 0) { 1029 device_printf(sc->dev, 1030 "Cannot get 'vddio-pex-ctl' regulator\n"); 1031 return (ENXIO); 1032 } 1033 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply", 1034 &sc->supply_avdd_pll_erefe); 1035 if (rv != 0) { 1036 device_printf(sc->dev, 1037 "Cannot get 'avdd-pll-erefe' regulator\n"); 1038 return (ENXIO); 1039 } 1040 1041 /* Resets. */ 1042 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); 1043 if (rv != 0) { 1044 device_printf(sc->dev, "Cannot get 'pex' reset\n"); 1045 return (ENXIO); 1046 } 1047 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); 1048 if (rv != 0) { 1049 device_printf(sc->dev, "Cannot get 'afi' reset\n"); 1050 return (ENXIO); 1051 } 1052 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); 1053 if (rv != 0) { 1054 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); 1055 return (ENXIO); 1056 } 1057 1058 /* Clocks. */ 1059 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); 1060 if (rv != 0) { 1061 device_printf(sc->dev, "Cannot get 'pex' clock\n"); 1062 return (ENXIO); 1063 } 1064 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); 1065 if (rv != 0) { 1066 device_printf(sc->dev, "Cannot get 'afi' clock\n"); 1067 return (ENXIO); 1068 } 1069 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 1070 if (rv != 0) { 1071 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 1072 return (ENXIO); 1073 } 1074 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1075 if (rv != 0) { 1076 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1077 return (ENXIO); 1078 } 1079 1080 /* Ports */ 1081 sc->num_ports = 0; 1082 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1083 port = tegra_pcib_parse_port(sc, child); 1084 if (port == NULL) { 1085 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1086 return (ENXIO); 1087 } 1088 sc->ports[sc->num_ports++] = port; 1089 } 1090 1091 return (0); 1092 } 1093 1094 static int 1095 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc, 1096 struct ofw_pci_range *ranges, int nranges) 1097 { 1098 int i; 1099 1100 for (i = 2; i < nranges; i++) { 1101 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1102 OFW_PCI_PHYS_HI_SPACE_IO) { 1103 if (sc->io_range.size != 0) { 1104 device_printf(sc->dev, 1105 "Duplicated IO range found in DT\n"); 1106 return (ENXIO); 1107 } 1108 sc->io_range = ranges[i]; 1109 } 1110 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 1111 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 1112 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 1113 if (sc->pref_mem_range.size != 0) { 1114 device_printf(sc->dev, 1115 "Duplicated memory range found " 1116 "in DT\n"); 1117 return (ENXIO); 1118 } 1119 sc->pref_mem_range = ranges[i]; 1120 } else { 1121 if (sc->mem_range.size != 0) { 1122 device_printf(sc->dev, 1123 "Duplicated memory range found " 1124 "in DT\n"); 1125 return (ENXIO); 1126 } 1127 sc->mem_range = ranges[i]; 1128 } 1129 } 1130 } 1131 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) 1132 || (sc->pref_mem_range.size == 0)) { 1133 device_printf(sc->dev, 1134 " Not all required ranges are found in DT\n"); 1135 return (ENXIO); 1136 } 1137 return (0); 1138 } 1139 1140 /* 1141 * Hardware config. 1142 */ 1143 static int 1144 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc, 1145 struct tegra_pcib_port *port) 1146 { 1147 uint32_t reg; 1148 int i; 1149 1150 1151 /* Setup link detection. */ 1152 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1153 RP_PRIV_MISC, 4); 1154 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT; 1155 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT; 1156 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, 1157 RP_PRIV_MISC, reg, 4); 1158 1159 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1160 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1161 RP_VEND_XP, 4); 1162 if (reg & RP_VEND_XP_DL_UP) 1163 break; 1164 DELAY(1); 1165 1166 } 1167 if (i <= 0) 1168 return (ETIMEDOUT); 1169 1170 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { 1171 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, 1172 RP_LINK_CONTROL_STATUS, 4); 1173 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE) 1174 break; 1175 1176 DELAY(1); 1177 } 1178 if (i <= 0) 1179 return (ETIMEDOUT); 1180 return (0); 1181 } 1182 1183 static void 1184 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num) 1185 { 1186 struct tegra_pcib_port *port; 1187 uint32_t reg; 1188 int rv; 1189 1190 port = sc->ports[port_num]; 1191 1192 /* Put port to reset. */ 1193 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1194 reg &= ~AFI_PEX_CTRL_RST_L; 1195 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1196 AFI_RD4(sc, port->afi_pex_ctrl); 1197 DELAY(10); 1198 1199 /* Enable clocks. */ 1200 reg |= AFI_PEX_CTRL_REFCLK_EN; 1201 reg |= AFI_PEX_CTRL_CLKREQ_EN; 1202 reg |= AFI_PEX_CTRL_OVERRIDE_EN; 1203 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1204 AFI_RD4(sc, port->afi_pex_ctrl); 1205 DELAY(100); 1206 1207 /* Release reset. */ 1208 reg |= AFI_PEX_CTRL_RST_L; 1209 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1210 1211 rv = tegra_pcib_wait_for_link(sc, port); 1212 if (bootverbose) 1213 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", 1214 port->port_idx, port->num_lanes, 1215 port->num_lanes > 1 ? "s": "", 1216 rv == 0 ? "up": "down"); 1217 } 1218 1219 1220 static void 1221 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num) 1222 { 1223 struct tegra_pcib_port *port; 1224 uint32_t reg; 1225 1226 port = sc->ports[port_num]; 1227 1228 /* Put port to reset. */ 1229 reg = AFI_RD4(sc, port->afi_pex_ctrl); 1230 reg &= ~AFI_PEX_CTRL_RST_L; 1231 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1232 AFI_RD4(sc, port->afi_pex_ctrl); 1233 DELAY(10); 1234 1235 /* Disable clocks. */ 1236 reg &= ~AFI_PEX_CTRL_CLKREQ_EN; 1237 reg &= ~AFI_PEX_CTRL_REFCLK_EN; 1238 AFI_WR4(sc, port->afi_pex_ctrl, reg); 1239 1240 if (bootverbose) 1241 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", 1242 port->port_idx, port->num_lanes, 1243 port->num_lanes > 1 ? "s": ""); 1244 } 1245 1246 static void 1247 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi, 1248 uint64_t fpci, uint32_t size, int is_memory) 1249 { 1250 uint32_t fpci_reg; 1251 uint32_t axi_reg; 1252 uint32_t size_reg; 1253 1254 axi_reg = axi & ~0xFFF; 1255 size_reg = size >> 12; 1256 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF; 1257 fpci_reg |= is_memory ? 0x1 : 0x0; 1258 AFI_WR4(sc, bars[bar].axi_start, axi_reg); 1259 AFI_WR4(sc, bars[bar].size, size_reg); 1260 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg); 1261 } 1262 1263 static int 1264 tegra_pcib_enable(struct tegra_pcib_softc *sc) 1265 { 1266 int rv; 1267 int i; 1268 uint32_t reg; 1269 1270 rv = tegra_pcib_enable_fdt_resources(sc); 1271 if (rv != 0) { 1272 device_printf(sc->dev, "Cannot enable FDT resources\n"); 1273 return (rv); 1274 } 1275 /* Enable PLLE control. */ 1276 reg = AFI_RD4(sc, AFI_PLLE_CONTROL); 1277 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; 1278 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; 1279 AFI_WR4(sc, AFI_PLLE_CONTROL, reg); 1280 1281 /* Set bias pad. */ 1282 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0); 1283 1284 /* Configure mode and ports. */ 1285 reg = AFI_RD4(sc, AFI_PCIE_CONFIG); 1286 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK; 1287 if (sc->lanes_cfg == 0x14) { 1288 if (bootverbose) 1289 device_printf(sc->dev, 1290 "Using x1,x4 configuration\n"); 1291 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1; 1292 } else if (sc->lanes_cfg == 0x12) { 1293 if (bootverbose) 1294 device_printf(sc->dev, 1295 "Using x1,x2 configuration\n"); 1296 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1; 1297 } else { 1298 device_printf(sc->dev, 1299 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); 1300 } 1301 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL; 1302 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1303 if ((sc->ports[i] != NULL)) 1304 reg &= 1305 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); 1306 } 1307 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1308 1309 /* Enable Gen2 support. */ 1310 reg = AFI_RD4(sc, AFI_FUSE); 1311 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1312 AFI_WR4(sc, AFI_FUSE, reg); 1313 1314 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1315 if (sc->ports[i] != NULL) { 1316 rv = phy_enable(sc->dev, sc->ports[i]->phy); 1317 if (rv != 0) { 1318 device_printf(sc->dev, 1319 "Cannot enable phy for port %d\n", 1320 sc->ports[i]->port_idx); 1321 return (rv); 1322 } 1323 } 1324 } 1325 1326 1327 rv = hwreset_deassert(sc->hwreset_pcie_x); 1328 if (rv != 0) { 1329 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1330 return (rv); 1331 } 1332 1333 /* Enable config space. */ 1334 reg = AFI_RD4(sc, AFI_CONFIGURATION); 1335 reg |= AFI_CONFIGURATION_EN_FPCI; 1336 AFI_WR4(sc, AFI_CONFIGURATION, reg); 1337 1338 /* Enable AFI errors. */ 1339 reg = 0; 1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR); 1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR); 1342 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR); 1343 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR); 1344 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR); 1345 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG); 1346 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR); 1347 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR); 1348 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT); 1349 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE); 1350 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE); 1351 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE); 1352 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE); 1353 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR); 1354 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg); 1355 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff); 1356 1357 /* Enable INT, disable MSI. */ 1358 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK); 1359 1360 /* Mask all FPCI errors. */ 1361 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0); 1362 1363 /* Setup AFI translation windows. */ 1364 /* BAR 0 - type 1 extended configuration. */ 1365 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), 1366 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); 1367 1368 /* BAR 1 - downstream I/O. */ 1369 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, 1370 sc->io_range.size, 0); 1371 1372 /* BAR 2 - downstream prefetchable memory 1:1. */ 1373 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, 1374 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); 1375 1376 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ 1377 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, 1378 sc->mem_range.host, sc->mem_range.size, 1); 1379 1380 /* BAR 3-8 clear. */ 1381 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0); 1382 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0); 1383 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0); 1384 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0); 1385 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0); 1386 1387 /* MSI BAR - clear. */ 1388 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0); 1389 return(0); 1390 } 1391 1392 #ifdef TEGRA_PCIB_MSI_ENABLE 1393 static int 1394 tegra_pcib_attach_msi(device_t dev) 1395 { 1396 struct tegra_pcib_softc *sc; 1397 uint32_t reg; 1398 int i, rv; 1399 1400 sc = device_get_softc(dev); 1401 1402 sc->msi_page = kmem_alloc_contig(kernel_arena, PAGE_SIZE, M_WAITOK, 1403 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT); 1404 1405 /* MSI BAR */ 1406 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), 1407 PAGE_SIZE, 0); 1408 1409 /* Disble and clear all interrupts. */ 1410 for (i = 0; i < AFI_MSI_REGS; i++) { 1411 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0); 1412 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF); 1413 } 1414 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1415 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); 1416 if (rv != 0) { 1417 device_printf(dev, "cannot setup MSI interrupt handler\n"); 1418 rv = ENXIO; 1419 goto out; 1420 } 1421 1422 if (tegra_pcib_msi_attach(sc) != 0) { 1423 device_printf(dev, "WARNING: unable to attach PIC\n"); 1424 tegra_pcib_msi_detach(sc); 1425 goto out; 1426 } 1427 1428 /* Unmask MSI interrupt. */ 1429 reg = AFI_RD4(sc, AFI_INTR_MASK); 1430 reg |= AFI_INTR_MASK_MSI_MASK; 1431 AFI_WR4(sc, AFI_INTR_MASK, reg); 1432 1433 out: 1434 return (rv); 1435 } 1436 #endif 1437 1438 static int 1439 tegra_pcib_probe(device_t dev) 1440 { 1441 if (!ofw_bus_status_okay(dev)) 1442 return (ENXIO); 1443 1444 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 1445 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); 1446 return (BUS_PROBE_DEFAULT); 1447 } 1448 return (ENXIO); 1449 } 1450 1451 static int 1452 tegra_pcib_attach(device_t dev) 1453 { 1454 struct tegra_pcib_softc *sc; 1455 phandle_t node; 1456 int rv; 1457 int rid; 1458 struct tegra_pcib_port *port; 1459 int i; 1460 1461 sc = device_get_softc(dev); 1462 sc->dev = dev; 1463 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); 1464 1465 node = ofw_bus_get_node(dev); 1466 1467 rv = tegra_pcib_parse_fdt_resources(sc, node); 1468 if (rv != 0) { 1469 device_printf(dev, "Cannot get FDT resources\n"); 1470 return (rv); 1471 } 1472 1473 /* Allocate bus_space resources. */ 1474 rid = 0; 1475 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1476 RF_ACTIVE); 1477 if (sc->pads_mem_res == NULL) { 1478 device_printf(dev, "Cannot allocate PADS register\n"); 1479 rv = ENXIO; 1480 goto out; 1481 } 1482 /* 1483 * XXX - FIXME 1484 * tag for config space is not filled when RF_ALLOCATED flag is used. 1485 */ 1486 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); 1487 1488 rid = 1; 1489 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1490 RF_ACTIVE); 1491 if (sc->afi_mem_res == NULL) { 1492 device_printf(dev, "Cannot allocate AFI register\n"); 1493 rv = ENXIO; 1494 goto out; 1495 } 1496 1497 rid = 2; 1498 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1499 RF_ALLOCATED); 1500 if (sc->cfg_mem_res == NULL) { 1501 device_printf(dev, "Cannot allocate config space memory\n"); 1502 rv = ENXIO; 1503 goto out; 1504 } 1505 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); 1506 1507 1508 /* Map RP slots */ 1509 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1510 if (sc->ports[i] == NULL) 1511 continue; 1512 port = sc->ports[i]; 1513 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, 1514 port->rp_size, 0, &port->cfg_handle); 1515 if (rv != 0) { 1516 device_printf(sc->dev, "Cannot allocate memory for " 1517 "port: %d\n", i); 1518 rv = ENXIO; 1519 goto out; 1520 } 1521 } 1522 1523 /* 1524 * Get PCI interrupt 1525 */ 1526 rid = 0; 1527 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1528 RF_ACTIVE | RF_SHAREABLE); 1529 if (sc->irq_res == NULL) { 1530 device_printf(dev, "Cannot allocate IRQ resources\n"); 1531 rv = ENXIO; 1532 goto out; 1533 } 1534 1535 rid = 1; 1536 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1537 RF_ACTIVE); 1538 if (sc->irq_res == NULL) { 1539 device_printf(dev, "Cannot allocate MSI IRQ resources\n"); 1540 rv = ENXIO; 1541 goto out; 1542 } 1543 1544 sc->ofw_pci.sc_range_mask = 0x3; 1545 rv = ofw_pci_init(dev); 1546 if (rv != 0) 1547 goto out; 1548 1549 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, 1550 sc->ofw_pci.sc_nrange); 1551 if (rv != 0) 1552 goto out; 1553 1554 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 1555 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { 1556 device_printf(dev, "cannot setup interrupt handler\n"); 1557 rv = ENXIO; 1558 goto out; 1559 } 1560 1561 /* 1562 * Enable PCIE device. 1563 */ 1564 rv = tegra_pcib_enable(sc); 1565 if (rv != 0) 1566 goto out; 1567 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1568 if (sc->ports[i] == NULL) 1569 continue; 1570 if (sc->ports[i]->enabled) 1571 tegra_pcib_port_enable(sc, i); 1572 else 1573 tegra_pcib_port_disable(sc, i); 1574 } 1575 1576 #ifdef TEGRA_PCIB_MSI_ENABLE 1577 rv = tegra_pcib_attach_msi(dev); 1578 if (rv != 0) 1579 goto out; 1580 #endif 1581 device_add_child(dev, "pci", -1); 1582 1583 return (bus_generic_attach(dev)); 1584 1585 out: 1586 1587 return (rv); 1588 } 1589 1590 1591 static device_method_t tegra_pcib_methods[] = { 1592 /* Device interface */ 1593 DEVMETHOD(device_probe, tegra_pcib_probe), 1594 DEVMETHOD(device_attach, tegra_pcib_attach), 1595 1596 /* Bus interface */ 1597 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1598 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1599 1600 /* pcib interface */ 1601 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots), 1602 DEVMETHOD(pcib_read_config, tegra_pcib_read_config), 1603 DEVMETHOD(pcib_write_config, tegra_pcib_write_config), 1604 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt), 1605 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi), 1606 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi), 1607 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi), 1608 1609 #ifdef TEGRA_PCIB_MSI_ENABLE 1610 /* MSI/MSI-X */ 1611 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi), 1612 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi), 1613 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi), 1614 1615 /* Interrupt controller interface */ 1616 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr), 1617 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr), 1618 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr), 1619 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr), 1620 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter), 1621 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread), 1622 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread), 1623 #endif 1624 1625 /* OFW bus interface */ 1626 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 1627 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 1628 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 1629 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 1630 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 1631 1632 DEVMETHOD_END 1633 }; 1634 1635 static devclass_t pcib_devclass; 1636 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods, 1637 sizeof(struct tegra_pcib_softc), ofw_pci_driver); 1638 DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass, 1639 NULL, NULL); 1640