1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Local interrupt controller driver for Tegra SoCs. 32 */ 33 #include <sys/param.h> 34 #include <sys/module.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/kernel.h> 39 #include <sys/rman.h> 40 41 #include <machine/fdt.h> 42 #include <machine/intr.h> 43 #include <machine/resource.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "pic_if.h" 49 50 #define LIC_VIRQ_CPU 0x00 51 #define LIC_VIRQ_COP 0x04 52 #define LIC_VFRQ_CPU 0x08 53 #define LIC_VFRQ_COP 0x0c 54 #define LIC_ISR 0x10 55 #define LIC_FIR 0x14 56 #define LIC_FIR_SET 0x18 57 #define LIC_FIR_CLR 0x1c 58 #define LIC_CPU_IER 0x20 59 #define LIC_CPU_IER_SET 0x24 60 #define LIC_CPU_IER_CLR 0x28 61 #define LIC_CPU_IEP_CLASS 0x2C 62 #define LIC_COP_IER 0x30 63 #define LIC_COP_IER_SET 0x34 64 #define LIC_COP_IER_CLR 0x38 65 #define LIC_COP_IEP_CLASS 0x3c 66 67 #define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v)) 68 #define RD4(_sc, _b, _r) bus_read_4((_sc)->mem_res[_b], (_r)) 69 70 static struct resource_spec lic_spec[] = { 71 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 72 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 73 { SYS_RES_MEMORY, 2, RF_ACTIVE }, 74 { SYS_RES_MEMORY, 3, RF_ACTIVE }, 75 { SYS_RES_MEMORY, 4, RF_ACTIVE }, 76 { -1, 0 } 77 }; 78 79 static struct ofw_compat_data compat_data[] = { 80 {"nvidia,tegra124-ictlr", 1}, 81 {NULL, 0} 82 }; 83 84 struct tegra_lic_sc { 85 device_t dev; 86 struct resource *mem_res[nitems(lic_spec)]; 87 device_t parent; 88 }; 89 90 static int 91 tegra_lic_register(device_t dev, struct intr_irqsrc *isrc, boolean_t *is_percpu) 92 { 93 struct tegra_lic_sc *sc = device_get_softc(dev); 94 95 return (PIC_REGISTER(sc->parent, isrc, is_percpu)); 96 } 97 98 static int 99 tegra_lic_unregister(device_t dev, struct intr_irqsrc *isrc) 100 { 101 struct tegra_lic_sc *sc = device_get_softc(dev); 102 103 return (PIC_UNREGISTER(sc->parent, isrc)); 104 } 105 106 static void 107 tegra_lic_enable_source(device_t dev, struct intr_irqsrc *isrc) 108 { 109 struct tegra_lic_sc *sc = device_get_softc(dev); 110 111 PIC_ENABLE_SOURCE(sc->parent, isrc); 112 } 113 114 static void 115 tegra_lic_disable_source(device_t dev, struct intr_irqsrc *isrc) 116 { 117 struct tegra_lic_sc *sc = device_get_softc(dev); 118 119 PIC_DISABLE_SOURCE(sc->parent, isrc); 120 } 121 122 static void 123 tegra_lic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 124 { 125 struct tegra_lic_sc *sc = device_get_softc(dev); 126 127 PIC_ENABLE_INTR(sc->parent, isrc); 128 } 129 130 static void 131 tegra_lic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 132 { 133 struct tegra_lic_sc *sc = device_get_softc(dev); 134 135 PIC_PRE_ITHREAD(sc->parent, isrc); 136 } 137 138 139 static void 140 tegra_lic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 141 { 142 struct tegra_lic_sc *sc = device_get_softc(dev); 143 144 PIC_POST_ITHREAD(sc->parent, isrc); 145 } 146 147 static void 148 tegra_lic_post_filter(device_t dev, struct intr_irqsrc *isrc) 149 { 150 struct tegra_lic_sc *sc = device_get_softc(dev); 151 152 PIC_POST_FILTER(sc->parent, isrc); 153 } 154 155 #ifdef SMP 156 static int 157 tegra_lic_bind(device_t dev, struct intr_irqsrc *isrc) 158 { 159 struct tegra_lic_sc *sc = device_get_softc(dev); 160 161 return (PIC_BIND(sc->parent, isrc)); 162 } 163 #endif 164 165 static int 166 tegra_lic_probe(device_t dev) 167 { 168 if (!ofw_bus_status_okay(dev)) 169 return (ENXIO); 170 171 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 172 return (ENXIO); 173 174 return (BUS_PROBE_DEFAULT); 175 } 176 177 static int 178 tegra_lic_attach(device_t dev) 179 { 180 struct tegra_lic_sc *sc; 181 phandle_t node; 182 phandle_t parent_xref; 183 int i, rv; 184 185 sc = device_get_softc(dev); 186 sc->dev = dev; 187 node = ofw_bus_get_node(dev); 188 189 rv = OF_getencprop(node, "interrupt-parent", &parent_xref, 190 sizeof(parent_xref)); 191 if (rv <= 0) { 192 device_printf(dev, "Cannot read parent node property\n"); 193 goto fail; 194 } 195 sc->parent = OF_device_from_xref(parent_xref); 196 if (sc->parent == NULL) { 197 device_printf(dev, "Cannott find parent controller\n"); 198 goto fail; 199 } 200 201 if (bus_alloc_resources(dev, lic_spec, sc->mem_res)) { 202 device_printf(dev, "Cannott allocate resources\n"); 203 goto fail; 204 } 205 206 /* Disable all interrupts, route all to irq */ 207 for (i = 0; i < nitems(lic_spec); i++) { 208 if (sc->mem_res[i] == NULL) 209 continue; 210 WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF); 211 WR4(sc, i, LIC_CPU_IEP_CLASS, 0); 212 } 213 214 215 if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) { 216 device_printf(dev, "Cannot register PIC\n"); 217 goto fail; 218 } 219 return (0); 220 221 fail: 222 bus_release_resources(dev, lic_spec, sc->mem_res); 223 return (ENXIO); 224 } 225 226 static int 227 tegra_lic_detach(device_t dev) 228 { 229 struct tegra_lic_sc *sc; 230 int i; 231 232 sc = device_get_softc(dev); 233 for (i = 0; i < nitems(lic_spec); i++) { 234 if (sc->mem_res[i] == NULL) 235 continue; 236 bus_release_resource(dev, SYS_RES_MEMORY, i, 237 sc->mem_res[i]); 238 } 239 return (0); 240 } 241 242 static device_method_t tegra_lic_methods[] = { 243 DEVMETHOD(device_probe, tegra_lic_probe), 244 DEVMETHOD(device_attach, tegra_lic_attach), 245 DEVMETHOD(device_detach, tegra_lic_detach), 246 247 /* Interrupt controller interface */ 248 DEVMETHOD(pic_register, tegra_lic_register), 249 DEVMETHOD(pic_unregister, tegra_lic_unregister), 250 DEVMETHOD(pic_enable_source, tegra_lic_enable_source), 251 DEVMETHOD(pic_disable_source, tegra_lic_disable_source), 252 DEVMETHOD(pic_enable_intr, tegra_lic_enable_intr), 253 DEVMETHOD(pic_pre_ithread, tegra_lic_pre_ithread), 254 DEVMETHOD(pic_post_ithread, tegra_lic_post_ithread), 255 DEVMETHOD(pic_post_filter, tegra_lic_post_filter), 256 #ifdef SMP 257 DEVMETHOD(pic_bind, tegra_lic_bind), 258 #endif 259 DEVMETHOD_END 260 }; 261 devclass_t tegra_lic_devclass; 262 DEFINE_CLASS_0(tegra_lic, tegra_lic_driver, tegra_lic_methods, 263 sizeof(struct tegra_lic_sc)); 264 EARLY_DRIVER_MODULE(tegra_lic, simplebus, tegra_lic_driver, tegra_lic_devclass, 265 NULL, NULL, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE + 1); 266