1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Tegra GPIO driver. 32 */ 33 #include "opt_platform.h" 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/gpio.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/resource.h> 48 49 #include <dev/gpio/gpiobusvar.h> 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include "pic_if.h" 55 56 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 57 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 58 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ 59 device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF) 60 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 61 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 62 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); 63 64 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 65 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 66 67 #define GPIO_BANK_OFFS 0x100 /* Bank offset */ 68 #define GPIO_NUM_BANKS 8 /* Total number per bank */ 69 #define GPIO_REGS_IN_BANK 4 /* Total registers in bank */ 70 #define GPIO_PINS_IN_REG 8 /* Total pin in register */ 71 72 #define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG)) 73 #define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK) 74 #define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG) 75 76 #define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \ 77 GPIO_PORTNUM(n) * 4) 78 79 #define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8) 80 81 /* Register offsets */ 82 #define GPIO_CNF 0x00 83 #define GPIO_OE 0x10 84 #define GPIO_OUT 0x20 85 #define GPIO_IN 0x30 86 #define GPIO_INT_STA 0x40 87 #define GPIO_INT_ENB 0x50 88 #define GPIO_INT_LVL 0x60 89 #define GPIO_INT_LVL_DELTA (1 << 16) 90 #define GPIO_INT_LVL_EDGE (1 << 8) 91 #define GPIO_INT_LVL_HIGH (1 << 0) 92 #define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \ 93 GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH) 94 #define GPIO_INT_CLR 0x70 95 #define GPIO_MSK_CNF 0x80 96 #define GPIO_MSK_OE 0x90 97 #define GPIO_MSK_OUT 0xA0 98 #define GPIO_MSK_INT_STA 0xC0 99 #define GPIO_MSK_INT_ENB 0xD0 100 #define GPIO_MSK_INT_LVL 0xE0 101 102 char *tegra_gpio_port_names[] = { 103 "A", "B", "C", "D", /* Bank 0 */ 104 "E", "F", "G", "H", /* Bank 1 */ 105 "I", "J", "K", "L", /* Bank 2 */ 106 "M", "N", "O", "P", /* Bank 3 */ 107 "Q", "R", "S", "T", /* Bank 4 */ 108 "U", "V", "W", "X", /* Bank 5 */ 109 "Y", "Z", "AA", "BB", /* Bank 6 */ 110 "CC", "DD", "EE" /* Bank 7 */ 111 }; 112 113 struct tegra_gpio_irqsrc { 114 struct intr_irqsrc isrc; 115 u_int irq; 116 uint32_t cfgreg; 117 }; 118 119 struct tegra_gpio_softc; 120 struct tegra_gpio_irq_cookie { 121 struct tegra_gpio_softc *sc; 122 int bank_num; 123 }; 124 125 struct tegra_gpio_softc { 126 device_t dev; 127 device_t busdev; 128 struct mtx mtx; 129 struct resource *mem_res; 130 struct resource *irq_res[GPIO_NUM_BANKS]; 131 void *irq_ih[GPIO_NUM_BANKS]; 132 struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS]; 133 int gpio_npins; 134 struct gpio_pin gpio_pins[NGPIO]; 135 struct tegra_gpio_irqsrc *isrcs; 136 }; 137 138 static struct ofw_compat_data compat_data[] = { 139 {"nvidia,tegra124-gpio", 1}, 140 {NULL, 0} 141 }; 142 143 /* -------------------------------------------------------------------------- 144 * 145 * GPIO 146 * 147 */ 148 static inline void 149 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, 150 struct gpio_pin *pin, uint32_t val) 151 { 152 uint32_t tmp; 153 int bit; 154 155 bit = GPIO_BIT(pin->gp_pin); 156 tmp = 0x100 << bit; /* mask */ 157 tmp |= (val & 1) << bit; /* value */ 158 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp); 159 } 160 161 static inline uint32_t 162 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 163 { 164 int bit; 165 uint32_t val; 166 167 bit = GPIO_BIT(pin->gp_pin); 168 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin)); 169 return (val >> bit) & 1; 170 } 171 172 static void 173 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin, 174 unsigned int flags) 175 { 176 177 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0) 178 return; 179 180 /* Manage input/output */ 181 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 182 if (flags & GPIO_PIN_OUTPUT) { 183 pin->gp_flags |= GPIO_PIN_OUTPUT; 184 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1); 185 } else { 186 pin->gp_flags |= GPIO_PIN_INPUT; 187 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0); 188 } 189 } 190 191 static device_t 192 tegra_gpio_get_bus(device_t dev) 193 { 194 struct tegra_gpio_softc *sc; 195 196 sc = device_get_softc(dev); 197 return (sc->busdev); 198 } 199 200 static int 201 tegra_gpio_pin_max(device_t dev, int *maxpin) 202 { 203 204 *maxpin = NGPIO - 1; 205 return (0); 206 } 207 208 static int 209 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 210 { 211 struct tegra_gpio_softc *sc; 212 213 sc = device_get_softc(dev); 214 if (pin >= sc->gpio_npins) 215 return (EINVAL); 216 217 GPIO_LOCK(sc); 218 *caps = sc->gpio_pins[pin].gp_caps; 219 GPIO_UNLOCK(sc); 220 221 return (0); 222 } 223 224 static int 225 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 226 { 227 struct tegra_gpio_softc *sc; 228 int cnf; 229 230 sc = device_get_softc(dev); 231 if (pin >= sc->gpio_npins) 232 return (EINVAL); 233 234 GPIO_LOCK(sc); 235 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 236 if (cnf == 0) { 237 GPIO_UNLOCK(sc); 238 return (ENXIO); 239 } 240 *flags = sc->gpio_pins[pin].gp_flags; 241 GPIO_UNLOCK(sc); 242 243 return (0); 244 } 245 246 static int 247 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 248 { 249 struct tegra_gpio_softc *sc; 250 251 sc = device_get_softc(dev); 252 if (pin >= sc->gpio_npins) 253 return (EINVAL); 254 255 GPIO_LOCK(sc); 256 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 257 GPIO_UNLOCK(sc); 258 259 return (0); 260 } 261 262 static int 263 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 264 { 265 struct tegra_gpio_softc *sc; 266 int cnf; 267 268 sc = device_get_softc(dev); 269 if (pin >= sc->gpio_npins) 270 return (EINVAL); 271 272 GPIO_LOCK(sc); 273 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 274 if (cnf == 0) { 275 /* XXX - allow this for while .... 276 GPIO_UNLOCK(sc); 277 return (ENXIO); 278 */ 279 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1); 280 } 281 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 282 GPIO_UNLOCK(sc); 283 284 return (0); 285 } 286 287 static int 288 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 289 { 290 struct tegra_gpio_softc *sc; 291 292 sc = device_get_softc(dev); 293 if (pin >= sc->gpio_npins) 294 return (EINVAL); 295 GPIO_LOCK(sc); 296 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value); 297 GPIO_UNLOCK(sc); 298 299 return (0); 300 } 301 302 static int 303 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 304 { 305 struct tegra_gpio_softc *sc; 306 307 sc = device_get_softc(dev); 308 if (pin >= sc->gpio_npins) 309 return (EINVAL); 310 311 GPIO_LOCK(sc); 312 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]); 313 GPIO_UNLOCK(sc); 314 315 return (0); 316 } 317 318 static int 319 tegra_gpio_pin_toggle(device_t dev, uint32_t pin) 320 { 321 struct tegra_gpio_softc *sc; 322 323 sc = device_get_softc(dev); 324 if (pin >= sc->gpio_npins) 325 return (EINVAL); 326 327 GPIO_LOCK(sc); 328 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin], 329 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1); 330 GPIO_UNLOCK(sc); 331 332 return (0); 333 } 334 335 /* -------------------------------------------------------------------------- 336 * 337 * Interrupts 338 * 339 */ 340 static inline void 341 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg, 342 struct tegra_gpio_irqsrc *tgi, uint32_t val) 343 { 344 uint32_t tmp; 345 int bit; 346 347 bit = GPIO_BIT(tgi->irq); 348 tmp = 0x100 << bit; /* mask */ 349 tmp |= (val & 1) << bit; /* value */ 350 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 351 } 352 353 static inline void 354 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg, 355 struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask) 356 { 357 uint32_t tmp; 358 int bit; 359 360 bit = GPIO_BIT(tgi->irq); 361 GPIO_LOCK(sc); 362 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq)); 363 tmp &= ~(mask << bit); 364 tmp |= val << bit; 365 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 366 GPIO_UNLOCK(sc); 367 } 368 369 static inline void 370 tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc, 371 struct tegra_gpio_irqsrc *tgi, uint32_t val) 372 { 373 374 intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val); 375 } 376 377 static inline void 378 tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc, 379 struct tegra_gpio_irqsrc *tgi) 380 { 381 382 intr_write_masked(sc, GPIO_INT_CLR, tgi, 1); 383 } 384 385 static inline bool 386 tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi) 387 { 388 389 return (tgi->cfgreg & GPIO_INT_LVL_EDGE); 390 } 391 392 static int 393 tegra_gpio_intr(void *arg) 394 { 395 u_int irq, i, j, val, basepin; 396 struct tegra_gpio_softc *sc; 397 struct trapframe *tf; 398 struct tegra_gpio_irqsrc *tgi; 399 struct tegra_gpio_irq_cookie *cookie; 400 401 cookie = (struct tegra_gpio_irq_cookie *)arg; 402 sc = cookie->sc; 403 tf = curthread->td_intr_frame; 404 405 for (i = 0; i < GPIO_REGS_IN_BANK; i++) { 406 basepin = cookie->bank_num * GPIO_REGS_IN_BANK * 407 GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG; 408 409 val = bus_read_4(sc->mem_res, GPIO_INT_STA + 410 GPIO_REGNUM(basepin)); 411 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + 412 GPIO_REGNUM(basepin)); 413 /* Interrupt handling */ 414 for (j = 0; j < GPIO_PINS_IN_REG; j++) { 415 if ((val & (1 << j)) == 0) 416 continue; 417 irq = basepin + j; 418 tgi = &sc->isrcs[irq]; 419 if (!tegra_gpio_isrc_is_level(tgi)) 420 tegra_gpio_isrc_eoi(sc, tgi); 421 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 422 tegra_gpio_isrc_mask(sc, tgi, 0); 423 if (tegra_gpio_isrc_is_level(tgi)) 424 tegra_gpio_isrc_eoi(sc, tgi); 425 device_printf(sc->dev, 426 "Stray irq %u disabled\n", irq); 427 } 428 } 429 } 430 431 return (FILTER_HANDLED); 432 } 433 434 static int 435 tegra_gpio_pic_attach(struct tegra_gpio_softc *sc) 436 { 437 int error; 438 uint32_t irq; 439 const char *name; 440 441 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, 442 M_WAITOK | M_ZERO); 443 444 name = device_get_nameunit(sc->dev); 445 for (irq = 0; irq < sc->gpio_npins; irq++) { 446 sc->isrcs[irq].irq = irq; 447 sc->isrcs[irq].cfgreg = 0; 448 error = intr_isrc_register(&sc->isrcs[irq].isrc, 449 sc->dev, 0, "%s,%u", name, irq); 450 if (error != 0) 451 return (error); /* XXX deregister ISRCs */ 452 } 453 if (intr_pic_register(sc->dev, 454 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) 455 return (ENXIO); 456 457 return (0); 458 } 459 460 static int 461 tegra_gpio_pic_detach(struct tegra_gpio_softc *sc) 462 { 463 464 /* 465 * There has not been established any procedure yet 466 * how to detach PIC from living system correctly. 467 */ 468 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 469 return (EBUSY); 470 } 471 472 static void 473 tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 474 { 475 struct tegra_gpio_softc *sc; 476 struct tegra_gpio_irqsrc *tgi; 477 478 sc = device_get_softc(dev); 479 tgi = (struct tegra_gpio_irqsrc *)isrc; 480 tegra_gpio_isrc_mask(sc, tgi, 0); 481 } 482 483 static void 484 tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 485 { 486 struct tegra_gpio_softc *sc; 487 struct tegra_gpio_irqsrc *tgi; 488 489 sc = device_get_softc(dev); 490 tgi = (struct tegra_gpio_irqsrc *)isrc; 491 tegra_gpio_isrc_mask(sc, tgi, 1); 492 } 493 494 static int 495 tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells, 496 pcell_t *cells, u_int *irqp, uint32_t *regp) 497 { 498 uint32_t reg; 499 500 /* 501 * The first cell is the interrupt number. 502 * The second cell is used to specify flags: 503 * bits[3:0] trigger type and level flags: 504 * 1 = low-to-high edge triggered. 505 * 2 = high-to-low edge triggered. 506 * 4 = active high level-sensitive. 507 * 8 = active low level-sensitive. 508 */ 509 if (ncells != 2 || cells[0] >= sc->gpio_npins) 510 return (EINVAL); 511 512 /* 513 * All interrupt types could be set for an interrupt at one moment. 514 * At least, the combination of 'low-to-high' and 'high-to-low' edge 515 * triggered interrupt types can make a sense. 516 */ 517 if (cells[1] == 1) 518 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 519 else if (cells[1] == 2) 520 reg = GPIO_INT_LVL_EDGE; 521 else if (cells[1] == 3) 522 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 523 else if (cells[1] == 4) 524 reg = GPIO_INT_LVL_HIGH; 525 else if (cells[1] == 8) 526 reg = 0; 527 else 528 return (EINVAL); 529 530 *irqp = cells[0]; 531 if (regp != NULL) 532 *regp = reg; 533 return (0); 534 } 535 536 static int 537 tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num, 538 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp) 539 { 540 541 uint32_t reg; 542 543 if (gpio_pin_num >= sc->gpio_npins) 544 return (EINVAL); 545 switch (intr_mode) { 546 case GPIO_INTR_CONFORM: 547 case GPIO_INTR_LEVEL_LOW: 548 reg = 0; 549 break; 550 case GPIO_INTR_LEVEL_HIGH: 551 reg = GPIO_INT_LVL_HIGH; 552 break; 553 case GPIO_INTR_EDGE_RISING: 554 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 555 break; 556 case GPIO_INTR_EDGE_FALLING: 557 reg = GPIO_INT_LVL_EDGE; 558 break; 559 case GPIO_INTR_EDGE_BOTH: 560 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 561 break; 562 default: 563 return (EINVAL); 564 } 565 *irqp = gpio_pin_num; 566 if (regp != NULL) 567 *regp = reg; 568 return (0); 569 } 570 571 static int 572 tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 573 struct intr_irqsrc **isrcp) 574 { 575 int rv; 576 u_int irq; 577 struct tegra_gpio_softc *sc; 578 579 sc = device_get_softc(dev); 580 581 if (data->type == INTR_MAP_DATA_FDT) { 582 struct intr_map_data_fdt *daf; 583 584 daf = (struct intr_map_data_fdt *)data; 585 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 586 NULL); 587 } else if (data->type == INTR_MAP_DATA_GPIO) { 588 struct intr_map_data_gpio *dag; 589 590 dag = (struct intr_map_data_gpio *)data; 591 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 592 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL); 593 } else 594 return (ENOTSUP); 595 596 if (rv == 0) 597 *isrcp = &sc->isrcs[irq].isrc; 598 return (rv); 599 } 600 601 static void 602 tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 603 { 604 struct tegra_gpio_softc *sc; 605 struct tegra_gpio_irqsrc *tgi; 606 607 sc = device_get_softc(dev); 608 tgi = (struct tegra_gpio_irqsrc *)isrc; 609 if (tegra_gpio_isrc_is_level(tgi)) 610 tegra_gpio_isrc_eoi(sc, tgi); 611 } 612 613 static void 614 tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 615 { 616 struct tegra_gpio_softc *sc; 617 struct tegra_gpio_irqsrc *tgi; 618 619 sc = device_get_softc(dev); 620 tgi = (struct tegra_gpio_irqsrc *)isrc; 621 tegra_gpio_isrc_mask(sc, tgi, 1); 622 } 623 624 static void 625 tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 626 { 627 struct tegra_gpio_softc *sc; 628 struct tegra_gpio_irqsrc *tgi; 629 630 sc = device_get_softc(dev); 631 tgi = (struct tegra_gpio_irqsrc *)isrc; 632 633 tegra_gpio_isrc_mask(sc, tgi, 0); 634 if (tegra_gpio_isrc_is_level(tgi)) 635 tegra_gpio_isrc_eoi(sc, tgi); 636 } 637 638 static int 639 tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 640 struct resource *res, struct intr_map_data *data) 641 { 642 u_int irq; 643 uint32_t cfgreg; 644 int rv; 645 struct tegra_gpio_softc *sc; 646 struct tegra_gpio_irqsrc *tgi; 647 648 sc = device_get_softc(dev); 649 tgi = (struct tegra_gpio_irqsrc *)isrc; 650 651 if (data == NULL) 652 return (ENOTSUP); 653 654 /* Get and check config for an interrupt. */ 655 if (data->type == INTR_MAP_DATA_FDT) { 656 struct intr_map_data_fdt *daf; 657 658 daf = (struct intr_map_data_fdt *)data; 659 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 660 &cfgreg); 661 } else if (data->type == INTR_MAP_DATA_GPIO) { 662 struct intr_map_data_gpio *dag; 663 664 dag = (struct intr_map_data_gpio *)data; 665 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 666 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg); 667 } else 668 return (ENOTSUP); 669 if (rv != 0) 670 return (EINVAL); 671 672 /* 673 * If this is a setup for another handler, 674 * only check that its configuration match. 675 */ 676 if (isrc->isrc_handlers != 0) 677 return (tgi->cfgreg == cfgreg ? 0 : EINVAL); 678 679 tgi->cfgreg = cfgreg; 680 intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK); 681 tegra_gpio_pic_enable_intr(dev, isrc); 682 683 return (0); 684 } 685 686 static int 687 tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 688 struct resource *res, struct intr_map_data *data) 689 { 690 struct tegra_gpio_softc *sc; 691 struct tegra_gpio_irqsrc *tgi; 692 693 sc = device_get_softc(dev); 694 tgi = (struct tegra_gpio_irqsrc *)isrc; 695 696 if (isrc->isrc_handlers == 0) 697 tegra_gpio_isrc_mask(sc, tgi, 0); 698 return (0); 699 } 700 701 static int 702 tegra_gpio_probe(device_t dev) 703 { 704 705 if (!ofw_bus_status_okay(dev)) 706 return (ENXIO); 707 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 708 device_set_desc(dev, "Tegra GPIO Controller"); 709 return (BUS_PROBE_DEFAULT); 710 } 711 712 return (ENXIO); 713 } 714 715 /* -------------------------------------------------------------------------- 716 * 717 * Bus 718 * 719 */ 720 static int 721 tegra_gpio_detach(device_t dev) 722 { 723 struct tegra_gpio_softc *sc; 724 int i; 725 726 sc = device_get_softc(dev); 727 728 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); 729 730 for (i = 0; i < GPIO_NUM_BANKS; i++) { 731 if (sc->irq_ih[i] != NULL) 732 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); 733 } 734 735 if (sc->isrcs != NULL) 736 tegra_gpio_pic_detach(sc); 737 738 gpiobus_detach_bus(dev); 739 740 for (i = 0; i < GPIO_NUM_BANKS; i++) { 741 if (sc->irq_res[i] != NULL) 742 bus_release_resource(dev, SYS_RES_IRQ, 0, 743 sc->irq_res[i]); 744 } 745 if (sc->mem_res != NULL) 746 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 747 GPIO_LOCK_DESTROY(sc); 748 749 return(0); 750 } 751 752 static int 753 tegra_gpio_attach(device_t dev) 754 { 755 struct tegra_gpio_softc *sc; 756 int i, rid; 757 758 sc = device_get_softc(dev); 759 sc->dev = dev; 760 GPIO_LOCK_INIT(sc); 761 762 /* Allocate bus_space resources. */ 763 rid = 0; 764 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 765 RF_ACTIVE); 766 if (sc->mem_res == NULL) { 767 device_printf(dev, "Cannot allocate memory resources\n"); 768 tegra_gpio_detach(dev); 769 return (ENXIO); 770 } 771 772 sc->gpio_npins = NGPIO; 773 for (i = 0; i < sc->gpio_npins; i++) { 774 sc->gpio_pins[i].gp_pin = i; 775 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 776 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 777 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 778 GPIO_INTR_EDGE_BOTH; 779 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d", 780 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG], 781 i % GPIO_PINS_IN_REG); 782 sc->gpio_pins[i].gp_flags = 783 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ? 784 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 785 } 786 787 /* Init interrupt related registes. */ 788 for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) { 789 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0); 790 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF); 791 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF); 792 } 793 794 /* Allocate interrupts. */ 795 for (i = 0; i < GPIO_NUM_BANKS; i++) { 796 sc->irq_cookies[i].sc = sc; 797 sc->irq_cookies[i].bank_num = i; 798 rid = i; 799 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 800 &rid, RF_ACTIVE); 801 if (sc->irq_res[i] == NULL) { 802 device_printf(dev, "Cannot allocate IRQ resources\n"); 803 tegra_gpio_detach(dev); 804 return (ENXIO); 805 } 806 if ((bus_setup_intr(dev, sc->irq_res[i], 807 INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL, 808 &sc->irq_cookies[i], &sc->irq_ih[i]))) { 809 device_printf(dev, 810 "WARNING: unable to register interrupt handler\n"); 811 tegra_gpio_detach(dev); 812 return (ENXIO); 813 } 814 } 815 816 if (tegra_gpio_pic_attach(sc) != 0) { 817 device_printf(dev, "WARNING: unable to attach PIC\n"); 818 tegra_gpio_detach(dev); 819 return (ENXIO); 820 } 821 822 sc->busdev = gpiobus_attach_bus(dev); 823 if (sc->busdev == NULL) { 824 tegra_gpio_detach(dev); 825 return (ENXIO); 826 } 827 828 return (bus_generic_attach(dev)); 829 } 830 831 static int 832 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 833 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 834 { 835 836 if (gcells != 2) 837 return (ERANGE); 838 *pin = gpios[0]; 839 *flags= gpios[1]; 840 return (0); 841 } 842 843 static phandle_t 844 tegra_gpio_get_node(device_t bus, device_t dev) 845 { 846 847 /* We only have one child, the GPIO bus, which needs our own node. */ 848 return (ofw_bus_get_node(bus)); 849 } 850 851 static device_method_t tegra_gpio_methods[] = { 852 DEVMETHOD(device_probe, tegra_gpio_probe), 853 DEVMETHOD(device_attach, tegra_gpio_attach), 854 DEVMETHOD(device_detach, tegra_gpio_detach), 855 856 /* Interrupt controller interface */ 857 DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr), 858 DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr), 859 DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr), 860 DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr), 861 DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr), 862 DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter), 863 DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread), 864 DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread), 865 866 /* GPIO protocol */ 867 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus), 868 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max), 869 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname), 870 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags), 871 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps), 872 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags), 873 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get), 874 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set), 875 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle), 876 DEVMETHOD(gpio_map_gpios, tegra_map_gpios), 877 878 /* ofw_bus interface */ 879 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node), 880 881 DEVMETHOD_END 882 }; 883 884 static devclass_t tegra_gpio_devclass; 885 static DEFINE_CLASS_0(gpio, tegra_gpio_driver, tegra_gpio_methods, 886 sizeof(struct tegra_gpio_softc)); 887 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver, 888 tegra_gpio_devclass, NULL, NULL, 70); 889