1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Tegra GPIO driver. 32 */ 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/gpio.h> 46 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/gpio/gpiobusvar.h> 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 57 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 58 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 59 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \ 60 device_get_nameunit(_sc->sc_dev), "tegra_gpio", MTX_DEF) 61 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 62 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 63 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 64 65 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 66 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 67 68 #define GPIO_BANK_OFFS 0x100 /* Bank offset */ 69 #define GPIO_NUM_BANKS 8 /* Total number per bank */ 70 #define GPIO_REGS_IN_BANK 4 /* Total registers in bank */ 71 #define GPIO_PINS_IN_REG 8 /* Total pin in register */ 72 73 #define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG)) 74 #define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK) 75 #define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG) 76 77 #define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \ 78 GPIO_PORTNUM(n) * 4) 79 80 #define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8) 81 82 /* Register offsets */ 83 #define GPIO_CNF 0x00 84 #define GPIO_OE 0x10 85 #define GPIO_OUT 0x20 86 #define GPIO_IN 0x30 87 #define GPIO_INT_STA 0x40 88 #define GPIO_INT_ENB 0x50 89 #define GPIO_INT_LVL 0x60 90 #define GPIO_INT_CLR 0x70 91 #define GPIO_MSK_CNF 0x80 92 #define GPIO_MSK_OE 0x90 93 #define GPIO_MSK_OUT 0xA0 94 #define GPIO_MSK_INT_STA 0xC0 95 #define GPIO_MSK_INT_ENB 0xD0 96 #define GPIO_MSK_INT_LVL 0xE0 97 98 char *tegra_gpio_port_names[] = { 99 "A", "B", "C", "D", /* Bank 0 */ 100 "E", "F", "G", "H", /* Bank 1 */ 101 "I", "J", "K", "L", /* Bank 2 */ 102 "M", "N", "O", "P", /* Bank 3 */ 103 "Q", "R", "S", "T", /* Bank 4 */ 104 "U", "V", "W", "X", /* Bank 5 */ 105 "Y", "Z", "AA", "BB", /* Bank 5 */ 106 "CC", "DD", "EE" /* Bank 5 */ 107 }; 108 109 struct tegra_gpio_softc { 110 device_t dev; 111 device_t sc_busdev; 112 struct mtx sc_mtx; 113 struct resource *mem_res; 114 struct resource *irq_res; 115 void *gpio_ih; 116 int gpio_npins; 117 struct gpio_pin gpio_pins[NGPIO]; 118 }; 119 120 static struct ofw_compat_data compat_data[] = { 121 {"nvidia,tegra124-gpio", 1}, 122 {NULL, 0} 123 }; 124 125 static inline void 126 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, 127 struct gpio_pin *pin, uint32_t val) 128 { 129 uint32_t tmp; 130 int bit; 131 132 bit = GPIO_BIT(pin->gp_pin); 133 tmp = 0x100 << bit; /* mask */ 134 tmp |= (val & 1) << bit; /* value */ 135 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp); 136 } 137 static inline uint32_t 138 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 139 { 140 int bit; 141 uint32_t val; 142 143 bit = GPIO_BIT(pin->gp_pin); 144 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin)); 145 return (val >> bit) & 1; 146 } 147 148 static void 149 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin, 150 unsigned int flags) 151 { 152 153 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0) 154 return; 155 156 /* Manage input/output */ 157 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 158 if (flags & GPIO_PIN_OUTPUT) { 159 pin->gp_flags |= GPIO_PIN_OUTPUT; 160 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1); 161 } else { 162 pin->gp_flags |= GPIO_PIN_INPUT; 163 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0); 164 } 165 } 166 167 static device_t 168 tegra_gpio_get_bus(device_t dev) 169 { 170 struct tegra_gpio_softc *sc; 171 172 sc = device_get_softc(dev); 173 return (sc->sc_busdev); 174 } 175 176 static int 177 tegra_gpio_pin_max(device_t dev, int *maxpin) 178 { 179 180 *maxpin = NGPIO - 1; 181 return (0); 182 } 183 184 static int 185 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 186 { 187 struct tegra_gpio_softc *sc; 188 189 sc = device_get_softc(dev); 190 if (pin >= sc->gpio_npins) 191 return (EINVAL); 192 193 GPIO_LOCK(sc); 194 *caps = sc->gpio_pins[pin].gp_caps; 195 GPIO_UNLOCK(sc); 196 197 return (0); 198 } 199 200 static int 201 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 202 { 203 struct tegra_gpio_softc *sc; 204 int cnf; 205 206 sc = device_get_softc(dev); 207 if (pin >= sc->gpio_npins) 208 return (EINVAL); 209 210 GPIO_LOCK(sc); 211 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 212 if (cnf == 0) { 213 GPIO_UNLOCK(sc); 214 return (ENXIO); 215 } 216 *flags = sc->gpio_pins[pin].gp_flags; 217 GPIO_UNLOCK(sc); 218 219 return (0); 220 } 221 222 static int 223 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 224 { 225 struct tegra_gpio_softc *sc; 226 227 sc = device_get_softc(dev); 228 if (pin >= sc->gpio_npins) 229 return (EINVAL); 230 231 GPIO_LOCK(sc); 232 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 233 GPIO_UNLOCK(sc); 234 235 return (0); 236 } 237 238 static int 239 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 240 { 241 struct tegra_gpio_softc *sc; 242 int cnf; 243 244 sc = device_get_softc(dev); 245 if (pin >= sc->gpio_npins) 246 return (EINVAL); 247 248 GPIO_LOCK(sc); 249 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 250 if (cnf == 0) { 251 /* XXX - allow this for while .... 252 GPIO_UNLOCK(sc); 253 return (ENXIO); 254 */ 255 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1); 256 } 257 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 258 GPIO_UNLOCK(sc); 259 260 return (0); 261 } 262 263 static int 264 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 265 { 266 struct tegra_gpio_softc *sc; 267 268 sc = device_get_softc(dev); 269 if (pin >= sc->gpio_npins) 270 return (EINVAL); 271 GPIO_LOCK(sc); 272 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value); 273 GPIO_UNLOCK(sc); 274 275 return (0); 276 } 277 278 static int 279 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 280 { 281 struct tegra_gpio_softc *sc; 282 283 sc = device_get_softc(dev); 284 if (pin >= sc->gpio_npins) 285 return (EINVAL); 286 287 GPIO_LOCK(sc); 288 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]); 289 GPIO_UNLOCK(sc); 290 291 return (0); 292 } 293 294 static int 295 tegra_gpio_pin_toggle(device_t dev, uint32_t pin) 296 { 297 struct tegra_gpio_softc *sc; 298 299 sc = device_get_softc(dev); 300 if (pin >= sc->gpio_npins) 301 return (EINVAL); 302 303 GPIO_LOCK(sc); 304 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin], 305 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1); 306 GPIO_UNLOCK(sc); 307 308 return (0); 309 } 310 311 static int 312 tegra_gpio_intr(void *arg) 313 { 314 struct tegra_gpio_softc *sc; 315 uint32_t val; 316 int i; 317 318 sc = arg; 319 for (i = 0; i < NGPIO; i += GPIO_PINS_IN_REG) { 320 /* Clear interrupt */ 321 val = bus_read_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i)); 322 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i)); 323 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), val); 324 /* Interrupt handling */ 325 #ifdef not_yet 326 for (j = 0; j < GPIO_PINS_IN_REG; j++) { 327 if (val & (1 << j)) 328 handle_irq(i + j); 329 } 330 */ 331 #endif 332 } 333 return (FILTER_HANDLED); 334 } 335 336 static int 337 tegra_gpio_probe(device_t dev) 338 { 339 340 if (!ofw_bus_status_okay(dev)) 341 return (ENXIO); 342 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 343 device_set_desc(dev, "Tegra GPIO Controller"); 344 return (BUS_PROBE_DEFAULT); 345 } 346 347 return (ENXIO); 348 } 349 350 static int 351 tegra_gpio_detach(device_t dev) 352 { 353 struct tegra_gpio_softc *sc; 354 355 sc = device_get_softc(dev); 356 357 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 358 359 gpiobus_detach_bus(dev); 360 if (sc->gpio_ih != NULL) 361 bus_teardown_intr(dev, sc->irq_res, sc->gpio_ih); 362 if (sc->irq_res != NULL) 363 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 364 if (sc->mem_res != NULL) 365 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 366 mtx_destroy(&sc->sc_mtx); 367 368 return(0); 369 } 370 371 static int 372 tegra_gpio_attach(device_t dev) 373 { 374 struct tegra_gpio_softc *sc; 375 int i, rid; 376 377 sc = device_get_softc(dev); 378 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 379 380 /* Allocate bus_space resources. */ 381 rid = 0; 382 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 383 RF_ACTIVE); 384 if (sc->mem_res == NULL) { 385 device_printf(dev, "Cannot allocate memory resources\n"); 386 tegra_gpio_detach(dev); 387 return (ENXIO); 388 } 389 390 rid = 0; 391 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 392 if (sc->irq_res == NULL) { 393 device_printf(dev, "Cannot allocate IRQ resources\n"); 394 tegra_gpio_detach(dev); 395 return (ENXIO); 396 } 397 398 sc->dev = dev; 399 sc->gpio_npins = NGPIO; 400 401 if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 402 tegra_gpio_intr, NULL, sc, &sc->gpio_ih))) { 403 device_printf(dev, 404 "WARNING: unable to register interrupt handler\n"); 405 tegra_gpio_detach(dev); 406 return (ENXIO); 407 } 408 409 for (i = 0; i < sc->gpio_npins; i++) { 410 sc->gpio_pins[i].gp_pin = i; 411 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 412 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d", 413 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG], 414 i % GPIO_PINS_IN_REG); 415 sc->gpio_pins[i].gp_flags = 416 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ? 417 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 418 } 419 420 sc->sc_busdev = gpiobus_attach_bus(dev); 421 if (sc->sc_busdev == NULL) { 422 tegra_gpio_detach(dev); 423 return (ENXIO); 424 } 425 426 return (bus_generic_attach(dev)); 427 } 428 429 static int 430 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 431 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 432 { 433 434 if (gcells != 2) 435 return (ERANGE); 436 *pin = gpios[0]; 437 *flags= gpios[1]; 438 return (0); 439 } 440 441 static phandle_t 442 tegra_gpio_get_node(device_t bus, device_t dev) 443 { 444 445 /* We only have one child, the GPIO bus, which needs our own node. */ 446 return (ofw_bus_get_node(bus)); 447 } 448 449 static device_method_t tegra_gpio_methods[] = { 450 DEVMETHOD(device_probe, tegra_gpio_probe), 451 DEVMETHOD(device_attach, tegra_gpio_attach), 452 DEVMETHOD(device_detach, tegra_gpio_detach), 453 454 /* GPIO protocol */ 455 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus), 456 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max), 457 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname), 458 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags), 459 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps), 460 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags), 461 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get), 462 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set), 463 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle), 464 DEVMETHOD(gpio_map_gpios, tegra_map_gpios), 465 466 /* ofw_bus interface */ 467 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node), 468 469 DEVMETHOD_END 470 }; 471 472 static driver_t tegra_gpio_driver = { 473 "gpio", 474 tegra_gpio_methods, 475 sizeof(struct tegra_gpio_softc), 476 }; 477 static devclass_t tegra_gpio_devclass; 478 479 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver, 480 tegra_gpio_devclass, 0, 0, 70); 481