1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Tegra GPIO driver. 32 */ 33 #include "opt_platform.h" 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/gpio.h> 38 #include <sys/kernel.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/resource.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/gpio/gpiobusvar.h> 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include "pic_if.h" 56 57 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 58 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 59 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ 60 device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF) 61 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 62 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 63 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); 64 65 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 66 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 67 68 #define GPIO_BANK_OFFS 0x100 /* Bank offset */ 69 #define GPIO_NUM_BANKS 8 /* Total number per bank */ 70 #define GPIO_REGS_IN_BANK 4 /* Total registers in bank */ 71 #define GPIO_PINS_IN_REG 8 /* Total pin in register */ 72 73 #define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG)) 74 #define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK) 75 #define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG) 76 77 #define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \ 78 GPIO_PORTNUM(n) * 4) 79 80 #define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8) 81 82 /* Register offsets */ 83 #define GPIO_CNF 0x00 84 #define GPIO_OE 0x10 85 #define GPIO_OUT 0x20 86 #define GPIO_IN 0x30 87 #define GPIO_INT_STA 0x40 88 #define GPIO_INT_ENB 0x50 89 #define GPIO_INT_LVL 0x60 90 #define GPIO_INT_LVL_DELTA (1 << 16) 91 #define GPIO_INT_LVL_EDGE (1 << 8) 92 #define GPIO_INT_LVL_HIGH (1 << 0) 93 #define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \ 94 GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH) 95 #define GPIO_INT_CLR 0x70 96 #define GPIO_MSK_CNF 0x80 97 #define GPIO_MSK_OE 0x90 98 #define GPIO_MSK_OUT 0xA0 99 #define GPIO_MSK_INT_STA 0xC0 100 #define GPIO_MSK_INT_ENB 0xD0 101 #define GPIO_MSK_INT_LVL 0xE0 102 103 char *tegra_gpio_port_names[] = { 104 "A", "B", "C", "D", /* Bank 0 */ 105 "E", "F", "G", "H", /* Bank 1 */ 106 "I", "J", "K", "L", /* Bank 2 */ 107 "M", "N", "O", "P", /* Bank 3 */ 108 "Q", "R", "S", "T", /* Bank 4 */ 109 "U", "V", "W", "X", /* Bank 5 */ 110 "Y", "Z", "AA", "BB", /* Bank 6 */ 111 "CC", "DD", "EE" /* Bank 7 */ 112 }; 113 114 struct tegra_gpio_irqsrc { 115 struct intr_irqsrc isrc; 116 u_int irq; 117 uint32_t cfgreg; 118 }; 119 120 struct tegra_gpio_softc; 121 struct tegra_gpio_irq_cookie { 122 struct tegra_gpio_softc *sc; 123 int bank_num; 124 }; 125 126 struct tegra_gpio_softc { 127 device_t dev; 128 device_t busdev; 129 struct mtx mtx; 130 struct resource *mem_res; 131 struct resource *irq_res[GPIO_NUM_BANKS]; 132 void *irq_ih[GPIO_NUM_BANKS]; 133 struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS]; 134 int gpio_npins; 135 struct gpio_pin gpio_pins[NGPIO]; 136 struct tegra_gpio_irqsrc *isrcs; 137 }; 138 139 static struct ofw_compat_data compat_data[] = { 140 {"nvidia,tegra124-gpio", 1}, 141 {NULL, 0} 142 }; 143 144 /* -------------------------------------------------------------------------- 145 * 146 * GPIO 147 * 148 */ 149 static inline void 150 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, 151 struct gpio_pin *pin, uint32_t val) 152 { 153 uint32_t tmp; 154 int bit; 155 156 bit = GPIO_BIT(pin->gp_pin); 157 tmp = 0x100 << bit; /* mask */ 158 tmp |= (val & 1) << bit; /* value */ 159 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp); 160 } 161 162 static inline uint32_t 163 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 164 { 165 int bit; 166 uint32_t val; 167 168 bit = GPIO_BIT(pin->gp_pin); 169 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin)); 170 return (val >> bit) & 1; 171 } 172 173 static void 174 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin, 175 unsigned int flags) 176 { 177 178 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0) 179 return; 180 181 /* Manage input/output */ 182 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 183 if (flags & GPIO_PIN_OUTPUT) { 184 pin->gp_flags |= GPIO_PIN_OUTPUT; 185 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1); 186 } else { 187 pin->gp_flags |= GPIO_PIN_INPUT; 188 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0); 189 } 190 } 191 192 static device_t 193 tegra_gpio_get_bus(device_t dev) 194 { 195 struct tegra_gpio_softc *sc; 196 197 sc = device_get_softc(dev); 198 return (sc->busdev); 199 } 200 201 static int 202 tegra_gpio_pin_max(device_t dev, int *maxpin) 203 { 204 205 *maxpin = NGPIO - 1; 206 return (0); 207 } 208 209 static int 210 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 211 { 212 struct tegra_gpio_softc *sc; 213 214 sc = device_get_softc(dev); 215 if (pin >= sc->gpio_npins) 216 return (EINVAL); 217 218 GPIO_LOCK(sc); 219 *caps = sc->gpio_pins[pin].gp_caps; 220 GPIO_UNLOCK(sc); 221 222 return (0); 223 } 224 225 static int 226 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 227 { 228 struct tegra_gpio_softc *sc; 229 int cnf; 230 231 sc = device_get_softc(dev); 232 if (pin >= sc->gpio_npins) 233 return (EINVAL); 234 235 GPIO_LOCK(sc); 236 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 237 if (cnf == 0) { 238 GPIO_UNLOCK(sc); 239 return (ENXIO); 240 } 241 *flags = sc->gpio_pins[pin].gp_flags; 242 GPIO_UNLOCK(sc); 243 244 return (0); 245 } 246 247 static int 248 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 249 { 250 struct tegra_gpio_softc *sc; 251 252 sc = device_get_softc(dev); 253 if (pin >= sc->gpio_npins) 254 return (EINVAL); 255 256 GPIO_LOCK(sc); 257 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 258 GPIO_UNLOCK(sc); 259 260 return (0); 261 } 262 263 static int 264 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 265 { 266 struct tegra_gpio_softc *sc; 267 int cnf; 268 269 sc = device_get_softc(dev); 270 if (pin >= sc->gpio_npins) 271 return (EINVAL); 272 273 GPIO_LOCK(sc); 274 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 275 if (cnf == 0) { 276 /* XXX - allow this for while .... 277 GPIO_UNLOCK(sc); 278 return (ENXIO); 279 */ 280 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1); 281 } 282 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 283 GPIO_UNLOCK(sc); 284 285 return (0); 286 } 287 288 static int 289 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 290 { 291 struct tegra_gpio_softc *sc; 292 293 sc = device_get_softc(dev); 294 if (pin >= sc->gpio_npins) 295 return (EINVAL); 296 GPIO_LOCK(sc); 297 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value); 298 GPIO_UNLOCK(sc); 299 300 return (0); 301 } 302 303 static int 304 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 305 { 306 struct tegra_gpio_softc *sc; 307 308 sc = device_get_softc(dev); 309 if (pin >= sc->gpio_npins) 310 return (EINVAL); 311 312 GPIO_LOCK(sc); 313 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]); 314 GPIO_UNLOCK(sc); 315 316 return (0); 317 } 318 319 static int 320 tegra_gpio_pin_toggle(device_t dev, uint32_t pin) 321 { 322 struct tegra_gpio_softc *sc; 323 324 sc = device_get_softc(dev); 325 if (pin >= sc->gpio_npins) 326 return (EINVAL); 327 328 GPIO_LOCK(sc); 329 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin], 330 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1); 331 GPIO_UNLOCK(sc); 332 333 return (0); 334 } 335 336 /* -------------------------------------------------------------------------- 337 * 338 * Interrupts 339 * 340 */ 341 static inline void 342 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg, 343 struct tegra_gpio_irqsrc *tgi, uint32_t val) 344 { 345 uint32_t tmp; 346 int bit; 347 348 bit = GPIO_BIT(tgi->irq); 349 tmp = 0x100 << bit; /* mask */ 350 tmp |= (val & 1) << bit; /* value */ 351 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 352 } 353 354 static inline void 355 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg, 356 struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask) 357 { 358 uint32_t tmp; 359 int bit; 360 361 bit = GPIO_BIT(tgi->irq); 362 GPIO_LOCK(sc); 363 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq)); 364 tmp &= ~(mask << bit); 365 tmp |= val << bit; 366 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 367 GPIO_UNLOCK(sc); 368 } 369 370 static inline void 371 tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc, 372 struct tegra_gpio_irqsrc *tgi, uint32_t val) 373 { 374 375 intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val); 376 } 377 378 static inline void 379 tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc, 380 struct tegra_gpio_irqsrc *tgi) 381 { 382 383 intr_write_masked(sc, GPIO_INT_CLR, tgi, 1); 384 } 385 386 static inline bool 387 tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi) 388 { 389 390 return (tgi->cfgreg & GPIO_INT_LVL_EDGE); 391 } 392 393 static int 394 tegra_gpio_intr(void *arg) 395 { 396 u_int irq, i, j, val, basepin; 397 struct tegra_gpio_softc *sc; 398 struct trapframe *tf; 399 struct tegra_gpio_irqsrc *tgi; 400 struct tegra_gpio_irq_cookie *cookie; 401 402 cookie = (struct tegra_gpio_irq_cookie *)arg; 403 sc = cookie->sc; 404 tf = curthread->td_intr_frame; 405 406 for (i = 0; i < GPIO_REGS_IN_BANK; i++) { 407 basepin = cookie->bank_num * GPIO_REGS_IN_BANK * 408 GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG; 409 410 val = bus_read_4(sc->mem_res, GPIO_INT_STA + 411 GPIO_REGNUM(basepin)); 412 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + 413 GPIO_REGNUM(basepin)); 414 /* Interrupt handling */ 415 for (j = 0; j < GPIO_PINS_IN_REG; j++) { 416 if ((val & (1 << j)) == 0) 417 continue; 418 irq = basepin + j; 419 tgi = &sc->isrcs[irq]; 420 if (!tegra_gpio_isrc_is_level(tgi)) 421 tegra_gpio_isrc_eoi(sc, tgi); 422 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 423 tegra_gpio_isrc_mask(sc, tgi, 0); 424 if (tegra_gpio_isrc_is_level(tgi)) 425 tegra_gpio_isrc_eoi(sc, tgi); 426 device_printf(sc->dev, 427 "Stray irq %u disabled\n", irq); 428 } 429 430 } 431 } 432 433 return (FILTER_HANDLED); 434 } 435 436 static int 437 tegra_gpio_pic_attach(struct tegra_gpio_softc *sc) 438 { 439 int error; 440 uint32_t irq; 441 const char *name; 442 443 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, 444 M_WAITOK | M_ZERO); 445 446 name = device_get_nameunit(sc->dev); 447 for (irq = 0; irq < sc->gpio_npins; irq++) { 448 sc->isrcs[irq].irq = irq; 449 sc->isrcs[irq].cfgreg = 0; 450 error = intr_isrc_register(&sc->isrcs[irq].isrc, 451 sc->dev, 0, "%s,%u", name, irq); 452 if (error != 0) 453 return (error); /* XXX deregister ISRCs */ 454 } 455 if (intr_pic_register(sc->dev, 456 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) 457 return (ENXIO); 458 459 return (0); 460 } 461 462 static int 463 tegra_gpio_pic_detach(struct tegra_gpio_softc *sc) 464 { 465 466 /* 467 * There has not been established any procedure yet 468 * how to detach PIC from living system correctly. 469 */ 470 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 471 return (EBUSY); 472 } 473 474 475 static void 476 tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 477 { 478 struct tegra_gpio_softc *sc; 479 struct tegra_gpio_irqsrc *tgi; 480 481 sc = device_get_softc(dev); 482 tgi = (struct tegra_gpio_irqsrc *)isrc; 483 tegra_gpio_isrc_mask(sc, tgi, 0); 484 } 485 486 static void 487 tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 488 { 489 struct tegra_gpio_softc *sc; 490 struct tegra_gpio_irqsrc *tgi; 491 492 sc = device_get_softc(dev); 493 tgi = (struct tegra_gpio_irqsrc *)isrc; 494 tegra_gpio_isrc_mask(sc, tgi, 1); 495 } 496 497 static int 498 tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells, 499 pcell_t *cells, u_int *irqp, uint32_t *regp) 500 { 501 uint32_t reg; 502 503 /* 504 * The first cell is the interrupt number. 505 * The second cell is used to specify flags: 506 * bits[3:0] trigger type and level flags: 507 * 1 = low-to-high edge triggered. 508 * 2 = high-to-low edge triggered. 509 * 4 = active high level-sensitive. 510 * 8 = active low level-sensitive. 511 */ 512 if (ncells != 2 || cells[0] >= sc->gpio_npins) 513 return (EINVAL); 514 515 /* 516 * All interrupt types could be set for an interrupt at one moment. 517 * At least, the combination of 'low-to-high' and 'high-to-low' edge 518 * triggered interrupt types can make a sense. 519 */ 520 if (cells[1] == 1) 521 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 522 else if (cells[1] == 2) 523 reg = GPIO_INT_LVL_EDGE; 524 else if (cells[1] == 3) 525 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 526 else if (cells[1] == 4) 527 reg = GPIO_INT_LVL_HIGH; 528 else if (cells[1] == 8) 529 reg = 0; 530 else 531 return (EINVAL); 532 533 *irqp = cells[0]; 534 if (regp != NULL) 535 *regp = reg; 536 return (0); 537 } 538 539 540 static int 541 tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num, 542 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp) 543 { 544 545 uint32_t reg; 546 547 if (gpio_pin_num >= sc->gpio_npins) 548 return (EINVAL); 549 switch (intr_mode) { 550 case GPIO_INTR_CONFORM: 551 case GPIO_INTR_LEVEL_LOW: 552 reg = 0; 553 break; 554 case GPIO_INTR_LEVEL_HIGH: 555 reg = GPIO_INT_LVL_HIGH; 556 break; 557 case GPIO_INTR_EDGE_RISING: 558 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 559 break; 560 case GPIO_INTR_EDGE_FALLING: 561 reg = GPIO_INT_LVL_EDGE; 562 break; 563 case GPIO_INTR_EDGE_BOTH: 564 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 565 break; 566 default: 567 return (EINVAL); 568 } 569 *irqp = gpio_pin_num; 570 if (regp != NULL) 571 *regp = reg; 572 return (0); 573 } 574 575 static int 576 tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 577 struct intr_irqsrc **isrcp) 578 { 579 int rv; 580 u_int irq; 581 struct tegra_gpio_softc *sc; 582 583 sc = device_get_softc(dev); 584 585 if (data->type == INTR_MAP_DATA_FDT) { 586 struct intr_map_data_fdt *daf; 587 588 daf = (struct intr_map_data_fdt *)data; 589 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 590 NULL); 591 } else if (data->type == INTR_MAP_DATA_GPIO) { 592 struct intr_map_data_gpio *dag; 593 594 dag = (struct intr_map_data_gpio *)data; 595 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 596 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL); 597 } else 598 return (ENOTSUP); 599 600 if (rv == 0) 601 *isrcp = &sc->isrcs[irq].isrc; 602 return (rv); 603 } 604 605 static void 606 tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 607 { 608 struct tegra_gpio_softc *sc; 609 struct tegra_gpio_irqsrc *tgi; 610 611 sc = device_get_softc(dev); 612 tgi = (struct tegra_gpio_irqsrc *)isrc; 613 if (tegra_gpio_isrc_is_level(tgi)) 614 tegra_gpio_isrc_eoi(sc, tgi); 615 } 616 617 static void 618 tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 619 { 620 struct tegra_gpio_softc *sc; 621 struct tegra_gpio_irqsrc *tgi; 622 623 sc = device_get_softc(dev); 624 tgi = (struct tegra_gpio_irqsrc *)isrc; 625 tegra_gpio_isrc_mask(sc, tgi, 1); 626 } 627 628 static void 629 tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 630 { 631 struct tegra_gpio_softc *sc; 632 struct tegra_gpio_irqsrc *tgi; 633 634 sc = device_get_softc(dev); 635 tgi = (struct tegra_gpio_irqsrc *)isrc; 636 637 tegra_gpio_isrc_mask(sc, tgi, 0); 638 if (tegra_gpio_isrc_is_level(tgi)) 639 tegra_gpio_isrc_eoi(sc, tgi); 640 } 641 642 static int 643 tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 644 struct resource *res, struct intr_map_data *data) 645 { 646 u_int irq; 647 uint32_t cfgreg; 648 int rv; 649 struct tegra_gpio_softc *sc; 650 struct tegra_gpio_irqsrc *tgi; 651 652 sc = device_get_softc(dev); 653 tgi = (struct tegra_gpio_irqsrc *)isrc; 654 655 if (data == NULL) 656 return (ENOTSUP); 657 658 /* Get and check config for an interrupt. */ 659 if (data->type == INTR_MAP_DATA_FDT) { 660 struct intr_map_data_fdt *daf; 661 662 daf = (struct intr_map_data_fdt *)data; 663 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 664 &cfgreg); 665 } else if (data->type == INTR_MAP_DATA_GPIO) { 666 struct intr_map_data_gpio *dag; 667 668 dag = (struct intr_map_data_gpio *)data; 669 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 670 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg); 671 } else 672 return (ENOTSUP); 673 if (rv != 0) 674 return (EINVAL); 675 676 /* 677 * If this is a setup for another handler, 678 * only check that its configuration match. 679 */ 680 if (isrc->isrc_handlers != 0) 681 return (tgi->cfgreg == cfgreg ? 0 : EINVAL); 682 683 tgi->cfgreg = cfgreg; 684 intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK); 685 tegra_gpio_pic_enable_intr(dev, isrc); 686 687 return (0); 688 } 689 690 static int 691 tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 692 struct resource *res, struct intr_map_data *data) 693 { 694 struct tegra_gpio_softc *sc; 695 struct tegra_gpio_irqsrc *tgi; 696 697 sc = device_get_softc(dev); 698 tgi = (struct tegra_gpio_irqsrc *)isrc; 699 700 if (isrc->isrc_handlers == 0) 701 tegra_gpio_isrc_mask(sc, tgi, 0); 702 return (0); 703 } 704 705 static int 706 tegra_gpio_probe(device_t dev) 707 { 708 709 if (!ofw_bus_status_okay(dev)) 710 return (ENXIO); 711 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 712 device_set_desc(dev, "Tegra GPIO Controller"); 713 return (BUS_PROBE_DEFAULT); 714 } 715 716 return (ENXIO); 717 } 718 719 /* -------------------------------------------------------------------------- 720 * 721 * Bus 722 * 723 */ 724 static int 725 tegra_gpio_detach(device_t dev) 726 { 727 struct tegra_gpio_softc *sc; 728 int i; 729 730 sc = device_get_softc(dev); 731 732 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); 733 734 for (i = 0; i < GPIO_NUM_BANKS; i++) { 735 if (sc->irq_ih[i] != NULL) 736 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); 737 } 738 739 if (sc->isrcs != NULL) 740 tegra_gpio_pic_detach(sc); 741 742 gpiobus_detach_bus(dev); 743 744 for (i = 0; i < GPIO_NUM_BANKS; i++) { 745 if (sc->irq_res[i] != NULL) 746 bus_release_resource(dev, SYS_RES_IRQ, 0, 747 sc->irq_res[i]); 748 } 749 if (sc->mem_res != NULL) 750 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 751 GPIO_LOCK_DESTROY(sc); 752 753 return(0); 754 } 755 756 static int 757 tegra_gpio_attach(device_t dev) 758 { 759 struct tegra_gpio_softc *sc; 760 int i, rid; 761 762 sc = device_get_softc(dev); 763 sc->dev = dev; 764 GPIO_LOCK_INIT(sc); 765 766 /* Allocate bus_space resources. */ 767 rid = 0; 768 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 769 RF_ACTIVE); 770 if (sc->mem_res == NULL) { 771 device_printf(dev, "Cannot allocate memory resources\n"); 772 tegra_gpio_detach(dev); 773 return (ENXIO); 774 } 775 776 sc->gpio_npins = NGPIO; 777 for (i = 0; i < sc->gpio_npins; i++) { 778 sc->gpio_pins[i].gp_pin = i; 779 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 780 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 781 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 782 GPIO_INTR_EDGE_BOTH; 783 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d", 784 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG], 785 i % GPIO_PINS_IN_REG); 786 sc->gpio_pins[i].gp_flags = 787 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ? 788 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 789 } 790 791 /* Init interrupt related registes. */ 792 for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) { 793 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0); 794 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF); 795 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF); 796 } 797 798 /* Allocate interrupts. */ 799 for (i = 0; i < GPIO_NUM_BANKS; i++) { 800 sc->irq_cookies[i].sc = sc; 801 sc->irq_cookies[i].bank_num = i; 802 rid = i; 803 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 804 &rid, RF_ACTIVE); 805 if (sc->irq_res[i] == NULL) { 806 device_printf(dev, "Cannot allocate IRQ resources\n"); 807 tegra_gpio_detach(dev); 808 return (ENXIO); 809 } 810 if ((bus_setup_intr(dev, sc->irq_res[i], 811 INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL, 812 &sc->irq_cookies[i], &sc->irq_ih[i]))) { 813 device_printf(dev, 814 "WARNING: unable to register interrupt handler\n"); 815 tegra_gpio_detach(dev); 816 return (ENXIO); 817 } 818 } 819 820 if (tegra_gpio_pic_attach(sc) != 0) { 821 device_printf(dev, "WARNING: unable to attach PIC\n"); 822 tegra_gpio_detach(dev); 823 return (ENXIO); 824 } 825 826 sc->busdev = gpiobus_attach_bus(dev); 827 if (sc->busdev == NULL) { 828 tegra_gpio_detach(dev); 829 return (ENXIO); 830 } 831 832 return (bus_generic_attach(dev)); 833 } 834 835 static int 836 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 837 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 838 { 839 840 if (gcells != 2) 841 return (ERANGE); 842 *pin = gpios[0]; 843 *flags= gpios[1]; 844 return (0); 845 } 846 847 static phandle_t 848 tegra_gpio_get_node(device_t bus, device_t dev) 849 { 850 851 /* We only have one child, the GPIO bus, which needs our own node. */ 852 return (ofw_bus_get_node(bus)); 853 } 854 855 static device_method_t tegra_gpio_methods[] = { 856 DEVMETHOD(device_probe, tegra_gpio_probe), 857 DEVMETHOD(device_attach, tegra_gpio_attach), 858 DEVMETHOD(device_detach, tegra_gpio_detach), 859 860 /* Interrupt controller interface */ 861 DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr), 862 DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr), 863 DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr), 864 DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr), 865 DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr), 866 DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter), 867 DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread), 868 DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread), 869 870 /* GPIO protocol */ 871 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus), 872 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max), 873 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname), 874 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags), 875 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps), 876 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags), 877 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get), 878 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set), 879 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle), 880 DEVMETHOD(gpio_map_gpios, tegra_map_gpios), 881 882 /* ofw_bus interface */ 883 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node), 884 885 DEVMETHOD_END 886 }; 887 888 static devclass_t tegra_gpio_devclass; 889 static DEFINE_CLASS_0(gpio, tegra_gpio_driver, tegra_gpio_methods, 890 sizeof(struct tegra_gpio_softc)); 891 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver, 892 tegra_gpio_devclass, NULL, NULL, 70); 893