1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 /* 29 * Tegra GPIO driver. 30 */ 31 #include "opt_platform.h" 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/gpio.h> 36 #include <sys/kernel.h> 37 #include <sys/proc.h> 38 #include <sys/rman.h> 39 #include <sys/lock.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 #include <machine/resource.h> 46 47 #include <dev/gpio/gpiobusvar.h> 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "pic_if.h" 53 54 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 55 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 56 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \ 57 device_get_nameunit(_sc->dev), "tegra_gpio", MTX_DEF) 58 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); 59 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); 60 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED); 61 62 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 63 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 64 65 #define GPIO_BANK_OFFS 0x100 /* Bank offset */ 66 #define GPIO_NUM_BANKS 8 /* Total number per bank */ 67 #define GPIO_REGS_IN_BANK 4 /* Total registers in bank */ 68 #define GPIO_PINS_IN_REG 8 /* Total pin in register */ 69 70 #define GPIO_BANKNUM(n) ((n) / (GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG)) 71 #define GPIO_PORTNUM(n) (((n) / GPIO_PINS_IN_REG) % GPIO_REGS_IN_BANK) 72 #define GPIO_BIT(n) ((n) % GPIO_PINS_IN_REG) 73 74 #define GPIO_REGNUM(n) (GPIO_BANKNUM(n) * GPIO_BANK_OFFS + \ 75 GPIO_PORTNUM(n) * 4) 76 77 #define NGPIO ((GPIO_NUM_BANKS * GPIO_REGS_IN_BANK * GPIO_PINS_IN_REG) - 8) 78 79 /* Register offsets */ 80 #define GPIO_CNF 0x00 81 #define GPIO_OE 0x10 82 #define GPIO_OUT 0x20 83 #define GPIO_IN 0x30 84 #define GPIO_INT_STA 0x40 85 #define GPIO_INT_ENB 0x50 86 #define GPIO_INT_LVL 0x60 87 #define GPIO_INT_LVL_DELTA (1 << 16) 88 #define GPIO_INT_LVL_EDGE (1 << 8) 89 #define GPIO_INT_LVL_HIGH (1 << 0) 90 #define GPIO_INT_LVL_MASK (GPIO_INT_LVL_DELTA | \ 91 GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH) 92 #define GPIO_INT_CLR 0x70 93 #define GPIO_MSK_CNF 0x80 94 #define GPIO_MSK_OE 0x90 95 #define GPIO_MSK_OUT 0xA0 96 #define GPIO_MSK_INT_STA 0xC0 97 #define GPIO_MSK_INT_ENB 0xD0 98 #define GPIO_MSK_INT_LVL 0xE0 99 100 char *tegra_gpio_port_names[] = { 101 "A", "B", "C", "D", /* Bank 0 */ 102 "E", "F", "G", "H", /* Bank 1 */ 103 "I", "J", "K", "L", /* Bank 2 */ 104 "M", "N", "O", "P", /* Bank 3 */ 105 "Q", "R", "S", "T", /* Bank 4 */ 106 "U", "V", "W", "X", /* Bank 5 */ 107 "Y", "Z", "AA", "BB", /* Bank 6 */ 108 "CC", "DD", "EE" /* Bank 7 */ 109 }; 110 111 struct tegra_gpio_irqsrc { 112 struct intr_irqsrc isrc; 113 u_int irq; 114 uint32_t cfgreg; 115 }; 116 117 struct tegra_gpio_softc; 118 struct tegra_gpio_irq_cookie { 119 struct tegra_gpio_softc *sc; 120 int bank_num; 121 }; 122 123 struct tegra_gpio_softc { 124 device_t dev; 125 device_t busdev; 126 struct mtx mtx; 127 struct resource *mem_res; 128 struct resource *irq_res[GPIO_NUM_BANKS]; 129 void *irq_ih[GPIO_NUM_BANKS]; 130 struct tegra_gpio_irq_cookie irq_cookies[GPIO_NUM_BANKS]; 131 int gpio_npins; 132 struct gpio_pin gpio_pins[NGPIO]; 133 struct tegra_gpio_irqsrc *isrcs; 134 }; 135 136 static struct ofw_compat_data compat_data[] = { 137 {"nvidia,tegra124-gpio", 1}, 138 {"nvidia,tegra210-gpio", 1}, 139 {NULL, 0} 140 }; 141 142 /* -------------------------------------------------------------------------- 143 * 144 * GPIO 145 * 146 */ 147 static inline void 148 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, 149 struct gpio_pin *pin, uint32_t val) 150 { 151 uint32_t tmp; 152 int bit; 153 154 bit = GPIO_BIT(pin->gp_pin); 155 tmp = 0x100 << bit; /* mask */ 156 tmp |= (val & 1) << bit; /* value */ 157 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp); 158 } 159 160 static inline uint32_t 161 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) 162 { 163 int bit; 164 uint32_t val; 165 166 bit = GPIO_BIT(pin->gp_pin); 167 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin)); 168 return (val >> bit) & 1; 169 } 170 171 static void 172 tegra_gpio_pin_configure(struct tegra_gpio_softc *sc, struct gpio_pin *pin, 173 unsigned int flags) 174 { 175 176 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0) 177 return; 178 179 /* Manage input/output */ 180 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 181 if (flags & GPIO_PIN_OUTPUT) { 182 pin->gp_flags |= GPIO_PIN_OUTPUT; 183 gpio_write_masked(sc, GPIO_MSK_OE, pin, 1); 184 } else { 185 pin->gp_flags |= GPIO_PIN_INPUT; 186 gpio_write_masked(sc, GPIO_MSK_OE, pin, 0); 187 } 188 } 189 190 static device_t 191 tegra_gpio_get_bus(device_t dev) 192 { 193 struct tegra_gpio_softc *sc; 194 195 sc = device_get_softc(dev); 196 return (sc->busdev); 197 } 198 199 static int 200 tegra_gpio_pin_max(device_t dev, int *maxpin) 201 { 202 203 *maxpin = NGPIO - 1; 204 return (0); 205 } 206 207 static int 208 tegra_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 209 { 210 struct tegra_gpio_softc *sc; 211 212 sc = device_get_softc(dev); 213 if (pin >= sc->gpio_npins) 214 return (EINVAL); 215 216 GPIO_LOCK(sc); 217 *caps = sc->gpio_pins[pin].gp_caps; 218 GPIO_UNLOCK(sc); 219 220 return (0); 221 } 222 223 static int 224 tegra_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 225 { 226 struct tegra_gpio_softc *sc; 227 int cnf; 228 229 sc = device_get_softc(dev); 230 if (pin >= sc->gpio_npins) 231 return (EINVAL); 232 233 GPIO_LOCK(sc); 234 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 235 if (cnf == 0) { 236 GPIO_UNLOCK(sc); 237 return (ENXIO); 238 } 239 *flags = sc->gpio_pins[pin].gp_flags; 240 GPIO_UNLOCK(sc); 241 242 return (0); 243 } 244 245 static int 246 tegra_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 247 { 248 struct tegra_gpio_softc *sc; 249 250 sc = device_get_softc(dev); 251 if (pin >= sc->gpio_npins) 252 return (EINVAL); 253 254 GPIO_LOCK(sc); 255 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 256 GPIO_UNLOCK(sc); 257 258 return (0); 259 } 260 261 static int 262 tegra_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 263 { 264 struct tegra_gpio_softc *sc; 265 int cnf; 266 267 sc = device_get_softc(dev); 268 if (pin >= sc->gpio_npins) 269 return (EINVAL); 270 271 GPIO_LOCK(sc); 272 cnf = gpio_read(sc, GPIO_CNF, &sc->gpio_pins[pin]); 273 if (cnf == 0) { 274 /* XXX - allow this for while .... 275 GPIO_UNLOCK(sc); 276 return (ENXIO); 277 */ 278 gpio_write_masked(sc, GPIO_MSK_CNF, &sc->gpio_pins[pin], 1); 279 } 280 tegra_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 281 GPIO_UNLOCK(sc); 282 283 return (0); 284 } 285 286 static int 287 tegra_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 288 { 289 struct tegra_gpio_softc *sc; 290 291 sc = device_get_softc(dev); 292 if (pin >= sc->gpio_npins) 293 return (EINVAL); 294 GPIO_LOCK(sc); 295 gpio_write_masked(sc, GPIO_MSK_OUT, &sc->gpio_pins[pin], value); 296 GPIO_UNLOCK(sc); 297 298 return (0); 299 } 300 301 static int 302 tegra_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 303 { 304 struct tegra_gpio_softc *sc; 305 306 sc = device_get_softc(dev); 307 if (pin >= sc->gpio_npins) 308 return (EINVAL); 309 310 GPIO_LOCK(sc); 311 *val = gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]); 312 GPIO_UNLOCK(sc); 313 314 return (0); 315 } 316 317 static int 318 tegra_gpio_pin_toggle(device_t dev, uint32_t pin) 319 { 320 struct tegra_gpio_softc *sc; 321 322 sc = device_get_softc(dev); 323 if (pin >= sc->gpio_npins) 324 return (EINVAL); 325 326 GPIO_LOCK(sc); 327 gpio_write_masked(sc, GPIO_MSK_OE, &sc->gpio_pins[pin], 328 gpio_read(sc, GPIO_IN, &sc->gpio_pins[pin]) ^ 1); 329 GPIO_UNLOCK(sc); 330 331 return (0); 332 } 333 334 /* -------------------------------------------------------------------------- 335 * 336 * Interrupts 337 * 338 */ 339 static inline void 340 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg, 341 struct tegra_gpio_irqsrc *tgi, uint32_t val) 342 { 343 uint32_t tmp; 344 int bit; 345 346 bit = GPIO_BIT(tgi->irq); 347 tmp = 0x100 << bit; /* mask */ 348 tmp |= (val & 1) << bit; /* value */ 349 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 350 } 351 352 static inline void 353 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg, 354 struct tegra_gpio_irqsrc *tgi, uint32_t val, uint32_t mask) 355 { 356 uint32_t tmp; 357 int bit; 358 359 bit = GPIO_BIT(tgi->irq); 360 GPIO_LOCK(sc); 361 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq)); 362 tmp &= ~(mask << bit); 363 tmp |= val << bit; 364 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp); 365 GPIO_UNLOCK(sc); 366 } 367 368 static inline void 369 tegra_gpio_isrc_mask(struct tegra_gpio_softc *sc, 370 struct tegra_gpio_irqsrc *tgi, uint32_t val) 371 { 372 373 intr_write_masked(sc, GPIO_MSK_INT_ENB, tgi, val); 374 } 375 376 static inline void 377 tegra_gpio_isrc_eoi(struct tegra_gpio_softc *sc, 378 struct tegra_gpio_irqsrc *tgi) 379 { 380 381 intr_write_masked(sc, GPIO_INT_CLR, tgi, 1); 382 } 383 384 static inline bool 385 tegra_gpio_isrc_is_level(struct tegra_gpio_irqsrc *tgi) 386 { 387 388 return (tgi->cfgreg & GPIO_INT_LVL_EDGE); 389 } 390 391 static int 392 tegra_gpio_intr(void *arg) 393 { 394 u_int irq, i, j, val, basepin; 395 struct tegra_gpio_softc *sc; 396 struct trapframe *tf; 397 struct tegra_gpio_irqsrc *tgi; 398 struct tegra_gpio_irq_cookie *cookie; 399 400 cookie = (struct tegra_gpio_irq_cookie *)arg; 401 sc = cookie->sc; 402 tf = curthread->td_intr_frame; 403 404 for (i = 0; i < GPIO_REGS_IN_BANK; i++) { 405 basepin = cookie->bank_num * GPIO_REGS_IN_BANK * 406 GPIO_PINS_IN_REG + i * GPIO_PINS_IN_REG; 407 408 val = bus_read_4(sc->mem_res, GPIO_INT_STA + 409 GPIO_REGNUM(basepin)); 410 val &= bus_read_4(sc->mem_res, GPIO_INT_ENB + 411 GPIO_REGNUM(basepin)); 412 /* Interrupt handling */ 413 for (j = 0; j < GPIO_PINS_IN_REG; j++) { 414 if ((val & (1 << j)) == 0) 415 continue; 416 irq = basepin + j; 417 tgi = &sc->isrcs[irq]; 418 if (!tegra_gpio_isrc_is_level(tgi)) 419 tegra_gpio_isrc_eoi(sc, tgi); 420 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { 421 tegra_gpio_isrc_mask(sc, tgi, 0); 422 if (tegra_gpio_isrc_is_level(tgi)) 423 tegra_gpio_isrc_eoi(sc, tgi); 424 device_printf(sc->dev, 425 "Stray irq %u disabled\n", irq); 426 } 427 } 428 } 429 430 return (FILTER_HANDLED); 431 } 432 433 static int 434 tegra_gpio_pic_attach(struct tegra_gpio_softc *sc) 435 { 436 int error; 437 uint32_t irq; 438 const char *name; 439 440 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, 441 M_WAITOK | M_ZERO); 442 443 name = device_get_nameunit(sc->dev); 444 for (irq = 0; irq < sc->gpio_npins; irq++) { 445 sc->isrcs[irq].irq = irq; 446 sc->isrcs[irq].cfgreg = 0; 447 error = intr_isrc_register(&sc->isrcs[irq].isrc, 448 sc->dev, 0, "%s,%u", name, irq); 449 if (error != 0) 450 return (error); /* XXX deregister ISRCs */ 451 } 452 if (intr_pic_register(sc->dev, 453 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) 454 return (ENXIO); 455 456 return (0); 457 } 458 459 static int 460 tegra_gpio_pic_detach(struct tegra_gpio_softc *sc) 461 { 462 463 /* 464 * There has not been established any procedure yet 465 * how to detach PIC from living system correctly. 466 */ 467 device_printf(sc->dev, "%s: not implemented yet\n", __func__); 468 return (EBUSY); 469 } 470 471 static void 472 tegra_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 473 { 474 struct tegra_gpio_softc *sc; 475 struct tegra_gpio_irqsrc *tgi; 476 477 sc = device_get_softc(dev); 478 tgi = (struct tegra_gpio_irqsrc *)isrc; 479 tegra_gpio_isrc_mask(sc, tgi, 0); 480 } 481 482 static void 483 tegra_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 484 { 485 struct tegra_gpio_softc *sc; 486 struct tegra_gpio_irqsrc *tgi; 487 488 sc = device_get_softc(dev); 489 tgi = (struct tegra_gpio_irqsrc *)isrc; 490 tegra_gpio_isrc_mask(sc, tgi, 1); 491 } 492 493 static int 494 tegra_gpio_pic_map_fdt(struct tegra_gpio_softc *sc, u_int ncells, 495 pcell_t *cells, u_int *irqp, uint32_t *regp) 496 { 497 uint32_t reg; 498 499 /* 500 * The first cell is the interrupt number. 501 * The second cell is used to specify flags: 502 * bits[3:0] trigger type and level flags: 503 * 1 = low-to-high edge triggered. 504 * 2 = high-to-low edge triggered. 505 * 4 = active high level-sensitive. 506 * 8 = active low level-sensitive. 507 */ 508 if (ncells != 2 || cells[0] >= sc->gpio_npins) 509 return (EINVAL); 510 511 /* 512 * All interrupt types could be set for an interrupt at one moment. 513 * At least, the combination of 'low-to-high' and 'high-to-low' edge 514 * triggered interrupt types can make a sense. 515 */ 516 if (cells[1] == 1) 517 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 518 else if (cells[1] == 2) 519 reg = GPIO_INT_LVL_EDGE; 520 else if (cells[1] == 3) 521 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 522 else if (cells[1] == 4) 523 reg = GPIO_INT_LVL_HIGH; 524 else if (cells[1] == 8) 525 reg = 0; 526 else 527 return (EINVAL); 528 529 *irqp = cells[0]; 530 if (regp != NULL) 531 *regp = reg; 532 return (0); 533 } 534 535 static int 536 tegra_gpio_pic_map_gpio(struct tegra_gpio_softc *sc, u_int gpio_pin_num, 537 u_int gpio_pin_flags, u_int intr_mode, u_int *irqp, uint32_t *regp) 538 { 539 540 uint32_t reg; 541 542 if (gpio_pin_num >= sc->gpio_npins) 543 return (EINVAL); 544 switch (intr_mode) { 545 case GPIO_INTR_CONFORM: 546 case GPIO_INTR_LEVEL_LOW: 547 reg = 0; 548 break; 549 case GPIO_INTR_LEVEL_HIGH: 550 reg = GPIO_INT_LVL_HIGH; 551 break; 552 case GPIO_INTR_EDGE_RISING: 553 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_HIGH; 554 break; 555 case GPIO_INTR_EDGE_FALLING: 556 reg = GPIO_INT_LVL_EDGE; 557 break; 558 case GPIO_INTR_EDGE_BOTH: 559 reg = GPIO_INT_LVL_EDGE | GPIO_INT_LVL_DELTA; 560 break; 561 default: 562 return (EINVAL); 563 } 564 *irqp = gpio_pin_num; 565 if (regp != NULL) 566 *regp = reg; 567 return (0); 568 } 569 570 static int 571 tegra_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 572 struct intr_irqsrc **isrcp) 573 { 574 int rv; 575 u_int irq; 576 struct tegra_gpio_softc *sc; 577 578 sc = device_get_softc(dev); 579 580 if (data->type == INTR_MAP_DATA_FDT) { 581 struct intr_map_data_fdt *daf; 582 583 daf = (struct intr_map_data_fdt *)data; 584 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 585 NULL); 586 } else if (data->type == INTR_MAP_DATA_GPIO) { 587 struct intr_map_data_gpio *dag; 588 589 dag = (struct intr_map_data_gpio *)data; 590 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 591 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL); 592 } else 593 return (ENOTSUP); 594 595 if (rv == 0) 596 *isrcp = &sc->isrcs[irq].isrc; 597 return (rv); 598 } 599 600 static void 601 tegra_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 602 { 603 struct tegra_gpio_softc *sc; 604 struct tegra_gpio_irqsrc *tgi; 605 606 sc = device_get_softc(dev); 607 tgi = (struct tegra_gpio_irqsrc *)isrc; 608 if (tegra_gpio_isrc_is_level(tgi)) 609 tegra_gpio_isrc_eoi(sc, tgi); 610 } 611 612 static void 613 tegra_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 614 { 615 struct tegra_gpio_softc *sc; 616 struct tegra_gpio_irqsrc *tgi; 617 618 sc = device_get_softc(dev); 619 tgi = (struct tegra_gpio_irqsrc *)isrc; 620 tegra_gpio_isrc_mask(sc, tgi, 1); 621 } 622 623 static void 624 tegra_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 625 { 626 struct tegra_gpio_softc *sc; 627 struct tegra_gpio_irqsrc *tgi; 628 629 sc = device_get_softc(dev); 630 tgi = (struct tegra_gpio_irqsrc *)isrc; 631 632 tegra_gpio_isrc_mask(sc, tgi, 0); 633 if (tegra_gpio_isrc_is_level(tgi)) 634 tegra_gpio_isrc_eoi(sc, tgi); 635 } 636 637 static int 638 tegra_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 639 struct resource *res, struct intr_map_data *data) 640 { 641 u_int irq; 642 uint32_t cfgreg; 643 int rv; 644 struct tegra_gpio_softc *sc; 645 struct tegra_gpio_irqsrc *tgi; 646 647 sc = device_get_softc(dev); 648 tgi = (struct tegra_gpio_irqsrc *)isrc; 649 650 if (data == NULL) 651 return (ENOTSUP); 652 653 /* Get and check config for an interrupt. */ 654 if (data->type == INTR_MAP_DATA_FDT) { 655 struct intr_map_data_fdt *daf; 656 657 daf = (struct intr_map_data_fdt *)data; 658 rv = tegra_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, 659 &cfgreg); 660 } else if (data->type == INTR_MAP_DATA_GPIO) { 661 struct intr_map_data_gpio *dag; 662 663 dag = (struct intr_map_data_gpio *)data; 664 rv = tegra_gpio_pic_map_gpio(sc, dag->gpio_pin_num, 665 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, &cfgreg); 666 } else 667 return (ENOTSUP); 668 if (rv != 0) 669 return (EINVAL); 670 671 /* 672 * If this is a setup for another handler, 673 * only check that its configuration match. 674 */ 675 if (isrc->isrc_handlers != 0) 676 return (tgi->cfgreg == cfgreg ? 0 : EINVAL); 677 678 tgi->cfgreg = cfgreg; 679 intr_write_modify(sc, GPIO_INT_LVL, tgi, cfgreg, GPIO_INT_LVL_MASK); 680 tegra_gpio_pic_enable_intr(dev, isrc); 681 682 return (0); 683 } 684 685 static int 686 tegra_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 687 struct resource *res, struct intr_map_data *data) 688 { 689 struct tegra_gpio_softc *sc; 690 struct tegra_gpio_irqsrc *tgi; 691 692 sc = device_get_softc(dev); 693 tgi = (struct tegra_gpio_irqsrc *)isrc; 694 695 if (isrc->isrc_handlers == 0) 696 tegra_gpio_isrc_mask(sc, tgi, 0); 697 return (0); 698 } 699 700 static int 701 tegra_gpio_probe(device_t dev) 702 { 703 704 if (!ofw_bus_status_okay(dev)) 705 return (ENXIO); 706 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 707 device_set_desc(dev, "Tegra GPIO Controller"); 708 return (BUS_PROBE_DEFAULT); 709 } 710 711 return (ENXIO); 712 } 713 714 /* -------------------------------------------------------------------------- 715 * 716 * Bus 717 * 718 */ 719 static int 720 tegra_gpio_detach(device_t dev) 721 { 722 struct tegra_gpio_softc *sc; 723 int i; 724 725 sc = device_get_softc(dev); 726 727 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); 728 729 for (i = 0; i < GPIO_NUM_BANKS; i++) { 730 if (sc->irq_ih[i] != NULL) 731 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); 732 } 733 734 if (sc->isrcs != NULL) 735 tegra_gpio_pic_detach(sc); 736 737 gpiobus_detach_bus(dev); 738 739 for (i = 0; i < GPIO_NUM_BANKS; i++) { 740 if (sc->irq_res[i] != NULL) 741 bus_release_resource(dev, SYS_RES_IRQ, 0, 742 sc->irq_res[i]); 743 } 744 if (sc->mem_res != NULL) 745 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 746 GPIO_LOCK_DESTROY(sc); 747 748 return(0); 749 } 750 751 static int 752 tegra_gpio_attach(device_t dev) 753 { 754 struct tegra_gpio_softc *sc; 755 int i, rid; 756 757 sc = device_get_softc(dev); 758 sc->dev = dev; 759 GPIO_LOCK_INIT(sc); 760 761 /* Allocate bus_space resources. */ 762 rid = 0; 763 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 764 RF_ACTIVE); 765 if (sc->mem_res == NULL) { 766 device_printf(dev, "Cannot allocate memory resources\n"); 767 tegra_gpio_detach(dev); 768 return (ENXIO); 769 } 770 771 sc->gpio_npins = NGPIO; 772 for (i = 0; i < sc->gpio_npins; i++) { 773 sc->gpio_pins[i].gp_pin = i; 774 sc->gpio_pins[i].gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 775 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 776 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 777 GPIO_INTR_EDGE_BOTH; 778 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "gpio_%s.%d", 779 tegra_gpio_port_names[ i / GPIO_PINS_IN_REG], 780 i % GPIO_PINS_IN_REG); 781 sc->gpio_pins[i].gp_flags = 782 gpio_read(sc, GPIO_OE, &sc->gpio_pins[i]) != 0 ? 783 GPIO_PIN_OUTPUT : GPIO_PIN_INPUT; 784 } 785 786 /* Init interrupt related registes. */ 787 for (i = 0; i < sc->gpio_npins; i += GPIO_PINS_IN_REG) { 788 bus_write_4(sc->mem_res, GPIO_INT_ENB + GPIO_REGNUM(i), 0); 789 bus_write_4(sc->mem_res, GPIO_INT_STA + GPIO_REGNUM(i), 0xFF); 790 bus_write_4(sc->mem_res, GPIO_INT_CLR + GPIO_REGNUM(i), 0xFF); 791 } 792 793 /* Allocate interrupts. */ 794 for (i = 0; i < GPIO_NUM_BANKS; i++) { 795 sc->irq_cookies[i].sc = sc; 796 sc->irq_cookies[i].bank_num = i; 797 rid = i; 798 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 799 &rid, RF_ACTIVE); 800 if (sc->irq_res[i] == NULL) { 801 device_printf(dev, "Cannot allocate IRQ resources\n"); 802 tegra_gpio_detach(dev); 803 return (ENXIO); 804 } 805 if ((bus_setup_intr(dev, sc->irq_res[i], 806 INTR_TYPE_MISC | INTR_MPSAFE, tegra_gpio_intr, NULL, 807 &sc->irq_cookies[i], &sc->irq_ih[i]))) { 808 device_printf(dev, 809 "WARNING: unable to register interrupt handler\n"); 810 tegra_gpio_detach(dev); 811 return (ENXIO); 812 } 813 } 814 815 if (tegra_gpio_pic_attach(sc) != 0) { 816 device_printf(dev, "WARNING: unable to attach PIC\n"); 817 tegra_gpio_detach(dev); 818 return (ENXIO); 819 } 820 821 sc->busdev = gpiobus_attach_bus(dev); 822 if (sc->busdev == NULL) { 823 tegra_gpio_detach(dev); 824 return (ENXIO); 825 } 826 827 return (bus_generic_attach(dev)); 828 } 829 830 static int 831 tegra_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent, 832 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) 833 { 834 835 if (gcells != 2) 836 return (ERANGE); 837 *pin = gpios[0]; 838 *flags= gpios[1]; 839 return (0); 840 } 841 842 static phandle_t 843 tegra_gpio_get_node(device_t bus, device_t dev) 844 { 845 846 /* We only have one child, the GPIO bus, which needs our own node. */ 847 return (ofw_bus_get_node(bus)); 848 } 849 850 static device_method_t tegra_gpio_methods[] = { 851 DEVMETHOD(device_probe, tegra_gpio_probe), 852 DEVMETHOD(device_attach, tegra_gpio_attach), 853 DEVMETHOD(device_detach, tegra_gpio_detach), 854 855 /* Interrupt controller interface */ 856 DEVMETHOD(pic_disable_intr, tegra_gpio_pic_disable_intr), 857 DEVMETHOD(pic_enable_intr, tegra_gpio_pic_enable_intr), 858 DEVMETHOD(pic_map_intr, tegra_gpio_pic_map_intr), 859 DEVMETHOD(pic_setup_intr, tegra_gpio_pic_setup_intr), 860 DEVMETHOD(pic_teardown_intr, tegra_gpio_pic_teardown_intr), 861 DEVMETHOD(pic_post_filter, tegra_gpio_pic_post_filter), 862 DEVMETHOD(pic_post_ithread, tegra_gpio_pic_post_ithread), 863 DEVMETHOD(pic_pre_ithread, tegra_gpio_pic_pre_ithread), 864 865 /* GPIO protocol */ 866 DEVMETHOD(gpio_get_bus, tegra_gpio_get_bus), 867 DEVMETHOD(gpio_pin_max, tegra_gpio_pin_max), 868 DEVMETHOD(gpio_pin_getname, tegra_gpio_pin_getname), 869 DEVMETHOD(gpio_pin_getflags, tegra_gpio_pin_getflags), 870 DEVMETHOD(gpio_pin_getcaps, tegra_gpio_pin_getcaps), 871 DEVMETHOD(gpio_pin_setflags, tegra_gpio_pin_setflags), 872 DEVMETHOD(gpio_pin_get, tegra_gpio_pin_get), 873 DEVMETHOD(gpio_pin_set, tegra_gpio_pin_set), 874 DEVMETHOD(gpio_pin_toggle, tegra_gpio_pin_toggle), 875 DEVMETHOD(gpio_map_gpios, tegra_map_gpios), 876 877 /* ofw_bus interface */ 878 DEVMETHOD(ofw_bus_get_node, tegra_gpio_get_node), 879 880 DEVMETHOD_END 881 }; 882 883 static DEFINE_CLASS_0(gpio, tegra_gpio_driver, tegra_gpio_methods, 884 sizeof(struct tegra_gpio_softc)); 885 EARLY_DRIVER_MODULE(tegra_gpio, simplebus, tegra_gpio_driver, NULL, NULL, 70); 886