1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _TEGRA_EFUSE_H_ 28 29 enum tegra_revision { 30 TEGRA_REVISION_UNKNOWN = 0, 31 TEGRA_REVISION_A01, 32 TEGRA_REVISION_A02, 33 TEGRA_REVISION_A03, 34 TEGRA_REVISION_A03p, 35 TEGRA_REVISION_A04, 36 }; 37 38 struct tegra_sku_info { 39 u_int chip_id; 40 u_int sku_id; 41 u_int cpu_process_id; 42 u_int cpu_speedo_id; 43 u_int cpu_speedo_value; 44 u_int cpu_iddq_value; 45 u_int soc_process_id; 46 u_int soc_speedo_id; 47 u_int soc_speedo_value; 48 u_int soc_iddq_value; 49 u_int gpu_process_id; 50 u_int gpu_speedo_id; 51 u_int gpu_speedo_value; 52 u_int gpu_iddq_value; 53 enum tegra_revision revision; 54 }; 55 56 extern struct tegra_sku_info tegra_sku_info; 57 uint32_t tegra_fuse_read_4(int addr); 58 59 #endif /* _TEGRA_EFUSE_H_ */ 60