1*ef2ee5d0SMichal Meloun /*- 2*ef2ee5d0SMichal Meloun * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3*ef2ee5d0SMichal Meloun * All rights reserved. 4*ef2ee5d0SMichal Meloun * 5*ef2ee5d0SMichal Meloun * Redistribution and use in source and binary forms, with or without 6*ef2ee5d0SMichal Meloun * modification, are permitted provided that the following conditions 7*ef2ee5d0SMichal Meloun * are met: 8*ef2ee5d0SMichal Meloun * 1. Redistributions of source code must retain the above copyright 9*ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer. 10*ef2ee5d0SMichal Meloun * 2. Redistributions in binary form must reproduce the above copyright 11*ef2ee5d0SMichal Meloun * notice, this list of conditions and the following disclaimer in the 12*ef2ee5d0SMichal Meloun * documentation and/or other materials provided with the distribution. 13*ef2ee5d0SMichal Meloun * 14*ef2ee5d0SMichal Meloun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15*ef2ee5d0SMichal Meloun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16*ef2ee5d0SMichal Meloun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17*ef2ee5d0SMichal Meloun * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18*ef2ee5d0SMichal Meloun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19*ef2ee5d0SMichal Meloun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20*ef2ee5d0SMichal Meloun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*ef2ee5d0SMichal Meloun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22*ef2ee5d0SMichal Meloun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23*ef2ee5d0SMichal Meloun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24*ef2ee5d0SMichal Meloun * SUCH DAMAGE. 25*ef2ee5d0SMichal Meloun */ 26*ef2ee5d0SMichal Meloun 27*ef2ee5d0SMichal Meloun #ifndef _TEGRA_EFUSE_H_ 28*ef2ee5d0SMichal Meloun 29*ef2ee5d0SMichal Meloun enum tegra_revision { 30*ef2ee5d0SMichal Meloun TEGRA_REVISION_UNKNOWN = 0, 31*ef2ee5d0SMichal Meloun TEGRA_REVISION_A01, 32*ef2ee5d0SMichal Meloun TEGRA_REVISION_A02, 33*ef2ee5d0SMichal Meloun TEGRA_REVISION_A03, 34*ef2ee5d0SMichal Meloun TEGRA_REVISION_A03p, 35*ef2ee5d0SMichal Meloun TEGRA_REVISION_A04, 36*ef2ee5d0SMichal Meloun }; 37*ef2ee5d0SMichal Meloun 38*ef2ee5d0SMichal Meloun struct tegra_sku_info { 39*ef2ee5d0SMichal Meloun u_int chip_id; 40*ef2ee5d0SMichal Meloun u_int sku_id; 41*ef2ee5d0SMichal Meloun u_int cpu_process_id; 42*ef2ee5d0SMichal Meloun u_int cpu_speedo_id; 43*ef2ee5d0SMichal Meloun u_int cpu_speedo_value; 44*ef2ee5d0SMichal Meloun u_int cpu_iddq_value; 45*ef2ee5d0SMichal Meloun u_int soc_process_id; 46*ef2ee5d0SMichal Meloun u_int soc_speedo_id; 47*ef2ee5d0SMichal Meloun u_int soc_speedo_value; 48*ef2ee5d0SMichal Meloun u_int soc_iddq_value; 49*ef2ee5d0SMichal Meloun u_int gpu_process_id; 50*ef2ee5d0SMichal Meloun u_int gpu_speedo_id; 51*ef2ee5d0SMichal Meloun u_int gpu_speedo_value; 52*ef2ee5d0SMichal Meloun u_int gpu_iddq_value; 53*ef2ee5d0SMichal Meloun enum tegra_revision revision; 54*ef2ee5d0SMichal Meloun }; 55*ef2ee5d0SMichal Meloun 56*ef2ee5d0SMichal Meloun extern struct tegra_sku_info tegra_sku_info; 57*ef2ee5d0SMichal Meloun uint32_t tegra_fuse_read_4(int addr); 58*ef2ee5d0SMichal Meloun 59*ef2ee5d0SMichal Meloun #endif /* _TEGRA_EFUSE_H_ */ 60