1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * AHCI driver for Tegra SoCs. 32 */ 33 #include <sys/param.h> 34 #include <sys/module.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 48 #include <dev/ahci/ahci.h> 49 #include <dev/extres/clk/clk.h> 50 #include <dev/extres/hwreset/hwreset.h> 51 #include <dev/extres/phy/phy.h> 52 #include <dev/extres/regulator/regulator.h> 53 #include <dev/fdt/fdt_pinctrl.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include <arm/nvidia/tegra_efuse.h> 58 #include <arm/nvidia/tegra_pmc.h> 59 60 #define AHCI_WR4(_sc, _r, _v) bus_write_4((_sc)->ctlr.r_mem, (_r), (_v)) 61 #define AHCI_RD4(_sc, _r) bus_read_4((_sc)->ctlr.r_mem, (_r)) 62 #define SATA_WR4(_sc, _r, _v) bus_write_4((_sc)->sata_mem, (_r), (_v)) 63 #define SATA_RD4(_sc, _r) bus_read_4((_sc)->sata_mem, (_r)) 64 65 static struct ofw_compat_data compat_data[] = { 66 {"nvidia,tegra124-ahci", 1}, 67 {NULL, 0} 68 }; 69 70 struct tegra_ahci_sc { 71 struct ahci_controller ctlr; /* Must be first */ 72 device_t dev; 73 struct resource *sata_mem; 74 clk_t clk_sata; 75 clk_t clk_sata_oob; 76 clk_t clk_pll_e; 77 clk_t clk_cml; 78 hwreset_t hwreset_sata; 79 hwreset_t hwreset_sata_oob; 80 hwreset_t hwreset_sata_cold; 81 regulator_t supply_hvdd; 82 regulator_t supply_vddio; 83 regulator_t supply_avdd; 84 regulator_t supply_target_5v; 85 regulator_t supply_target_12v; 86 phy_t phy; 87 }; 88 89 struct sata_pad_calibration { 90 uint32_t gen1_tx_amp; 91 uint32_t gen1_tx_peak; 92 uint32_t gen2_tx_amp; 93 uint32_t gen2_tx_peak; 94 }; 95 96 static const struct sata_pad_calibration tegra124_pad_calibration[] = { 97 {0x18, 0x04, 0x18, 0x0a}, 98 {0x0e, 0x04, 0x14, 0x0a}, 99 {0x0e, 0x07, 0x1a, 0x0e}, 100 {0x14, 0x0e, 0x1a, 0x0e}, 101 }; 102 103 #define SATA_CONFIGURATION 0x180 104 #define SATA_CONFIGURATION_EN_FPCI (1 << 0) 105 106 #define SATA_FPCI_BAR5 0x94 107 #define SATA_FPCI_BAR5_START_SHIFT 4 108 109 #define SATA_INTR_MASK 0x188 110 #define SATA_INTR_MASK_IP_INT_MASK (1 << 16) 111 112 #define SCFG_OFFSET 0x1000 113 114 #define T_SATA0_CFG_1 0x04 115 #define T_SATA0_CFG_1_IO_SPACE (1 << 0) 116 #define T_SATA0_CFG_1_MEMORY_SPACE (1 << 1) 117 #define T_SATA0_CFG_1_BUS_MASTER (1 << 2) 118 #define T_SATA0_CFG_1_SERR (1 << 8) 119 120 #define T_SATA0_CFG_9 0x24 121 #define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13 122 123 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300 124 #define T_SATA0_BKDOOR_CC 0x4a4 125 #define T_SATA0_CFG_SATA 0x54c 126 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN (1 << 12) 127 128 #define T_SATA0_CFG_MISC 0x550 129 #define T_SATA0_INDEX 0x680 130 131 #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690 132 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK 0xff 133 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8 134 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff 135 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0 136 137 138 #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694 139 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK 0xff 140 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12 141 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff 142 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0 143 144 #define T_SATA0_CHX_PHY_CTRL2 0x69c 145 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23 146 147 #define T_SATA0_CHX_PHY_CTRL11 0x6d0 148 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16) 149 150 #define FUSE_SATA_CALIB 0x124 151 #define FUSE_SATA_CALIB_MASK 0x3 152 153 154 #define SATA_AUX_MISC_CNTL 0x1108 155 #define SATA_AUX_PAD_PLL_CTRL_0 0x1120 156 #define SATA_AUX_PAD_PLL_CTRL_1 0x1124 157 #define SATA_AUX_PAD_PLL_CTRL_2 0x1128 158 #define SATA_AUX_PAD_PLL_CTRL_3 0x112c 159 160 #define T_AHCI_HBA_CCC_PORTS 0x0018 161 #define T_AHCI_HBA_CAP_BKDR 0x00A0 162 #define T_AHCI_HBA_CAP_BKDR_S64A (1 << 31) 163 #define T_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30) 164 #define T_AHCI_HBA_CAP_BKDR_SSNTF (1 << 29) 165 #define T_AHCI_HBA_CAP_BKDR_SMPS (1 << 28) 166 #define T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP (1 << 27) 167 #define T_AHCI_HBA_CAP_BKDR_SALP (1 << 26) 168 #define T_AHCI_HBA_CAP_BKDR_SAL (1 << 25) 169 #define T_AHCI_HBA_CAP_BKDR_SUPP_CLO (1 << 24) 170 #define T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x) (((x) & 0xF) << 20) 171 #define T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET (1 << 19) 172 #define T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY (1 << 18) 173 #define T_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17) 174 #define T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING (1 << 16) 175 #define T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK (1 << 15) 176 #define T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14) 177 #define T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13) 178 #define T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x) (((x) & 0x1F) << 8) 179 #define T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING (1 << 7) 180 #define T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP (1 << 6) 181 #define T_AHCI_HBA_CAP_BKDR_EXT_SATA (1 << 5) 182 #define T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x) (((x) & 0xF) << 0) 183 184 #define T_AHCI_PORT_BKDR 0x0170 185 186 #define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24) 187 #define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16) 188 #define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE (1 << 15) 189 #define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE (1 << 14) 190 #define T_AHCI_PORT_BKDR_PXDEVSLP_DM(x) (((x) & 0xF) << 10) 191 #define T_AHCI_PORT_BKDR_PORT_UNCONNECTED (1 << 9) 192 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH (1 << 8) 193 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 << 7) 194 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP (1 << 6) 195 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP (1 << 5) 196 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP (1 << 4) 197 #define T_AHCI_PORT_BKDR_HOTPLUG_CAP (1 << 3) 198 #define T_AHCI_PORT_BKDR_MECH_SWITCH (1 << 2) 199 #define T_AHCI_PORT_BKDR_COLD_PRSN_DET (1 << 1) 200 #define T_AHCI_PORT_BKDR_EXT_SATA_SUPP (1 << 0) 201 202 static int 203 get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node) 204 { 205 int rv; 206 207 208 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-supply", 209 &sc->supply_hvdd ); 210 if (rv != 0) { 211 device_printf(sc->dev, "Cannot get 'hvdd' regulator\n"); 212 return (ENXIO); 213 } 214 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-supply", 215 &sc->supply_vddio); 216 if (rv != 0) { 217 device_printf(sc->dev, "Cannot get 'vddio' regulator\n"); 218 return (ENXIO); 219 } 220 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-supply", 221 &sc->supply_avdd); 222 if (rv != 0) { 223 device_printf(sc->dev, "Cannot get 'avdd' regulator\n"); 224 return (ENXIO); 225 } 226 rv = regulator_get_by_ofw_property(sc->dev, 0, "target-5v-supply", 227 &sc->supply_target_5v); 228 if (rv != 0) { 229 device_printf(sc->dev, "Cannot get 'target-5v' regulator\n"); 230 return (ENXIO); 231 } 232 rv = regulator_get_by_ofw_property(sc->dev, 0, "target-12v-supply", 233 &sc->supply_target_12v); 234 if (rv != 0) { 235 device_printf(sc->dev, "Cannot get 'target-12v' regulator\n"); 236 return (ENXIO); 237 } 238 239 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata ); 240 if (rv != 0) { 241 device_printf(sc->dev, "Cannot get 'sata' reset\n"); 242 return (ENXIO); 243 } 244 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob", 245 &sc->hwreset_sata_oob); 246 if (rv != 0) { 247 device_printf(sc->dev, "Cannot get 'sata oob' reset\n"); 248 return (ENXIO); 249 } 250 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold", 251 &sc->hwreset_sata_cold); 252 if (rv != 0) { 253 device_printf(sc->dev, "Cannot get 'sata cold' reset\n"); 254 return (ENXIO); 255 } 256 257 rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy); 258 if (rv != 0) { 259 device_printf(sc->dev, "Cannot get 'sata' phy\n"); 260 return (ENXIO); 261 } 262 263 rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata); 264 if (rv != 0) { 265 device_printf(sc->dev, "Cannot get 'sata' clock\n"); 266 return (ENXIO); 267 } 268 rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob); 269 if (rv != 0) { 270 device_printf(sc->dev, "Cannot get 'sata oob' clock\n"); 271 return (ENXIO); 272 } 273 rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml); 274 if (rv != 0) { 275 device_printf(sc->dev, "Cannot get 'cml1' clock\n"); 276 return (ENXIO); 277 } 278 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 279 if (rv != 0) { 280 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 281 return (ENXIO); 282 } 283 return (0); 284 } 285 286 static int 287 enable_fdt_resources(struct tegra_ahci_sc *sc) 288 { 289 int rv; 290 291 rv = regulator_enable(sc->supply_hvdd); 292 if (rv != 0) { 293 device_printf(sc->dev, "Cannot enable 'hvdd' regulator\n"); 294 return (rv); 295 } 296 rv = regulator_enable(sc->supply_vddio); 297 if (rv != 0) { 298 device_printf(sc->dev, "Cannot enable 'vddio' regulator\n"); 299 return (rv); 300 } 301 rv = regulator_enable(sc->supply_avdd); 302 if (rv != 0) { 303 device_printf(sc->dev, "Cannot enable 'avdd' regulator\n"); 304 return (rv); 305 } 306 rv = regulator_enable(sc->supply_target_5v); 307 if (rv != 0) { 308 device_printf(sc->dev, 309 "Cannot enable 'target-5v' regulator\n"); 310 return (rv); 311 } 312 rv = regulator_enable(sc->supply_target_12v); 313 if (rv != 0) { 314 device_printf(sc->dev, 315 "Cannot enable 'sc->target-12v' regulator\n"); 316 return (rv); 317 } 318 319 /* Stop clocks */ 320 clk_stop(sc->clk_sata); 321 clk_stop(sc->clk_sata_oob); 322 tegra_powergate_power_off(TEGRA_POWERGATE_SAX); 323 324 rv = hwreset_assert(sc->hwreset_sata); 325 if (rv != 0) { 326 device_printf(sc->dev, "Cannot assert 'sata' reset\n"); 327 return (rv); 328 } 329 rv = hwreset_assert(sc->hwreset_sata_oob); 330 if (rv != 0) { 331 device_printf(sc->dev, "Cannot assert 'sata oob' reset\n"); 332 return (rv); 333 } 334 335 rv = hwreset_assert(sc->hwreset_sata_cold); 336 if (rv != 0) { 337 device_printf(sc->dev, "Cannot assert 'sata cold' reset\n"); 338 return (rv); 339 } 340 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX, 341 sc->clk_sata, sc->hwreset_sata); 342 if (rv != 0) { 343 device_printf(sc->dev, "Cannot enable 'SAX' powergate\n"); 344 return (rv); 345 } 346 347 rv = clk_enable(sc->clk_sata_oob); 348 if (rv != 0) { 349 device_printf(sc->dev, "Cannot enable 'sata oob' clock\n"); 350 return (rv); 351 } 352 rv = clk_enable(sc->clk_cml); 353 if (rv != 0) { 354 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 355 return (rv); 356 } 357 rv = clk_enable(sc->clk_pll_e); 358 if (rv != 0) { 359 device_printf(sc->dev, "Cannot enable 'pll e' clock\n"); 360 return (rv); 361 } 362 363 rv = hwreset_deassert(sc->hwreset_sata_cold); 364 if (rv != 0) { 365 device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n"); 366 return (rv); 367 } 368 rv = hwreset_deassert(sc->hwreset_sata_oob); 369 if (rv != 0) { 370 device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n"); 371 return (rv); 372 } 373 374 rv = phy_enable(sc->dev, sc->phy); 375 if (rv != 0) { 376 device_printf(sc->dev, "Cannot enable SATA phy\n"); 377 return (rv); 378 } 379 380 return (0); 381 } 382 383 static int 384 tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc) 385 { 386 uint32_t val; 387 const struct sata_pad_calibration *calib; 388 389 val = SATA_RD4(sc, SATA_CONFIGURATION); 390 val |= SATA_CONFIGURATION_EN_FPCI; 391 SATA_WR4(sc, SATA_CONFIGURATION, val); 392 393 394 /* Pad calibration. */ 395 val = tegra_fuse_read_4(FUSE_SATA_CALIB); 396 calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK); 397 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1); 398 399 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1); 400 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK << 401 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT); 402 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK << 403 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT); 404 val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 405 val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 406 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val); 407 408 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2); 409 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK << 410 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT); 411 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK << 412 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT); 413 val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT; 414 val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT; 415 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val); 416 417 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11, 418 T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ); 419 420 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2, 421 T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1); 422 423 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0); 424 425 /* Set device ID. */ 426 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 427 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 428 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 429 430 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, 0x01060100); 431 432 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 433 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 434 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 435 436 /* Enable IO & memory access, bus master mode */ 437 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1); 438 val |= T_SATA0_CFG_1_IO_SPACE; 439 val |= T_SATA0_CFG_1_MEMORY_SPACE; 440 val |= T_SATA0_CFG_1_BUS_MASTER; 441 val |= T_SATA0_CFG_1_SERR; 442 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val); 443 444 /* SATA MMIO. */ 445 SATA_WR4(sc, SATA_FPCI_BAR5, 0x10000 << SATA_FPCI_BAR5_START_SHIFT); 446 /* AHCI bar */ 447 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_9, 448 0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT); 449 450 /* Unmask interrupts. */ 451 val = SATA_RD4(sc, SATA_INTR_MASK); 452 val |= SATA_INTR_MASK_IP_INT_MASK; 453 SATA_WR4(sc, SATA_INTR_MASK, val); 454 455 return (0); 456 } 457 458 static int 459 tegra_ahci_ctlr_reset(device_t dev) 460 { 461 struct tegra_ahci_sc *sc; 462 int rv; 463 uint32_t reg; 464 465 sc = device_get_softc(dev); 466 rv = ahci_ctlr_reset(dev); 467 if (rv != 0) 468 return (0); 469 AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1); 470 471 /* Overwrite AHCI capabilites. */ 472 reg = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR); 473 reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0); 474 reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0); 475 reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA; 476 reg |= T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP; 477 reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING; 478 reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING; 479 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM; 480 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO; 481 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP; 482 AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg); 483 484 /* Overwrite AHCI portcapabilites. */ 485 reg = AHCI_RD4(sc, T_AHCI_PORT_BKDR); 486 reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET; 487 reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP; 488 reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP; 489 AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg); 490 491 return (0); 492 } 493 494 static int 495 tegra_ahci_probe(device_t dev) 496 { 497 498 if (!ofw_bus_status_okay(dev)) 499 return (ENXIO); 500 501 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 502 return (ENXIO); 503 504 device_set_desc_copy(dev, "AHCI SATA controller"); 505 return (BUS_PROBE_DEFAULT); 506 } 507 508 static int 509 tegra_ahci_attach(device_t dev) 510 { 511 struct tegra_ahci_sc *sc; 512 struct ahci_controller *ctlr; 513 phandle_t node; 514 int rv, rid; 515 516 sc = device_get_softc(dev); 517 sc->dev = dev; 518 ctlr = &sc->ctlr; 519 node = ofw_bus_get_node(dev); 520 521 ctlr->r_rid = 0; 522 ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 523 &ctlr->r_rid, RF_ACTIVE); 524 if (ctlr->r_mem == NULL) 525 return (ENXIO); 526 527 rid = 1; 528 sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 529 &rid, RF_ACTIVE); 530 if (sc->sata_mem == NULL) { 531 rv = ENXIO; 532 goto fail; 533 } 534 rv = get_fdt_resources(sc, node); 535 if (rv != 0) { 536 device_printf(sc->dev, "Failed to allocate FDT resource(s)\n"); 537 goto fail; 538 } 539 540 rv = enable_fdt_resources(sc); 541 if (rv != 0) { 542 device_printf(sc->dev, "Failed to enable FDT resource(s)\n"); 543 goto fail; 544 } 545 rv = tegra_ahci_ctrl_init(sc); 546 if (rv != 0) { 547 device_printf(sc->dev, "Failed to initialize controller)\n"); 548 goto fail; 549 } 550 551 /* Setup controller defaults. */ 552 ctlr->msi = 0; 553 ctlr->numirqs = 1; 554 ctlr->ccc = 0; 555 556 /* Reset controller. */ 557 rv = tegra_ahci_ctlr_reset(dev); 558 if (rv != 0) 559 goto fail; 560 rv = ahci_attach(dev); 561 return (rv); 562 563 fail: 564 /* XXX FDT stuff */ 565 if (sc->sata_mem != NULL) 566 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem); 567 if (ctlr->r_mem != NULL) 568 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 569 ctlr->r_mem); 570 return (rv); 571 } 572 573 static int 574 tegra_ahci_detach(device_t dev) 575 { 576 577 ahci_detach(dev); 578 return (0); 579 } 580 581 static int 582 tegra_ahci_suspend(device_t dev) 583 { 584 struct tegra_ahci_sc *sc = device_get_softc(dev); 585 586 bus_generic_suspend(dev); 587 /* Disable interupts, so the state change(s) doesn't trigger. */ 588 ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC, 589 ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 590 return (0); 591 } 592 593 static int 594 tegra_ahci_resume(device_t dev) 595 { 596 int res; 597 598 if ((res = tegra_ahci_ctlr_reset(dev)) != 0) 599 return (res); 600 ahci_ctlr_setup(dev); 601 return (bus_generic_resume(dev)); 602 } 603 604 static device_method_t tegra_ahci_methods[] = { 605 DEVMETHOD(device_probe, tegra_ahci_probe), 606 DEVMETHOD(device_attach, tegra_ahci_attach), 607 DEVMETHOD(device_detach, tegra_ahci_detach), 608 DEVMETHOD(device_suspend, tegra_ahci_suspend), 609 DEVMETHOD(device_resume, tegra_ahci_resume), 610 DEVMETHOD(bus_print_child, ahci_print_child), 611 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 612 DEVMETHOD(bus_release_resource, ahci_release_resource), 613 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 614 DEVMETHOD(bus_teardown_intr, ahci_teardown_intr), 615 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 616 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 617 618 DEVMETHOD_END 619 }; 620 621 static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods, 622 sizeof(struct tegra_ahci_sc)); 623 DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, ahci_devclass, 624 NULL, NULL); 625