1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * AHCI driver for Tegra SoCs. 32 */ 33 #include <sys/param.h> 34 #include <sys/module.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 48 #include <dev/ahci/ahci.h> 49 #include <dev/extres/clk/clk.h> 50 #include <dev/extres/hwreset/hwreset.h> 51 #include <dev/extres/phy/phy.h> 52 #include <dev/extres/regulator/regulator.h> 53 #include <dev/fdt/fdt_pinctrl.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 57 #include <arm/nvidia/tegra_efuse.h> 58 #include <arm/nvidia/tegra_pmc.h> 59 60 #define AHCI_WR4(_sc, _r, _v) bus_write_4((_sc)->ctlr.r_mem, (_r), (_v)) 61 #define AHCI_RD4(_sc, _r) bus_read_4((_sc)->ctlr.r_mem, (_r)) 62 #define SATA_WR4(_sc, _r, _v) bus_write_4((_sc)->sata_mem, (_r), (_v)) 63 #define SATA_RD4(_sc, _r) bus_read_4((_sc)->sata_mem, (_r)) 64 65 static struct ofw_compat_data compat_data[] = { 66 {"nvidia,tegra124-ahci", 1}, 67 {NULL, 0} 68 }; 69 70 struct tegra_ahci_sc { 71 struct ahci_controller ctlr; /* Must be first */ 72 device_t dev; 73 struct resource *sata_mem; 74 clk_t clk_sata; 75 clk_t clk_sata_oob; 76 clk_t clk_pll_e; 77 clk_t clk_cml; 78 hwreset_t hwreset_sata; 79 hwreset_t hwreset_sata_oob; 80 hwreset_t hwreset_sata_cold; 81 regulator_t supply_hvdd; 82 regulator_t supply_vddio; 83 regulator_t supply_avdd; 84 regulator_t supply_target_5v; 85 regulator_t supply_target_12v; 86 phy_t phy; 87 }; 88 89 struct sata_pad_calibration { 90 uint32_t gen1_tx_amp; 91 uint32_t gen1_tx_peak; 92 uint32_t gen2_tx_amp; 93 uint32_t gen2_tx_peak; 94 }; 95 96 static const struct sata_pad_calibration tegra124_pad_calibration[] = { 97 {0x18, 0x04, 0x18, 0x0a}, 98 {0x0e, 0x04, 0x14, 0x0a}, 99 {0x0e, 0x07, 0x1a, 0x0e}, 100 {0x14, 0x0e, 0x1a, 0x0e}, 101 }; 102 103 #define SATA_CONFIGURATION 0x180 104 #define SATA_CONFIGURATION_EN_FPCI (1 << 0) 105 106 #define SATA_FPCI_BAR5 0x94 107 #define SATA_FPCI_BAR5_START_SHIFT 4 108 109 #define SATA_INTR_MASK 0x188 110 #define SATA_INTR_MASK_IP_INT_MASK (1 << 16) 111 112 #define SCFG_OFFSET 0x1000 113 114 #define T_SATA0_CFG_1 0x04 115 #define T_SATA0_CFG_1_IO_SPACE (1 << 0) 116 #define T_SATA0_CFG_1_MEMORY_SPACE (1 << 1) 117 #define T_SATA0_CFG_1_BUS_MASTER (1 << 2) 118 #define T_SATA0_CFG_1_SERR (1 << 8) 119 120 #define T_SATA0_CFG_9 0x24 121 #define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13 122 123 #define T_SATA0_AHCI_HBA_CAP_BKDR 0x300 124 #define T_SATA0_BKDOOR_CC 0x4a4 125 #define T_SATA0_CFG_SATA 0x54c 126 #define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN (1 << 12) 127 128 #define T_SATA0_CFG_MISC 0x550 129 #define T_SATA0_INDEX 0x680 130 131 #define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690 132 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK 0xff 133 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8 134 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff 135 #define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0 136 137 #define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694 138 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK 0xff 139 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12 140 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff 141 #define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0 142 143 #define T_SATA0_CHX_PHY_CTRL2 0x69c 144 #define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23 145 146 #define T_SATA0_CHX_PHY_CTRL11 0x6d0 147 #define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16) 148 149 #define FUSE_SATA_CALIB 0x124 150 #define FUSE_SATA_CALIB_MASK 0x3 151 152 #define SATA_AUX_MISC_CNTL 0x1108 153 #define SATA_AUX_PAD_PLL_CTRL_0 0x1120 154 #define SATA_AUX_PAD_PLL_CTRL_1 0x1124 155 #define SATA_AUX_PAD_PLL_CTRL_2 0x1128 156 #define SATA_AUX_PAD_PLL_CTRL_3 0x112c 157 158 #define T_AHCI_HBA_CCC_PORTS 0x0018 159 #define T_AHCI_HBA_CAP_BKDR 0x00A0 160 #define T_AHCI_HBA_CAP_BKDR_S64A (1 << 31) 161 #define T_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30) 162 #define T_AHCI_HBA_CAP_BKDR_SSNTF (1 << 29) 163 #define T_AHCI_HBA_CAP_BKDR_SMPS (1 << 28) 164 #define T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP (1 << 27) 165 #define T_AHCI_HBA_CAP_BKDR_SALP (1 << 26) 166 #define T_AHCI_HBA_CAP_BKDR_SAL (1 << 25) 167 #define T_AHCI_HBA_CAP_BKDR_SUPP_CLO (1 << 24) 168 #define T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x) (((x) & 0xF) << 20) 169 #define T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET (1 << 19) 170 #define T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY (1 << 18) 171 #define T_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17) 172 #define T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING (1 << 16) 173 #define T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK (1 << 15) 174 #define T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14) 175 #define T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13) 176 #define T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x) (((x) & 0x1F) << 8) 177 #define T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING (1 << 7) 178 #define T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP (1 << 6) 179 #define T_AHCI_HBA_CAP_BKDR_EXT_SATA (1 << 5) 180 #define T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x) (((x) & 0xF) << 0) 181 182 #define T_AHCI_PORT_BKDR 0x0170 183 184 #define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24) 185 #define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16) 186 #define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE (1 << 15) 187 #define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE (1 << 14) 188 #define T_AHCI_PORT_BKDR_PXDEVSLP_DM(x) (((x) & 0xF) << 10) 189 #define T_AHCI_PORT_BKDR_PORT_UNCONNECTED (1 << 9) 190 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH (1 << 8) 191 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 << 7) 192 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP (1 << 6) 193 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP (1 << 5) 194 #define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP (1 << 4) 195 #define T_AHCI_PORT_BKDR_HOTPLUG_CAP (1 << 3) 196 #define T_AHCI_PORT_BKDR_MECH_SWITCH (1 << 2) 197 #define T_AHCI_PORT_BKDR_COLD_PRSN_DET (1 << 1) 198 #define T_AHCI_PORT_BKDR_EXT_SATA_SUPP (1 << 0) 199 200 static int 201 get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node) 202 { 203 int rv; 204 205 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-supply", 206 &sc->supply_hvdd ); 207 if (rv != 0) { 208 device_printf(sc->dev, "Cannot get 'hvdd' regulator\n"); 209 return (ENXIO); 210 } 211 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-supply", 212 &sc->supply_vddio); 213 if (rv != 0) { 214 device_printf(sc->dev, "Cannot get 'vddio' regulator\n"); 215 return (ENXIO); 216 } 217 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-supply", 218 &sc->supply_avdd); 219 if (rv != 0) { 220 device_printf(sc->dev, "Cannot get 'avdd' regulator\n"); 221 return (ENXIO); 222 } 223 rv = regulator_get_by_ofw_property(sc->dev, 0, "target-5v-supply", 224 &sc->supply_target_5v); 225 if (rv != 0) { 226 device_printf(sc->dev, "Cannot get 'target-5v' regulator\n"); 227 return (ENXIO); 228 } 229 rv = regulator_get_by_ofw_property(sc->dev, 0, "target-12v-supply", 230 &sc->supply_target_12v); 231 if (rv != 0) { 232 device_printf(sc->dev, "Cannot get 'target-12v' regulator\n"); 233 return (ENXIO); 234 } 235 236 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata ); 237 if (rv != 0) { 238 device_printf(sc->dev, "Cannot get 'sata' reset\n"); 239 return (ENXIO); 240 } 241 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob", 242 &sc->hwreset_sata_oob); 243 if (rv != 0) { 244 device_printf(sc->dev, "Cannot get 'sata oob' reset\n"); 245 return (ENXIO); 246 } 247 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold", 248 &sc->hwreset_sata_cold); 249 if (rv != 0) { 250 device_printf(sc->dev, "Cannot get 'sata cold' reset\n"); 251 return (ENXIO); 252 } 253 254 rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy); 255 if (rv != 0) { 256 device_printf(sc->dev, "Cannot get 'sata' phy\n"); 257 return (ENXIO); 258 } 259 260 rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata); 261 if (rv != 0) { 262 device_printf(sc->dev, "Cannot get 'sata' clock\n"); 263 return (ENXIO); 264 } 265 rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob); 266 if (rv != 0) { 267 device_printf(sc->dev, "Cannot get 'sata oob' clock\n"); 268 return (ENXIO); 269 } 270 rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml); 271 if (rv != 0) { 272 device_printf(sc->dev, "Cannot get 'cml1' clock\n"); 273 return (ENXIO); 274 } 275 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 276 if (rv != 0) { 277 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); 278 return (ENXIO); 279 } 280 return (0); 281 } 282 283 static int 284 enable_fdt_resources(struct tegra_ahci_sc *sc) 285 { 286 int rv; 287 288 rv = regulator_enable(sc->supply_hvdd); 289 if (rv != 0) { 290 device_printf(sc->dev, "Cannot enable 'hvdd' regulator\n"); 291 return (rv); 292 } 293 rv = regulator_enable(sc->supply_vddio); 294 if (rv != 0) { 295 device_printf(sc->dev, "Cannot enable 'vddio' regulator\n"); 296 return (rv); 297 } 298 rv = regulator_enable(sc->supply_avdd); 299 if (rv != 0) { 300 device_printf(sc->dev, "Cannot enable 'avdd' regulator\n"); 301 return (rv); 302 } 303 rv = regulator_enable(sc->supply_target_5v); 304 if (rv != 0) { 305 device_printf(sc->dev, 306 "Cannot enable 'target-5v' regulator\n"); 307 return (rv); 308 } 309 rv = regulator_enable(sc->supply_target_12v); 310 if (rv != 0) { 311 device_printf(sc->dev, 312 "Cannot enable 'sc->target-12v' regulator\n"); 313 return (rv); 314 } 315 316 /* Stop clocks */ 317 clk_stop(sc->clk_sata); 318 clk_stop(sc->clk_sata_oob); 319 tegra_powergate_power_off(TEGRA_POWERGATE_SAX); 320 321 rv = hwreset_assert(sc->hwreset_sata); 322 if (rv != 0) { 323 device_printf(sc->dev, "Cannot assert 'sata' reset\n"); 324 return (rv); 325 } 326 rv = hwreset_assert(sc->hwreset_sata_oob); 327 if (rv != 0) { 328 device_printf(sc->dev, "Cannot assert 'sata oob' reset\n"); 329 return (rv); 330 } 331 332 rv = hwreset_assert(sc->hwreset_sata_cold); 333 if (rv != 0) { 334 device_printf(sc->dev, "Cannot assert 'sata cold' reset\n"); 335 return (rv); 336 } 337 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX, 338 sc->clk_sata, sc->hwreset_sata); 339 if (rv != 0) { 340 device_printf(sc->dev, "Cannot enable 'SAX' powergate\n"); 341 return (rv); 342 } 343 344 rv = clk_enable(sc->clk_sata_oob); 345 if (rv != 0) { 346 device_printf(sc->dev, "Cannot enable 'sata oob' clock\n"); 347 return (rv); 348 } 349 rv = clk_enable(sc->clk_cml); 350 if (rv != 0) { 351 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 352 return (rv); 353 } 354 rv = clk_enable(sc->clk_pll_e); 355 if (rv != 0) { 356 device_printf(sc->dev, "Cannot enable 'pll e' clock\n"); 357 return (rv); 358 } 359 360 rv = hwreset_deassert(sc->hwreset_sata_cold); 361 if (rv != 0) { 362 device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n"); 363 return (rv); 364 } 365 rv = hwreset_deassert(sc->hwreset_sata_oob); 366 if (rv != 0) { 367 device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n"); 368 return (rv); 369 } 370 371 rv = phy_enable(sc->phy); 372 if (rv != 0) { 373 device_printf(sc->dev, "Cannot enable SATA phy\n"); 374 return (rv); 375 } 376 377 return (0); 378 } 379 380 static int 381 tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc) 382 { 383 uint32_t val; 384 const struct sata_pad_calibration *calib; 385 386 val = SATA_RD4(sc, SATA_CONFIGURATION); 387 val |= SATA_CONFIGURATION_EN_FPCI; 388 SATA_WR4(sc, SATA_CONFIGURATION, val); 389 390 /* Pad calibration. */ 391 val = tegra_fuse_read_4(FUSE_SATA_CALIB); 392 calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK); 393 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1); 394 395 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1); 396 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK << 397 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT); 398 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK << 399 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT); 400 val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 401 val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 402 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val); 403 404 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2); 405 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK << 406 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT); 407 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK << 408 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT); 409 val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT; 410 val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT; 411 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val); 412 413 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11, 414 T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ); 415 416 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2, 417 T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1); 418 419 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0); 420 421 /* Set device ID. */ 422 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 423 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 424 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 425 426 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, 0x01060100); 427 428 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 429 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 430 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 431 432 /* Enable IO & memory access, bus master mode */ 433 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1); 434 val |= T_SATA0_CFG_1_IO_SPACE; 435 val |= T_SATA0_CFG_1_MEMORY_SPACE; 436 val |= T_SATA0_CFG_1_BUS_MASTER; 437 val |= T_SATA0_CFG_1_SERR; 438 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val); 439 440 /* SATA MMIO. */ 441 SATA_WR4(sc, SATA_FPCI_BAR5, 0x10000 << SATA_FPCI_BAR5_START_SHIFT); 442 /* AHCI bar */ 443 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_9, 444 0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT); 445 446 /* Unmask interrupts. */ 447 val = SATA_RD4(sc, SATA_INTR_MASK); 448 val |= SATA_INTR_MASK_IP_INT_MASK; 449 SATA_WR4(sc, SATA_INTR_MASK, val); 450 451 return (0); 452 } 453 454 static int 455 tegra_ahci_ctlr_reset(device_t dev) 456 { 457 struct tegra_ahci_sc *sc; 458 int rv; 459 uint32_t reg; 460 461 sc = device_get_softc(dev); 462 rv = ahci_ctlr_reset(dev); 463 if (rv != 0) 464 return (0); 465 AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1); 466 467 /* Overwrite AHCI capabilites. */ 468 reg = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR); 469 reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0); 470 reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0); 471 reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA; 472 reg |= T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP; 473 reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING; 474 reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING; 475 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM; 476 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO; 477 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP; 478 AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg); 479 480 /* Overwrite AHCI portcapabilites. */ 481 reg = AHCI_RD4(sc, T_AHCI_PORT_BKDR); 482 reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET; 483 reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP; 484 reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP; 485 AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg); 486 487 return (0); 488 } 489 490 static int 491 tegra_ahci_probe(device_t dev) 492 { 493 494 if (!ofw_bus_status_okay(dev)) 495 return (ENXIO); 496 497 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 498 return (ENXIO); 499 500 device_set_desc_copy(dev, "AHCI SATA controller"); 501 return (BUS_PROBE_DEFAULT); 502 } 503 504 static int 505 tegra_ahci_attach(device_t dev) 506 { 507 struct tegra_ahci_sc *sc; 508 struct ahci_controller *ctlr; 509 phandle_t node; 510 int rv, rid; 511 512 sc = device_get_softc(dev); 513 sc->dev = dev; 514 ctlr = &sc->ctlr; 515 node = ofw_bus_get_node(dev); 516 517 ctlr->r_rid = 0; 518 ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 519 &ctlr->r_rid, RF_ACTIVE); 520 if (ctlr->r_mem == NULL) 521 return (ENXIO); 522 523 rid = 1; 524 sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 525 &rid, RF_ACTIVE); 526 if (sc->sata_mem == NULL) { 527 rv = ENXIO; 528 goto fail; 529 } 530 rv = get_fdt_resources(sc, node); 531 if (rv != 0) { 532 device_printf(sc->dev, "Failed to allocate FDT resource(s)\n"); 533 goto fail; 534 } 535 536 rv = enable_fdt_resources(sc); 537 if (rv != 0) { 538 device_printf(sc->dev, "Failed to enable FDT resource(s)\n"); 539 goto fail; 540 } 541 rv = tegra_ahci_ctrl_init(sc); 542 if (rv != 0) { 543 device_printf(sc->dev, "Failed to initialize controller)\n"); 544 goto fail; 545 } 546 547 /* Setup controller defaults. */ 548 ctlr->msi = 0; 549 ctlr->numirqs = 1; 550 ctlr->ccc = 0; 551 552 /* Reset controller. */ 553 rv = tegra_ahci_ctlr_reset(dev); 554 if (rv != 0) 555 goto fail; 556 rv = ahci_attach(dev); 557 return (rv); 558 559 fail: 560 /* XXX FDT stuff */ 561 if (sc->sata_mem != NULL) 562 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem); 563 if (ctlr->r_mem != NULL) 564 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 565 ctlr->r_mem); 566 return (rv); 567 } 568 569 static int 570 tegra_ahci_detach(device_t dev) 571 { 572 573 ahci_detach(dev); 574 return (0); 575 } 576 577 static int 578 tegra_ahci_suspend(device_t dev) 579 { 580 struct tegra_ahci_sc *sc = device_get_softc(dev); 581 582 bus_generic_suspend(dev); 583 /* Disable interupts, so the state change(s) doesn't trigger. */ 584 ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC, 585 ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 586 return (0); 587 } 588 589 static int 590 tegra_ahci_resume(device_t dev) 591 { 592 int res; 593 594 if ((res = tegra_ahci_ctlr_reset(dev)) != 0) 595 return (res); 596 ahci_ctlr_setup(dev); 597 return (bus_generic_resume(dev)); 598 } 599 600 static device_method_t tegra_ahci_methods[] = { 601 DEVMETHOD(device_probe, tegra_ahci_probe), 602 DEVMETHOD(device_attach, tegra_ahci_attach), 603 DEVMETHOD(device_detach, tegra_ahci_detach), 604 DEVMETHOD(device_suspend, tegra_ahci_suspend), 605 DEVMETHOD(device_resume, tegra_ahci_resume), 606 DEVMETHOD(bus_print_child, ahci_print_child), 607 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 608 DEVMETHOD(bus_release_resource, ahci_release_resource), 609 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 610 DEVMETHOD(bus_teardown_intr, ahci_teardown_intr), 611 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 612 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 613 614 DEVMETHOD_END 615 }; 616 617 static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods, 618 sizeof(struct tegra_ahci_sc)); 619 DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, ahci_devclass, 620 NULL, NULL); 621