1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * SoC misc configuration and indentification driver. 32 */ 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/clock.h> 37 #include <sys/kernel.h> 38 #include <sys/limits.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/module.h> 42 #include <sys/resource.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 #include <sys/rman.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <arm/nvidia/tegra_efuse.h> 52 53 #define PMC_STRAPPING_OPT_A 0 /* 0x464 */ 54 55 #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4 56 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \ 57 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) 58 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \ 59 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) 60 61 #define ABP_RD4(_sc, _r) bus_read_4((_sc)->abp_misc_res, (_r)) 62 #define STR_RD4(_sc, _r) bus_read_4((_sc)->strap_opt_res, (_r)) 63 64 static struct ofw_compat_data compat_data[] = { 65 {"nvidia,tegra124-apbmisc", 1}, 66 {NULL, 0} 67 }; 68 69 struct tegra_abpmisc_softc { 70 device_t dev; 71 72 struct resource *abp_misc_res; 73 struct resource *strap_opt_res; 74 }; 75 76 static struct tegra_abpmisc_softc *dev_sc; 77 78 static void 79 tegra_abpmisc_read_revision(struct tegra_abpmisc_softc *sc) 80 { 81 uint32_t id, chip_id, minor_rev; 82 int rev; 83 84 id = ABP_RD4(sc, 4); 85 chip_id = (id >> 8) & 0xff; 86 minor_rev = (id >> 16) & 0xf; 87 88 switch (minor_rev) { 89 case 1: 90 rev = TEGRA_REVISION_A01; 91 break; 92 case 2: 93 rev = TEGRA_REVISION_A02; 94 break; 95 case 3: 96 rev = TEGRA_REVISION_A03; 97 break; 98 case 4: 99 rev = TEGRA_REVISION_A04; 100 break; 101 default: 102 rev = TEGRA_REVISION_UNKNOWN; 103 } 104 105 tegra_sku_info.chip_id = chip_id; 106 tegra_sku_info.revision = rev; 107 } 108 109 static int 110 tegra_abpmisc_probe(device_t dev) 111 { 112 if (!ofw_bus_status_okay(dev)) 113 return (ENXIO); 114 115 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 116 return (ENXIO); 117 118 return (BUS_PROBE_DEFAULT); 119 } 120 121 static int 122 tegra_abpmisc_attach(device_t dev) 123 { 124 int rid; 125 struct tegra_abpmisc_softc *sc; 126 127 sc = device_get_softc(dev); 128 sc->dev = dev; 129 130 rid = 0; 131 sc->abp_misc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 132 RF_ACTIVE | RF_SHAREABLE); 133 if (sc->abp_misc_res == NULL) { 134 device_printf(dev, "Cannot map ABP misc registers.\n"); 135 goto fail; 136 } 137 138 rid = 1; 139 sc->strap_opt_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 140 RF_ACTIVE); 141 if (sc->strap_opt_res == NULL) { 142 device_printf(dev, "Cannot map strapping options registers.\n"); 143 goto fail; 144 } 145 146 tegra_abpmisc_read_revision(sc); 147 148 /* XXX - Hack - address collision with pinmux. */ 149 if (sc->abp_misc_res != NULL) { 150 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res); 151 sc->abp_misc_res = NULL; 152 } 153 154 dev_sc = sc; 155 return (bus_generic_attach(dev)); 156 157 fail: 158 if (sc->abp_misc_res != NULL) 159 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res); 160 if (sc->strap_opt_res != NULL) 161 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->strap_opt_res); 162 163 return (ENXIO); 164 } 165 166 static int 167 tegra_abpmisc_detach(device_t dev) 168 { 169 struct tegra_abpmisc_softc *sc; 170 171 sc = device_get_softc(dev); 172 if (sc->abp_misc_res != NULL) 173 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res); 174 if (sc->strap_opt_res != NULL) 175 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->strap_opt_res); 176 return (bus_generic_detach(dev)); 177 } 178 179 static device_method_t tegra_abpmisc_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, tegra_abpmisc_probe), 182 DEVMETHOD(device_attach, tegra_abpmisc_attach), 183 DEVMETHOD(device_detach, tegra_abpmisc_detach), 184 185 DEVMETHOD_END 186 }; 187 188 static devclass_t tegra_abpmisc_devclass; 189 static DEFINE_CLASS_0(abpmisc, tegra_abpmisc_driver, tegra_abpmisc_methods, 190 sizeof(struct tegra_abpmisc_softc)); 191 EARLY_DRIVER_MODULE(tegra_abpmisc, simplebus, tegra_abpmisc_driver, 192 tegra_abpmisc_devclass, NULL, NULL, BUS_PASS_TIMER); 193