xref: /freebsd/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c (revision f6a3b357e9be4c6423c85eff9a847163a0d307c8)
1 /*-
2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
36 #include <sys/rman.h>
37 
38 #include <machine/bus.h>
39 #include <machine/fdt.h>
40 
41 #include <dev/extres/hwreset/hwreset.h>
42 #include <dev/extres/phy/phy.h>
43 #include <dev/extres/regulator/regulator.h>
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/fdt/fdt_pinctrl.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 
50 #include <arm/nvidia/tegra_efuse.h>
51 
52 #include <gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
53 
54 #include "phydev_if.h"
55 
56 /* FUSE calibration data. */
57 #define	FUSE_XUSB_CALIB				0x0F0
58 #define	  FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x)		(((x) >> 15) & 0x3F);
59 #define	  FUSE_XUSB_CALIB_HS_IREF_CAP(x)		(((x) >> 13) & 0x03);
60 #define	  FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x)		(((x) >> 11) & 0x03);
61 #define	  FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x)		(((x) >>  7) & 0x0F);
62 #define	  FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x)		(((x) >>  0) & 0x3F);
63 
64 
65 /* Registers. */
66 #define	XUSB_PADCTL_USB2_PAD_MUX		0x004
67 
68 #define	XUSB_PADCTL_USB2_PORT_CAP		0x008
69 #define	 USB2_PORT_CAP_ULPI_PORT_INTERNAL		(1 << 25)
70 #define	 USB2_PORT_CAP_ULPI_PORT_CAP			(1 << 24)
71 #define	 USB2_PORT_CAP_PORT_REVERSE_ID(p)		(1 << (3 + (p) * 4))
72 #define	 USB2_PORT_CAP_PORT_INTERNAL(p)			(1 << (2 + (p) * 4))
73 #define	 USB2_PORT_CAP_PORT_CAP(p, x)			(((x) & 3) << ((p) * 4))
74 #define	  USB2_PORT_CAP_PORT_CAP_OTG			0x3
75 #define	  USB2_PORT_CAP_PORT_CAP_DEVICE			0x2
76 #define	  USB2_PORT_CAP_PORT_CAP_HOST			0x1
77 #define	  USB2_PORT_CAP_PORT_CAP_DISABLED		0x0
78 
79 #define	XUSB_PADCTL_SS_PORT_MAP			0x014
80 #define	 SS_PORT_MAP_PORT_INTERNAL(p)			(1 << (3 + (p) * 4))
81 #define	 SS_PORT_MAP_PORT_MAP(p, x)			(((x) & 7) << ((p) * 4))
82 
83 #define	XUSB_PADCTL_ELPG_PROGRAM		0x01C
84 #define	 ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN		(1 << 26)
85 #define	 ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY	(1 << 25)
86 #define	 ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN		(1 << 24)
87 #define	 ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) 		(1 << (18 + (x) * 4))
88 #define	 ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) 	(1 << (17 + (x) * 4))
89 #define	 ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x)		(1 << (16 + (x) * 4))
90 
91 #define	XUSB_PADCTL_IOPHY_PLL_P0_CTL1		0x040
92 #define	 IOPHY_PLL_P0_CTL1_PLL0_LOCKDET			(1 << 19)
93 #define	 IOPHY_PLL_P0_CTL1_REFCLK_SEL(x)		(((x) & 0xF) << 12)
94 #define	 IOPHY_PLL_P0_CTL1_PLL_RST			(1 << 1)
95 
96 #define	XUSB_PADCTL_IOPHY_PLL_P0_CTL2		0x044
97 #define	 IOPHY_PLL_P0_CTL2_REFCLKBUF_EN			(1 << 6)
98 #define	 IOPHY_PLL_P0_CTL2_TXCLKREF_EN			(1 << 5)
99 #define	 IOPHY_PLL_P0_CTL2_TXCLKREF_SEL			(1 << 4)
100 
101 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) 	(0x058 + (x) * 4)
102 #define	 IOPHY_USB3_PAD_CTL2_CDR_CNTL(x)		(((x) & 0x00FF) <<  4)
103 #define	 IOPHY_USB3_PAD_CTL2_RX_EQ(x)			(((x) & 0xFFFF) <<  8)
104 #define	 IOPHY_USB3_PAD_CTL2_RX_WANDER(x)		(((x) & 0x000F) <<  4)
105 #define	 IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x)		(((x) & 0x0003) <<  2)
106 #define	 IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x)		(((x) & 0x0003) <<  0)
107 
108 
109 #define	XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x)	(0x068 + (x) * 4)
110 
111 #define	XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) 	(0x0A0 + (x) * 4)
112 #define	 USB2_OTG_PAD_CTL0_LSBIAS_SEL			(1 << 23)
113 #define	 USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD		(1 << 22)
114 #define	 USB2_OTG_PAD_CTL0_PD_ZI			(1 << 21)
115 #define	 USB2_OTG_PAD_CTL0_PD2				(1 << 20)
116 #define	 USB2_OTG_PAD_CTL0_PD				(1 << 19)
117 #define	 USB2_OTG_PAD_CTL0_TERM_EN			(1 << 18)
118 #define	 USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x)		(((x) & 0x03) << 16)
119 #define	 USB2_OTG_PAD_CTL0_LS_RSLEW(x)			(((x) & 0x03) << 14)
120 #define	 USB2_OTG_PAD_CTL0_FS_SLEW(x)			(((x) & 0x03) << 12)
121 #define	 USB2_OTG_PAD_CTL0_HS_SLEW(x)			(((x) & 0x3F) <<  6)
122 #define	 USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x)		(((x) & 0x3F) <<  0)
123 
124 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) 	(0x0AC + (x) * 4)
125 #define	 USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x)		(((x) & 0x3) << 11)
126 #define	 USB2_OTG_PAD_CTL1_HS_IREF_CAP(x)		(((x) & 0x3) <<  9)
127 #define	 USB2_OTG_PAD_CTL1_SPARE(x)			(((x) & 0x3) <<  7)
128 #define	 USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x)		(((x) & 0xF) <<  3)
129 #define	 USB2_OTG_PAD_CTL1_PD_DR			(1 <<  2)
130 #define	 USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP	(1 <<  1)
131 #define	 USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP	(1 <<  0)
132 
133 #define	XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x0B8
134 #define	 USB2_BIAS_PAD_CTL0_ADJRPU(x)			(((x) & 0x7) << 14)
135 #define	 USB2_BIAS_PAD_CTL0_PD_TRK			(1 << 13)
136 #define	 USB2_BIAS_PAD_CTL0_PD				(1 << 12)
137 #define	 USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x)		(((x) & 0x3) <<  9)
138 #define	 USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x)		(((x) & 0x3) <<  7)
139 #define	 USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x)		(((x) & 0x3) <<  5)
140 #define	 USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x)		(((x) & 0x7) <<  2)
141 #define	 USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x)		(((x) & 0x3) <<  0)
142 
143 #define	XUSB_PADCTL_HSIC_PAD0_CTL0		0x0C8
144 #define	 HSIC_PAD0_CTL0_HSIC_OPT(x)			(((x) & 0xF) << 16)
145 #define	 HSIC_PAD0_CTL0_TX_SLEWN(x)			(((x) & 0xF) << 12)
146 #define	 HSIC_PAD0_CTL0_TX_SLEWP(x)			(((x) & 0xF) <<  8)
147 #define	 HSIC_PAD0_CTL0_TX_RTUNEN(x)			(((x) & 0xF) <<  4)
148 #define	 HSIC_PAD0_CTL0_TX_RTUNEP(x)			(((x) & 0xF) <<  0)
149 
150 #define	XUSB_PADCTL_USB3_PAD_MUX		0x134
151 #define	 USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) 		(1 << (1 + (x)))
152 #define	 USB3_PAD_MUX_SATA_IDDQ_DISABLE 		(1 << 6)
153 
154 
155 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL1		0x138
156 #define	 IOPHY_PLL_S0_CTL1_PLL1_LOCKDET			(1 << 27)
157 #define	 IOPHY_PLL_S0_CTL1_PLL1_MODE			(1 << 24)
158 #define	 IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD			(1 << 3)
159 #define	 IOPHY_PLL_S0_CTL1_PLL_RST_L			(1 << 1)
160 #define	 IOPHY_PLL_S0_CTL1_PLL_IDDQ			(1 << 0)
161 
162 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL2		0x13C
163 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL3		0x140
164 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL4		0x144
165 
166 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1	0x148
167 #define	 IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD		(1 << 1)
168 #define	 IOPHY_MISC_PAD_S0_CTL1_IDDQ			(1 << 0)
169 
170 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2	0x14C
171 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3	0x150
172 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4	0x154
173 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5	0x158
174 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6	0x15C
175 
176 
177 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, (_r), (_v))
178 #define	RD4(_sc, _r)		bus_read_4((_sc)->mem_res, (_r))
179 
180 
181 struct padctl_softc {
182 	device_t	dev;
183 	struct resource	*mem_res;
184 	hwreset_t	rst;
185 	int		phy_ena_cnt;
186 
187 	/* Fuses calibration data */
188 	uint32_t	hs_curr_level_0;
189 	uint32_t	hs_curr_level_123;
190 	uint32_t	hs_iref_cap;
191 	uint32_t	hs_term_range_adj;
192 	uint32_t	hs_squelch_level;
193 
194 	uint32_t	hs_curr_level_offset;
195 };
196 
197 static struct ofw_compat_data compat_data[] = {
198 	{"nvidia,tegra124-xusb-padctl",	1},
199 	{NULL,				0},
200 };
201 
202 /* Ports. */
203 enum padctl_port_type {
204 	PADCTL_PORT_USB2,
205 	PADCTL_PORT_ULPI,
206 	PADCTL_PORT_HSIC,
207 	PADCTL_PORT_USB3,
208 };
209 
210 struct padctl_lane;
211 struct padctl_port {
212 	enum padctl_port_type	type;
213 	const char		*name;
214 	const char		*base_name;
215 	int			idx;
216 	int			(*init)(struct padctl_softc *sc,
217 				    struct padctl_port *port);
218 
219 	/* Runtime data. */
220 	bool			enabled;
221 	regulator_t		supply_vbus;	/* USB2, USB3 */
222 	bool			internal;	/* ULPI, USB2, USB3 */
223 	uint32_t		companion;	/* USB3 */
224 	struct padctl_lane	*lane;
225 };
226 
227 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
228 
229 #define	PORT(t, n, p, i) {						\
230 	.type = t,							\
231 	.name = n "-" #p,						\
232 	.base_name = n,							\
233 	.idx = p,							\
234 	.init = i,							\
235 }
236 static struct padctl_port ports_tbl[] = {
237 	PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
238 	PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
239 	PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
240 	PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL),
241 	PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
242 	PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
243 	PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
244 	PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
245 };
246 
247 /* Pads - a group of lannes. */
248 enum padctl_pad_type {
249 	PADCTL_PAD_USB2,
250 	PADCTL_PAD_ULPI,
251 	PADCTL_PAD_HSIC,
252 	PADCTL_PAD_PCIE,
253 	PADCTL_PAD_SATA,
254 };
255 
256 struct padctl_lane;
257 struct padctl_pad {
258 	const char		*name;
259 	enum padctl_pad_type	type;
260 	int			(*powerup)(struct padctl_softc *sc,
261 				    struct padctl_lane *lane);
262 	int			(*powerdown)(struct padctl_softc *sc,
263 				    struct padctl_lane *lane);
264 	/* Runtime data. */
265 	bool			enabled;
266 	struct padctl_lane	*lanes[8]; 	/* Safe maximum value. */
267 	int			nlanes;
268 };
269 
270 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
271 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
272 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
273 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
274 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
275 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
276 
277 #define	PAD(n, t, u, d) {						\
278 	.name = n,							\
279 	.type = t,							\
280 	.powerup = u,							\
281 	.powerdown = d,							\
282 }
283 static struct padctl_pad pads_tbl[] = {
284 	PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown),
285 	PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL),
286 	PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL),
287 	PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown),
288 	PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown),
289 };
290 
291 /* Lanes. */
292 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"};
293 static char *usb_mux[] = {"snps", "xusb"};
294 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"};
295 
296 struct padctl_lane {
297 	const char		*name;
298 	int			idx;
299 	bus_size_t		reg;
300 	uint32_t		shift;
301 	uint32_t		mask;
302 	char			**mux;
303 	int			nmux;
304 	/* Runtime data. */
305 	bool			enabled;
306 	struct padctl_pad	*pad;
307 	struct padctl_port	*port;
308 	int			mux_idx;
309 
310 };
311 
312 #define	LANE(n, p, r, s, m, mx) {					\
313 	.name = n "-" #p,						\
314 	.idx = p,							\
315 	.reg = r,							\
316 	.shift = s,							\
317 	.mask = m,							\
318 	.mux = mx,							\
319 	.nmux = nitems(mx),						\
320 }
321 static struct padctl_lane lanes_tbl[] = {
322 	LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX,  0, 0x3, otg_mux),
323 	LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX,  2, 0x3, otg_mux),
324 	LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX,  4, 0x3, otg_mux),
325 	LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux),
326 	LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux),
327 	LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux),
328 	LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
329 	LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
330 	LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
331 	LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
332 	LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
333 	LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux),
334 };
335 
336 /* Define all possible mappings for USB3 port lanes */
337 struct padctl_lane_map {
338 	int			port_idx;
339 	enum padctl_pad_type	pad_type;
340 	int			lane_idx;
341 };
342 
343 #define	LANE_MAP(pi, pt, li) {						\
344 	.port_idx = pi,							\
345 	.pad_type = pt,							\
346 	.lane_idx = li,							\
347 }
348 static struct padctl_lane_map lane_map_tbl[] = {
349 	LANE_MAP(0, PADCTL_PAD_PCIE, 0), 	/* port USB3-0 -> lane PCIE-0 */
350 	LANE_MAP(1, PADCTL_PAD_PCIE, 1), 	/* port USB3-1 -> lane PCIE-1 */
351 						/* -- or -- */
352 	LANE_MAP(1, PADCTL_PAD_SATA, 0), 	/* port USB3-1 -> lane SATA-0 */
353 };
354 
355  /* Phy class and methods. */
356 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);
357 static phynode_method_t xusbpadctl_phynode_methods[] = {
358 	PHYNODEMETHOD(phynode_enable,	xusbpadctl_phy_enable),
359 	PHYNODEMETHOD_END
360 
361 };
362 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class,
363     xusbpadctl_phynode_methods, 0, phynode_class);
364 
365 static struct padctl_port *search_lane_port(struct padctl_softc *sc,
366     struct padctl_lane *lane);
367 /* -------------------------------------------------------------------------
368  *
369  *   PHY functions
370  */
371 static int
372 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
373 {
374 	uint32_t reg;
375 
376 	reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
377 	if (port->internal)
378 		reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
379 	else
380 		reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
381 	reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
382 	reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
383 	WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
384 
385 	reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
386 	reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0);
387 	reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0);
388 	reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0);
389 	reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24);
390 	reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070);
391 	reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF);
392 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
393 
394 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
395 	    0x002008EE);
396 
397 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
398 	reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx);
399 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
400 	DELAY(100);
401 
402 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
403 	reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
404 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
405 	DELAY(100);
406 
407 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
408 	reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx);
409 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
410 	DELAY(100);
411 
412 	return (0);
413 }
414 
415 static int
416 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
417 {
418 	uint32_t reg;
419 	int i;
420 
421 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
422 	reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0);
423 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
424 	DELAY(100);
425 
426 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
427 	reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN;
428 	reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN;
429 	reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
430 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
431 	DELAY(100);
432 
433 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
434 	reg |= IOPHY_PLL_P0_CTL1_PLL_RST;
435 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
436 	DELAY(100);
437 
438 	for (i = 100; i > 0; i--) {
439 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
440 		if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET)
441 			break;
442 		DELAY(10);
443 	}
444 	if (i <= 0) {
445 		device_printf(sc->dev, "Failed to power up PCIe phy\n");
446 		return (ETIMEDOUT);
447 	}
448 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
449 	reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
450 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
451 
452 	return (0);
453 }
454 
455 static int
456 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
457 {
458 	uint32_t reg;
459 
460 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
461 	reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
462 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
463 
464 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
465 	reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST;
466 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
467 	DELAY(100);
468 
469 	return (0);
470 
471 }
472 
473 static int
474 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
475 {
476 	uint32_t reg;
477 	int i;
478 
479 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
480 	reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
481 	reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ;
482 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
483 
484 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
485 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
486 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ;
487 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
488 
489 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
490 	reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE;
491 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
492 
493 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
494 	reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
495 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
496 
497 	for (i = 100; i >= 0; i--) {
498 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
499 		if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
500 			break;
501 		DELAY(100);
502 	}
503 	if (i <= 0) {
504 		device_printf(sc->dev, "Failed to power up SATA phy\n");
505 		return (ETIMEDOUT);
506 	}
507 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
508 	reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
509 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
510 
511 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
512 	reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE;
513 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
514 
515 	return (0);
516 }
517 
518 static int
519 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
520 {
521 	uint32_t reg;
522 
523 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
524 	reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE;
525 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
526 
527 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
528 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L;
529 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
530 	DELAY(100);
531 
532 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
533 	reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE;
534 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
535 	DELAY(100);
536 
537 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
538 	reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
539 	reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ;
540 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
541 	DELAY(100);
542 
543 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
544 	reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
545 	reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ;
546 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
547 	DELAY(100);
548 
549 	return (0);
550 }
551 
552 static int
553 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
554 {
555 	uint32_t reg;
556 	struct padctl_port *port;
557 	int rv;
558 
559 	port = search_lane_port(sc, lane);
560 	if (port == NULL) {
561 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
562 		    lane->name);
563 	}
564 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
565 	reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
566 	reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
567 	reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level);
568 	reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5);
569 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
570 
571 	reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
572 	reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
573 	reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
574 	WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
575 
576 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
577 	reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
578 	reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
579 	reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0);
580 	reg &= ~USB2_OTG_PAD_CTL0_PD;
581 	reg &= ~USB2_OTG_PAD_CTL0_PD2;
582 	reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
583 
584 	reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
585 	if (lane->idx == 0) {
586 		reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0);
587 		reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3);
588 	} else {
589 		reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123);
590 		reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0);
591 	}
592 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
593 
594 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
595 	reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
596 	reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0);
597 	reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
598 	reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP;
599 	reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP;
600 
601 	reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
602 	reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap);
603 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
604 
605 	if (port != NULL && port->supply_vbus != NULL) {
606 		rv = regulator_enable(port->supply_vbus);
607 		if (rv != 0) {
608 			device_printf(sc->dev,
609 			    "Cannot enable vbus regulator\n");
610 			return (rv);
611 		}
612 	}
613 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
614 	reg &= ~USB2_BIAS_PAD_CTL0_PD;
615 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
616 
617 	return (0);
618 }
619 
620 static int
621 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
622 {
623 	uint32_t reg;
624 	struct padctl_port *port;
625 	int rv;
626 
627 	port = search_lane_port(sc, lane);
628 	if (port == NULL) {
629 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
630 		    lane->name);
631 	}
632 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
633 	reg |= USB2_BIAS_PAD_CTL0_PD;
634 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
635 
636 	if (port != NULL && port->supply_vbus != NULL) {
637 		rv = regulator_enable(port->supply_vbus);
638 		if (rv != 0) {
639 			device_printf(sc->dev,
640 			    "Cannot disable vbus regulator\n");
641 			return (rv);
642 		}
643 	}
644 	return (0);
645 }
646 
647 
648 static int
649 phy_powerup(struct padctl_softc *sc)
650 {
651 	uint32_t reg;
652 
653 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
654 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
655 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
656 	DELAY(100);
657 
658 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
659 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
660 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
661 	DELAY(100);
662 
663 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
664 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
665 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
666 	DELAY(100);
667 
668 	return (0);
669 }
670 
671 static int
672 phy_powerdown(struct padctl_softc *sc)
673 {
674 	uint32_t reg;
675 
676 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
677 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
678 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
679 	DELAY(100);
680 
681 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
682 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
683 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
684 	DELAY(100);
685 
686 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
687 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
688 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
689 	DELAY(100);
690 
691 	return (0);
692 }
693 
694 static int
695 xusbpadctl_phy_enable(struct phynode *phy, bool enable)
696 {
697 	device_t dev;
698 	intptr_t id;
699 	struct padctl_softc *sc;
700 	struct padctl_lane *lane;
701 	struct padctl_pad *pad;
702 	int rv;
703 
704 	dev = phynode_get_device(phy);
705 	id = phynode_get_id(phy);
706 	sc = device_get_softc(dev);
707 
708 	if (id < 0 || id >= nitems(lanes_tbl)) {
709 		device_printf(dev, "Unknown phy: %d\n", id);
710 		return (ENXIO);
711 	}
712 	lane = lanes_tbl + id;
713 	if (!lane->enabled) {
714 		device_printf(dev, "Lane is not enabled/configured: %s\n",
715 		    lane->name);
716 		return (ENXIO);
717 	}
718 	pad = lane->pad;
719 	if (enable) {
720 		if (sc->phy_ena_cnt == 0) {
721 			rv = phy_powerup(sc);
722 			if (rv != 0)
723 				return (rv);
724 		}
725 		sc->phy_ena_cnt++;
726 	}
727 
728 	if (enable)
729 		rv = pad->powerup(sc, lane);
730 	else
731 		rv = pad->powerdown(sc, lane);
732 	if (rv != 0)
733 		return (rv);
734 
735 	if (!enable) {
736 		 if (sc->phy_ena_cnt == 1) {
737 			rv = phy_powerdown(sc);
738 			if (rv != 0)
739 				return (rv);
740 		}
741 		sc->phy_ena_cnt--;
742 	}
743 
744 	return (0);
745 }
746 
747 /* -------------------------------------------------------------------------
748  *
749  *   FDT processing
750  */
751 static struct padctl_port *
752 search_port(struct padctl_softc *sc, char *port_name)
753 {
754 	int i;
755 
756 	for (i = 0; i < nitems(ports_tbl); i++) {
757 		if (strcmp(port_name, ports_tbl[i].name) == 0)
758 			return (&ports_tbl[i]);
759 	}
760 	return (NULL);
761 }
762 
763 static struct padctl_port *
764 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
765 {
766 	int i;
767 
768 	for (i = 0; i < nitems(ports_tbl); i++) {
769 		if (!ports_tbl[i].enabled)
770 			continue;
771 		if (ports_tbl[i].lane == lane)
772 			return (ports_tbl + i);
773 	}
774 	return (NULL);
775 }
776 
777 static struct padctl_lane *
778 search_lane(struct padctl_softc *sc, char *lane_name)
779 {
780 	int i;
781 
782 	for (i = 0; i < nitems(lanes_tbl); i++) {
783 		if (strcmp(lane_name, lanes_tbl[i].name) == 0)
784 			return 	(lanes_tbl + i);
785 	}
786 	return (NULL);
787 }
788 
789 static struct padctl_lane *
790 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
791 {
792 	int i;
793 
794 	for (i = 0; i < nitems(lanes_tbl); i++) {
795 		if (!lanes_tbl[i].enabled)
796 			continue;
797 		if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
798 			return 	(lanes_tbl + i);
799 	}
800 	return (NULL);
801 }
802 
803 static struct padctl_lane *
804 search_usb3_pad_lane(struct padctl_softc *sc, int idx)
805 {
806 	int i;
807 	struct padctl_lane *lane, *tmp;
808 
809 	lane = NULL;
810 	for (i = 0; i < nitems(lane_map_tbl); i++) {
811 		if (idx != lane_map_tbl[i].port_idx)
812 			continue;
813 		tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
814 		    lane_map_tbl[i].lane_idx);
815 		if (tmp == NULL)
816 			continue;
817 		if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
818 			continue;
819 		if (lane != NULL) {
820 			device_printf(sc->dev, "Duplicated mappings found for"
821 			 " lanes: %s and %s\n", lane->name, tmp->name);
822 			return (NULL);
823 		}
824 		lane = tmp;
825 	}
826 	return (lane);
827 }
828 
829 static struct padctl_pad *
830 search_pad(struct padctl_softc *sc, char *pad_name)
831 {
832 	int i;
833 
834 	for (i = 0; i < nitems(pads_tbl); i++) {
835 		if (strcmp(pad_name, pads_tbl[i].name) == 0)
836 			return 	(pads_tbl + i);
837 	}
838 	return (NULL);
839 }
840 
841 static int
842 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
843 {
844 	int i;
845 
846 	for (i = 0; i < lane->nmux; i++) {
847 		if (strcmp(fnc_name, lane->mux[i]) == 0)
848 			return 	(i);
849 	}
850 	return (-1);
851 }
852 
853 static int
854 config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
855 {
856 	uint32_t reg;
857 
858 	reg = RD4(sc, lane->reg);
859 	reg &= ~(lane->mask << lane->shift);
860 	reg |=  (lane->mux_idx & lane->mask) << lane->shift;
861 	WR4(sc, lane->reg, reg);
862 	return (0);
863 }
864 
865 static int
866 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
867 {
868 	struct padctl_lane *lane;
869 	struct phynode *phynode;
870 	struct phynode_init_def phy_init;
871 	char *name;
872 	char *function;
873 	int rv;
874 
875 	name = NULL;
876 	function = NULL;
877 	rv = OF_getprop_alloc(node, "name", (void **)&name);
878 	if (rv <= 0) {
879 		device_printf(sc->dev, "Cannot read lane name.\n");
880 		return (ENXIO);
881 	}
882 
883 	lane = search_lane(sc, name);
884 	if (lane == NULL) {
885 		device_printf(sc->dev, "Unknown lane: %s\n", name);
886 		rv = ENXIO;
887 		goto end;
888 	}
889 
890 	/* Read function (mux) settings. */
891 	rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function);
892 	if (rv <= 0) {
893 		device_printf(sc->dev, "Cannot read lane function.\n");
894 		rv = ENXIO;
895 		goto end;
896 	}
897 
898 	lane->mux_idx = search_mux(sc, lane, function);
899 	if (lane->mux_idx == ~0) {
900 		device_printf(sc->dev, "Unknown function %s for lane %s\n",
901 		    function, name);
902 		rv = ENXIO;
903 		goto end;
904 	}
905 
906 	rv = config_lane(sc, lane);
907 	if (rv != 0) {
908 		device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
909 		    name, rv);
910 		rv = ENXIO;
911 		goto end;
912 	}
913 	lane->pad = pad;
914 	lane->enabled = true;
915 	pad->lanes[pad->nlanes++] = lane;
916 
917 	/* Create and register phy. */
918 	bzero(&phy_init, sizeof(phy_init));
919 	phy_init.id = lane - lanes_tbl;
920 	phy_init.ofw_node = node;
921 	phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init);
922 	if (phynode == NULL) {
923 		device_printf(sc->dev, "Cannot create phy\n");
924 		rv = ENXIO;
925 		goto end;
926 	}
927 	if (phynode_register(phynode) == NULL) {
928 		device_printf(sc->dev, "Cannot create phy\n");
929 		return (ENXIO);
930 	}
931 
932 	rv = 0;
933 
934 end:
935 	if (name != NULL)
936 		OF_prop_free(name);
937 	if (function != NULL)
938 		OF_prop_free(function);
939 	return (rv);
940 }
941 
942 static int
943 process_pad(struct padctl_softc *sc, phandle_t node)
944 {
945 	struct padctl_pad *pad;
946 	char *name;
947 	int rv;
948 
949 	name = NULL;
950 	rv = OF_getprop_alloc(node, "name", (void **)&name);
951 	if (rv <= 0) {
952 		device_printf(sc->dev, "Cannot read pad name.\n");
953 		return (ENXIO);
954 	}
955 	pad = search_pad(sc, name);
956 	if (pad == NULL) {
957 		device_printf(sc->dev, "Unknown pad: %s\n", name);
958 		rv = ENXIO;
959 		goto end;
960 	}
961 
962 	/* Read and process associated lanes. */
963 	node = ofw_bus_find_child(node, "lanes");
964 	if (node <= 0) {
965 		device_printf(sc->dev, "Cannot find regulators subnode\n");
966 		rv = ENXIO;
967 		goto end;
968 	}
969 
970 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
971 		if (!ofw_bus_node_status_okay(node))
972 			continue;
973 
974 		rv = process_lane(sc, node, pad);
975 		if (rv != 0)
976 			goto end;
977 	}
978 	pad->enabled = true;
979 	rv = 0;
980 end:
981 	if (name != NULL)
982 		OF_prop_free(name);
983 	return (rv);
984 }
985 
986 static int
987 process_port(struct padctl_softc *sc, phandle_t node)
988 {
989 
990 	struct padctl_port *port;
991 	char *name;
992 	int rv;
993 
994 	name = NULL;
995 	rv = OF_getprop_alloc(node, "name", (void **)&name);
996 	if (rv <= 0) {
997 		device_printf(sc->dev, "Cannot read port name.\n");
998 		return (ENXIO);
999 	}
1000 
1001 	port = search_port(sc, name);
1002 	if (port == NULL) {
1003 		device_printf(sc->dev, "Unknown port: %s\n", name);
1004 		rv = ENXIO;
1005 		goto end;
1006 	}
1007 
1008 	if (port->type == PADCTL_PORT_USB3) {
1009 		rv = OF_getencprop(node,  "nvidia,usb2-companion",
1010 		   &(port->companion), sizeof(port->companion));
1011 		if (rv <= 0) {
1012 			device_printf(sc->dev,
1013 			    "Missing 'nvidia,usb2-companion' property "
1014 			    "for port: %s\n", name);
1015 			rv = ENXIO;
1016 			goto end;
1017 		}
1018 	}
1019 
1020 	if (OF_hasprop(node, "vbus-supply")) {
1021 		rv = regulator_get_by_ofw_property(sc->dev, 0,
1022 		    "vbus-supply", &port->supply_vbus);
1023 		if (rv <= 0) {
1024 			device_printf(sc->dev,
1025 			    "Cannot get 'vbus-supply' regulator "
1026 			    "for port: %s\n", name);
1027 			rv = ENXIO;
1028 			goto end;
1029 		}
1030 	}
1031 
1032 	if (OF_hasprop(node, "nvidia,internal"))
1033 		port->internal = true;
1034 	/* Find assigned lane */
1035 	if (port->lane == NULL) {
1036 		switch(port->type) {
1037 		/* Routing is fixed for USB2, ULPI AND HSIC. */
1038 		case PADCTL_PORT_USB2:
1039 			port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
1040 			    port->idx);
1041 			break;
1042 		case PADCTL_PORT_ULPI:
1043 			port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI,
1044 			    port->idx);
1045 			break;
1046 		case PADCTL_PORT_HSIC:
1047 			port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
1048 			    port->idx);
1049 			break;
1050 		case PADCTL_PORT_USB3:
1051 			port->lane = search_usb3_pad_lane(sc, port->idx);
1052 			break;
1053 		}
1054 	}
1055 	if (port->lane == NULL) {
1056 		device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
1057 		rv = ENXIO;
1058 		goto end;
1059 	}
1060 	port->enabled = true;
1061 	rv = 0;
1062 end:
1063 	if (name != NULL)
1064 		OF_prop_free(name);
1065 	return (rv);
1066 }
1067 
1068 static int
1069 parse_fdt(struct padctl_softc *sc, phandle_t base_node)
1070 {
1071 	phandle_t node;
1072 	int rv;
1073 
1074 	rv = 0;
1075 	node = ofw_bus_find_child(base_node, "pads");
1076 
1077 	if (node <= 0) {
1078 		device_printf(sc->dev, "Cannot find pads subnode.\n");
1079 		return (ENXIO);
1080 	}
1081 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1082 		if (!ofw_bus_node_status_okay(node))
1083 			continue;
1084 		rv = process_pad(sc, node);
1085 		if (rv != 0)
1086 			return (rv);
1087 	}
1088 
1089 	node = ofw_bus_find_child(base_node, "ports");
1090 	if (node <= 0) {
1091 		device_printf(sc->dev, "Cannot find ports subnode.\n");
1092 		return (ENXIO);
1093 	}
1094 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1095 		if (!ofw_bus_node_status_okay(node))
1096 			continue;
1097 		rv = process_port(sc, node);
1098 		if (rv != 0)
1099 			return (rv);
1100 	}
1101 
1102 	return (0);
1103 }
1104 
1105 static void
1106 load_calibration(struct padctl_softc *sc)
1107 {
1108 	uint32_t reg;
1109 
1110 	/* All XUSB pad calibrations are packed into single dword.*/
1111 	reg = tegra_fuse_read_4(FUSE_XUSB_CALIB);
1112 	sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg);
1113 	sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg);
1114 	sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg);
1115 	sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg);
1116 	sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg);
1117 }
1118 
1119 /* -------------------------------------------------------------------------
1120  *
1121  *   BUS functions
1122  */
1123 static int
1124 xusbpadctl_probe(device_t dev)
1125 {
1126 
1127 	if (!ofw_bus_status_okay(dev))
1128 		return (ENXIO);
1129 
1130 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
1131 		return (ENXIO);
1132 
1133 	device_set_desc(dev, "Tegra XUSB phy");
1134 	return (BUS_PROBE_DEFAULT);
1135 }
1136 
1137 static int
1138 xusbpadctl_detach(device_t dev)
1139 {
1140 
1141 	/* This device is always present. */
1142 	return (EBUSY);
1143 }
1144 
1145 static int
1146 xusbpadctl_attach(device_t dev)
1147 {
1148 	struct padctl_softc * sc;
1149 	int i, rid, rv;
1150 	struct padctl_port *port;
1151 	phandle_t node;
1152 
1153 	sc = device_get_softc(dev);
1154 	sc->dev = dev;
1155 	node = ofw_bus_get_node(dev);
1156 
1157 	rid = 0;
1158 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1159 	    RF_ACTIVE);
1160 	if (sc->mem_res == NULL) {
1161 		device_printf(dev, "Cannot allocate memory resources\n");
1162 		return (ENXIO);
1163 	}
1164 
1165 	rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
1166 	if (rv != 0) {
1167 		device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
1168 		return (rv);
1169 	}
1170 	rv = hwreset_deassert(sc->rst);
1171 	if (rv != 0) {
1172 		device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
1173 		return (rv);
1174 	}
1175 
1176 	load_calibration(sc);
1177 
1178 	rv = parse_fdt(sc, node);
1179 	if (rv != 0) {
1180 		device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
1181 		return (rv);
1182 	}
1183 	for (i = 0; i < nitems(ports_tbl); i++) {
1184 		port = ports_tbl + i;
1185 		if (!port->enabled)
1186 			continue;
1187 		if (port->init == NULL)
1188 			continue;
1189 		rv = port->init(sc, port);
1190 		if (rv != 0) {
1191 			device_printf(dev, "Cannot init port '%s'\n",
1192 			    port->name);
1193 			return (rv);
1194 		}
1195 	}
1196 	return (0);
1197 }
1198 
1199 static device_method_t tegra_xusbpadctl_methods[] = {
1200 	/* Device interface */
1201 	DEVMETHOD(device_probe,         xusbpadctl_probe),
1202 	DEVMETHOD(device_attach,        xusbpadctl_attach),
1203 	DEVMETHOD(device_detach,        xusbpadctl_detach),
1204 
1205 	DEVMETHOD_END
1206 };
1207 
1208 static devclass_t tegra_xusbpadctl_devclass;
1209 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
1210     tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
1211 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
1212     tegra_xusbpadctl_devclass, NULL, NULL, 73);
1213