xref: /freebsd/sys/arm/nvidia/tegra124/tegra124_xusbpadctl.c (revision af6a5351a1fdb1130f18be6c782c4d48916eb971)
1 /*-
2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  */
28 
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/malloc.h>
35 #include <sys/rman.h>
36 
37 #include <machine/bus.h>
38 #include <machine/fdt.h>
39 
40 #include <dev/extres/hwreset/hwreset.h>
41 #include <dev/extres/phy/phy.h>
42 #include <dev/extres/regulator/regulator.h>
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/fdt/fdt_pinctrl.h>
45 #include <dev/ofw/openfirm.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48 
49 #include <arm/nvidia/tegra_efuse.h>
50 
51 #include <gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
52 
53 #include "phy_if.h"
54 
55 /* FUSE calibration data. */
56 #define	FUSE_XUSB_CALIB				0x0F0
57 #define	  FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x)		(((x) >> 15) & 0x3F);
58 #define	  FUSE_XUSB_CALIB_HS_IREF_CAP(x)		(((x) >> 13) & 0x03);
59 #define	  FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x)		(((x) >> 11) & 0x03);
60 #define	  FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x)		(((x) >>  7) & 0x0F);
61 #define	  FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x)		(((x) >>  0) & 0x3F);
62 
63 
64 /* Registers. */
65 #define	XUSB_PADCTL_USB2_PAD_MUX		0x004
66 
67 #define	XUSB_PADCTL_USB2_PORT_CAP		0x008
68 #define	 USB2_PORT_CAP_ULPI_PORT_INTERNAL		(1 << 25)
69 #define	 USB2_PORT_CAP_ULPI_PORT_CAP			(1 << 24)
70 #define	 USB2_PORT_CAP_PORT_REVERSE_ID(p)		(1 << (3 + (p) * 4))
71 #define	 USB2_PORT_CAP_PORT_INTERNAL(p)			(1 << (2 + (p) * 4))
72 #define	 USB2_PORT_CAP_PORT_CAP(p, x)			(((x) & 3) << ((p) * 4))
73 #define	  USB2_PORT_CAP_PORT_CAP_OTG			0x3
74 #define	  USB2_PORT_CAP_PORT_CAP_DEVICE			0x2
75 #define	  USB2_PORT_CAP_PORT_CAP_HOST			0x1
76 #define	  USB2_PORT_CAP_PORT_CAP_DISABLED		0x0
77 
78 #define	XUSB_PADCTL_SS_PORT_MAP			0x014
79 #define	 SS_PORT_MAP_PORT_INTERNAL(p)			(1 << (3 + (p) * 4))
80 #define	 SS_PORT_MAP_PORT_MAP(p, x)			(((x) & 7) << ((p) * 4))
81 
82 #define	XUSB_PADCTL_ELPG_PROGRAM		0x01C
83 #define	 ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN		(1 << 26)
84 #define	 ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY	(1 << 25)
85 #define	 ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN		(1 << 24)
86 #define	 ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) 		(1 << (18 + (x) * 4))
87 #define	 ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) 	(1 << (17 + (x) * 4))
88 #define	 ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x)		(1 << (16 + (x) * 4))
89 
90 #define	XUSB_PADCTL_IOPHY_PLL_P0_CTL1		0x040
91 #define	 IOPHY_PLL_P0_CTL1_PLL0_LOCKDET			(1 << 19)
92 #define	 IOPHY_PLL_P0_CTL1_REFCLK_SEL(x)		(((x) & 0xF) << 12)
93 #define	 IOPHY_PLL_P0_CTL1_PLL_RST			(1 << 1)
94 
95 #define	XUSB_PADCTL_IOPHY_PLL_P0_CTL2		0x044
96 #define	 IOPHY_PLL_P0_CTL2_REFCLKBUF_EN			(1 << 6)
97 #define	 IOPHY_PLL_P0_CTL2_TXCLKREF_EN			(1 << 5)
98 #define	 IOPHY_PLL_P0_CTL2_TXCLKREF_SEL			(1 << 4)
99 
100 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) 	(0x058 + (x) * 4)
101 #define	 IOPHY_USB3_PAD_CTL2_CDR_CNTL(x)		(((x) & 0x00FF) <<  4)
102 #define	 IOPHY_USB3_PAD_CTL2_RX_EQ(x)			(((x) & 0xFFFF) <<  8)
103 #define	 IOPHY_USB3_PAD_CTL2_RX_WANDER(x)		(((x) & 0x000F) <<  4)
104 #define	 IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x)		(((x) & 0x0003) <<  2)
105 #define	 IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x)		(((x) & 0x0003) <<  0)
106 
107 
108 #define	XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x)	(0x068 + (x) * 4)
109 
110 #define	XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) 	(0x0A0 + (x) * 4)
111 #define	 USB2_OTG_PAD_CTL0_LSBIAS_SEL			(1 << 23)
112 #define	 USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD		(1 << 22)
113 #define	 USB2_OTG_PAD_CTL0_PD_ZI			(1 << 21)
114 #define	 USB2_OTG_PAD_CTL0_PD2				(1 << 20)
115 #define	 USB2_OTG_PAD_CTL0_PD				(1 << 19)
116 #define	 USB2_OTG_PAD_CTL0_TERM_EN			(1 << 18)
117 #define	 USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x)		(((x) & 0x03) << 16)
118 #define	 USB2_OTG_PAD_CTL0_LS_RSLEW(x)			(((x) & 0x03) << 14)
119 #define	 USB2_OTG_PAD_CTL0_FS_SLEW(x)			(((x) & 0x03) << 12)
120 #define	 USB2_OTG_PAD_CTL0_HS_SLEW(x)			(((x) & 0x3F) <<  6)
121 #define	 USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x)		(((x) & 0x3F) <<  0)
122 
123 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) 	(0x0AC + (x) * 4)
124 #define	 USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x)		(((x) & 0x3) << 11)
125 #define	 USB2_OTG_PAD_CTL1_HS_IREF_CAP(x)		(((x) & 0x3) <<  9)
126 #define	 USB2_OTG_PAD_CTL1_SPARE(x)			(((x) & 0x3) <<  7)
127 #define	 USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x)		(((x) & 0xF) <<  3)
128 #define	 USB2_OTG_PAD_CTL1_PD_DR			(1 <<  2)
129 #define	 USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP	(1 <<  1)
130 #define	 USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP	(1 <<  0)
131 
132 #define	XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x0B8
133 #define	 USB2_BIAS_PAD_CTL0_ADJRPU(x)			(((x) & 0x7) << 14)
134 #define	 USB2_BIAS_PAD_CTL0_PD_TRK			(1 << 13)
135 #define	 USB2_BIAS_PAD_CTL0_PD				(1 << 12)
136 #define	 USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x)		(((x) & 0x3) <<  9)
137 #define	 USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x)		(((x) & 0x3) <<  7)
138 #define	 USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x)		(((x) & 0x3) <<  5)
139 #define	 USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x)		(((x) & 0x7) <<  2)
140 #define	 USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x)		(((x) & 0x3) <<  0)
141 
142 #define	XUSB_PADCTL_HSIC_PAD0_CTL0		0x0C8
143 #define	 HSIC_PAD0_CTL0_HSIC_OPT(x)			(((x) & 0xF) << 16)
144 #define	 HSIC_PAD0_CTL0_TX_SLEWN(x)			(((x) & 0xF) << 12)
145 #define	 HSIC_PAD0_CTL0_TX_SLEWP(x)			(((x) & 0xF) <<  8)
146 #define	 HSIC_PAD0_CTL0_TX_RTUNEN(x)			(((x) & 0xF) <<  4)
147 #define	 HSIC_PAD0_CTL0_TX_RTUNEP(x)			(((x) & 0xF) <<  0)
148 
149 #define	XUSB_PADCTL_USB3_PAD_MUX		0x134
150 #define	 USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) 		(1 << (1 + (x)))
151 #define	 USB3_PAD_MUX_SATA_IDDQ_DISABLE 		(1 << 6)
152 
153 
154 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL1		0x138
155 #define	 IOPHY_PLL_S0_CTL1_PLL1_LOCKDET			(1 << 27)
156 #define	 IOPHY_PLL_S0_CTL1_PLL1_MODE			(1 << 24)
157 #define	 IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD			(1 << 3)
158 #define	 IOPHY_PLL_S0_CTL1_PLL_RST_L			(1 << 1)
159 #define	 IOPHY_PLL_S0_CTL1_PLL_IDDQ			(1 << 0)
160 
161 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL2		0x13C
162 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL3		0x140
163 #define	XUSB_PADCTL_IOPHY_PLL_S0_CTL4		0x144
164 
165 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1	0x148
166 #define	 IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD		(1 << 1)
167 #define	 IOPHY_MISC_PAD_S0_CTL1_IDDQ			(1 << 0)
168 
169 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2	0x14C
170 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3	0x150
171 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4	0x154
172 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5	0x158
173 #define	XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6	0x15C
174 
175 
176 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, (_r), (_v))
177 #define	RD4(_sc, _r)		bus_read_4((_sc)->mem_res, (_r))
178 
179 
180 struct padctl_softc {
181 	device_t	dev;
182 	struct resource	*mem_res;
183 	hwreset_t	rst;
184 	int		phy_ena_cnt;
185 
186 	/* Fuses calibration data */
187 	uint32_t	hs_curr_level_0;
188 	uint32_t	hs_curr_level_123;
189 	uint32_t	hs_iref_cap;
190 	uint32_t	hs_term_range_adj;
191 	uint32_t	hs_squelch_level;
192 
193 	uint32_t	hs_curr_level_offset;
194 };
195 
196 static struct ofw_compat_data compat_data[] = {
197 	{"nvidia,tegra124-xusb-padctl",	1},
198 	{NULL,				0},
199 };
200 
201 /* Ports. */
202 enum padctl_port_type {
203 	PADCTL_PORT_USB2,
204 	PADCTL_PORT_ULPI,
205 	PADCTL_PORT_HSIC,
206 	PADCTL_PORT_USB3,
207 };
208 
209 struct padctl_lane;
210 struct padctl_port {
211 	enum padctl_port_type	type;
212 	const char		*name;
213 	const char		*base_name;
214 	int			idx;
215 	int			(*init)(struct padctl_softc *sc,
216 				    struct padctl_port *port);
217 
218 	/* Runtime data. */
219 	phandle_t		xref;
220 	bool			enabled;
221 	regulator_t		supply_vbus;	/* USB2, USB3 */
222 	bool			internal;	/* ULPI, USB2, USB3 */
223 	uint32_t		companion;	/* USB3 */
224 	struct padctl_lane	*lane;
225 };
226 
227 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
228 
229 #define	PORT(t, n, p, i) {						\
230 	.type = t,							\
231 	.name = n "-" #p,						\
232 	.base_name = n,							\
233 	.idx = p,							\
234 	.init = i,							\
235 }
236 static struct padctl_port ports_tbl[] = {
237 	PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
238 	PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
239 	PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
240 	PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL),
241 	PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
242 	PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
243 	PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
244 	PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
245 };
246 
247 /* Pads - a group of lannes. */
248 enum padctl_pad_type {
249 	PADCTL_PAD_USB2,
250 	PADCTL_PAD_ULPI,
251 	PADCTL_PAD_HSIC,
252 	PADCTL_PAD_PCIE,
253 	PADCTL_PAD_SATA,
254 };
255 
256 struct padctl_lane;
257 struct padctl_pad {
258 	const char		*name;
259 	enum padctl_pad_type	type;
260 	int			(*powerup)(struct padctl_softc *sc,
261 				    struct padctl_lane *lane);
262 	int			(*powerdown)(struct padctl_softc *sc,
263 				    struct padctl_lane *lane);
264 	/* Runtime data. */
265 	bool			enabled;
266 	struct padctl_lane	*lanes[8]; 	/* Safe maximum value. */
267 	int			nlanes;
268 };
269 
270 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
271 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
272 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
273 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
274 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
275 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
276 
277 #define	PAD(n, t, u, d) {						\
278 	.name = n,							\
279 	.type = t,							\
280 	.powerup = u,							\
281 	.powerdown = d,							\
282 }
283 static struct padctl_pad pads_tbl[] = {
284 	PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown),
285 	PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL),
286 	PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL),
287 	PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown),
288 	PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown),
289 };
290 
291 /* Lanes. */
292 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"};
293 static char *usb_mux[] = {"snps", "xusb"};
294 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"};
295 
296 struct padctl_lane {
297 	const char		*name;
298 	int			idx;
299 	bus_size_t		reg;
300 	uint32_t		shift;
301 	uint32_t		mask;
302 	char			**mux;
303 	int			nmux;
304 	/* Runtime data. */
305 	bool			enabled;
306 	phandle_t		xref;
307 	struct padctl_pad	*pad;
308 	struct padctl_port	*port;
309 	int			mux_idx;
310 
311 };
312 
313 #define	LANE(n, p, r, s, m, mx) {					\
314 	.name = n "-" #p,						\
315 	.idx = p,							\
316 	.reg = r,							\
317 	.shift = s,							\
318 	.mask = m,							\
319 	.mux = mx,							\
320 	.nmux = nitems(mx),						\
321 }
322 static struct padctl_lane lanes_tbl[] = {
323 	LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX,  0, 0x3, otg_mux),
324 	LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX,  2, 0x3, otg_mux),
325 	LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX,  4, 0x3, otg_mux),
326 	LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux),
327 	LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux),
328 	LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux),
329 	LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
330 	LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
331 	LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
332 	LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
333 	LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
334 	LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux),
335 };
336 
337 /* Define all possible mappings for USB3 port lanes */
338 struct padctl_lane_map {
339 	int			port_idx;
340 	enum padctl_pad_type	pad_type;
341 	int			lane_idx;
342 };
343 
344 #define	LANE_MAP(pi, pt, li) {						\
345 	.port_idx = pi,							\
346 	.pad_type = pt,							\
347 	.lane_idx = li,							\
348 }
349 static struct padctl_lane_map lane_map_tbl[] = {
350 	LANE_MAP(0, PADCTL_PAD_PCIE, 0), 	/* port USB3-0 -> lane PCIE-0 */
351 	LANE_MAP(1, PADCTL_PAD_PCIE, 1), 	/* port USB3-1 -> lane PCIE-1 */
352 						/* -- or -- */
353 	LANE_MAP(1, PADCTL_PAD_SATA, 0), 	/* port USB3-1 -> lane SATA-0 */
354 };
355 
356 static struct padctl_port *search_lane_port(struct padctl_softc *sc,
357     struct padctl_lane *lane);
358 /* -------------------------------------------------------------------------
359  *
360  *   PHY functions
361  */
362 static int
363 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
364 {
365 	uint32_t reg;
366 
367 	reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
368 	if (port->internal)
369 		reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
370 	else
371 		reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
372 	reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
373 	reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
374 	WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
375 
376 	reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx));
377 	reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0);
378 	reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0);
379 	reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0);
380 	reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24);
381 	reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070);
382 	reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF);
383 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg);
384 
385 	WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx),
386 	    0x002008EE);
387 
388 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
389 	reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx);
390 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
391 	DELAY(100);
392 
393 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
394 	reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
395 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
396 	DELAY(100);
397 
398 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
399 	reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx);
400 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
401 	DELAY(100);
402 
403 	return (0);
404 }
405 
406 static int
407 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
408 {
409 	uint32_t reg;
410 	int i;
411 
412 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
413 	reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0);
414 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
415 	DELAY(100);
416 
417 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
418 	reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN;
419 	reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN;
420 	reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
421 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg);
422 	DELAY(100);
423 
424 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
425 	reg |= IOPHY_PLL_P0_CTL1_PLL_RST;
426 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
427 	DELAY(100);
428 
429 	for (i = 100; i > 0; i--) {
430 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
431 		if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET)
432 			break;
433 		DELAY(10);
434 	}
435 	if (i <= 0) {
436 		device_printf(sc->dev, "Failed to power up PCIe phy\n");
437 		return (ETIMEDOUT);
438 	}
439 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
440 	reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
441 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
442 
443 	return (0);
444 }
445 
446 static int
447 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
448 {
449 	uint32_t reg;
450 
451 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
452 	reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
453 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
454 
455 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
456 	reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST;
457 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg);
458 	DELAY(100);
459 
460 	return (0);
461 
462 }
463 
464 static int
465 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
466 {
467 	uint32_t reg;
468 	int i;
469 
470 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
471 	reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
472 	reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ;
473 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
474 
475 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
476 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
477 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ;
478 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
479 
480 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
481 	reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE;
482 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
483 
484 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
485 	reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
486 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
487 
488 	for (i = 100; i >= 0; i--) {
489 		reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
490 		if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
491 			break;
492 		DELAY(100);
493 	}
494 	if (i <= 0) {
495 		device_printf(sc->dev, "Failed to power up SATA phy\n");
496 		return (ETIMEDOUT);
497 	}
498 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
499 	reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L;
500 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
501 
502 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
503 	reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE;
504 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
505 
506 	return (0);
507 }
508 
509 static int
510 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
511 {
512 	uint32_t reg;
513 
514 	reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
515 	reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE;
516 	WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
517 
518 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
519 	reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L;
520 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
521 	DELAY(100);
522 
523 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
524 	reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE;
525 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
526 	DELAY(100);
527 
528 	reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
529 	reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
530 	reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ;
531 	WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg);
532 	DELAY(100);
533 
534 	reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
535 	reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
536 	reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ;
537 	WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg);
538 	DELAY(100);
539 
540 	return (0);
541 }
542 
543 static int
544 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane)
545 {
546 	uint32_t reg;
547 	struct padctl_port *port;
548 	int rv;
549 
550 	port = search_lane_port(sc, lane);
551 	if (port == NULL) {
552 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
553 		    lane->name);
554 	}
555 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
556 	reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
557 	reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
558 	reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level);
559 	reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5);
560 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
561 
562 	reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
563 	reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
564 	reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
565 	WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
566 
567 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
568 	reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
569 	reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
570 	reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0);
571 	reg &= ~USB2_OTG_PAD_CTL0_PD;
572 	reg &= ~USB2_OTG_PAD_CTL0_PD2;
573 	reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
574 
575 	reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
576 	if (lane->idx == 0) {
577 		reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0);
578 		reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3);
579 	} else {
580 		reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123);
581 		reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0);
582 	}
583 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
584 
585 	reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
586 	reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
587 	reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0);
588 	reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
589 	reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP;
590 	reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP;
591 
592 	reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
593 	reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap);
594 	WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
595 
596 	if (port != NULL && port->supply_vbus != NULL) {
597 		rv = regulator_enable(port->supply_vbus);
598 		if (rv != 0) {
599 			device_printf(sc->dev,
600 			    "Cannot enable vbus regulator\n");
601 			return (rv);
602 		}
603 	}
604 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
605 	reg &= ~USB2_BIAS_PAD_CTL0_PD;
606 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
607 
608 	return (0);
609 }
610 
611 static int
612 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane)
613 {
614 	uint32_t reg;
615 	struct padctl_port *port;
616 	int rv;
617 
618 	port = search_lane_port(sc, lane);
619 	if (port == NULL) {
620 		device_printf(sc->dev, "Cannot find port for lane: %s\n",
621 		    lane->name);
622 	}
623 	reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
624 	reg |= USB2_BIAS_PAD_CTL0_PD;
625 	WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
626 
627 	if (port != NULL && port->supply_vbus != NULL) {
628 		rv = regulator_enable(port->supply_vbus);
629 		if (rv != 0) {
630 			device_printf(sc->dev,
631 			    "Cannot disable vbus regulator\n");
632 			return (rv);
633 		}
634 	}
635 	return (0);
636 }
637 
638 
639 static int
640 phy_powerup(struct padctl_softc *sc)
641 {
642 	uint32_t reg;
643 
644 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
645 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
646 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
647 	DELAY(100);
648 
649 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
650 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
651 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
652 	DELAY(100);
653 
654 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
655 	reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
656 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
657 	DELAY(100);
658 
659 	return (0);
660 }
661 
662 static int
663 phy_powerdown(struct padctl_softc *sc)
664 {
665 	uint32_t reg;
666 
667 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
668 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
669 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
670 	DELAY(100);
671 
672 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
673 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
674 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
675 	DELAY(100);
676 
677 	reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM);
678 	reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
679 	WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg);
680 	DELAY(100);
681 
682 	return (0);
683 }
684 
685 static int
686 xusbpadctl_phy_enable(device_t dev, intptr_t id, bool enable)
687 {
688 	struct padctl_softc *sc;
689 	struct padctl_lane *lane;
690 	struct padctl_pad *pad;
691 	int rv;
692 
693 	sc = device_get_softc(dev);
694 
695 	if (id < 0 || id >= nitems(lanes_tbl)) {
696 		device_printf(dev, "Unknown phy: %d\n", id);
697 		return (ENXIO);
698 	}
699 	lane = lanes_tbl + id;
700 	if (!lane->enabled) {
701 		device_printf(dev, "Lane is not enabled/configured: %s\n",
702 		    lane->name);
703 		return (ENXIO);
704 	}
705 	pad = lane->pad;
706 	if (enable) {
707 		if (sc->phy_ena_cnt == 0) {
708 			rv = phy_powerup(sc);
709 			if (rv != 0)
710 				return (rv);
711 		}
712 		sc->phy_ena_cnt++;
713 	}
714 
715 	if (enable)
716 		rv = pad->powerup(sc, lane);
717 	else
718 		rv = pad->powerdown(sc, lane);
719 	if (rv != 0)
720 		return (rv);
721 
722 	if (!enable) {
723 		 if (sc->phy_ena_cnt == 1) {
724 			rv = phy_powerdown(sc);
725 			if (rv != 0)
726 				return (rv);
727 		}
728 		sc->phy_ena_cnt--;
729 	}
730 
731 	return (0);
732 }
733 
734 static int
735 xusbpadctl_phy_map(device_t provider, phandle_t xref, int ncells,
736     pcell_t *cells, intptr_t *id)
737 {
738 	int i;
739 
740 	if (ncells != 0)
741 		return  (ERANGE);
742 
743 	for (i = 0; i < nitems(lanes_tbl); i++) {
744 		if (lanes_tbl[i].xref == xref) {
745 			*id = i;
746 			return (0);
747 		}
748 	}
749 	return (ENXIO);
750 }
751 
752 /* -------------------------------------------------------------------------
753  *
754  *   FDT processing
755  */
756 static struct padctl_port *
757 search_port(struct padctl_softc *sc, char *port_name)
758 {
759 	int i;
760 
761 	for (i = 0; i < nitems(ports_tbl); i++) {
762 		if (strcmp(port_name, ports_tbl[i].name) == 0)
763 			return (&ports_tbl[i]);
764 	}
765 	return (NULL);
766 }
767 
768 static struct padctl_port *
769 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
770 {
771 	int i;
772 
773 	for (i = 0; i < nitems(ports_tbl); i++) {
774 		if (!ports_tbl[i].enabled)
775 			continue;
776 		if (ports_tbl[i].lane == lane)
777 			return (ports_tbl + i);
778 	}
779 	return (NULL);
780 }
781 
782 static struct padctl_lane *
783 search_lane(struct padctl_softc *sc, char *lane_name)
784 {
785 	int i;
786 
787 	for (i = 0; i < nitems(lanes_tbl); i++) {
788 		if (strcmp(lane_name, lanes_tbl[i].name) == 0)
789 			return 	(lanes_tbl + i);
790 	}
791 	return (NULL);
792 }
793 
794 static struct padctl_lane *
795 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
796 {
797 	int i;
798 
799 	for (i = 0; i < nitems(lanes_tbl); i++) {
800 		if (!lanes_tbl[i].enabled)
801 			continue;
802 		if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
803 			return 	(lanes_tbl + i);
804 	}
805 	return (NULL);
806 }
807 
808 static struct padctl_lane *
809 search_usb3_pad_lane(struct padctl_softc *sc, int idx)
810 {
811 	int i;
812 	struct padctl_lane *lane, *tmp;
813 
814 	lane = NULL;
815 	for (i = 0; i < nitems(lane_map_tbl); i++) {
816 		if (idx != lane_map_tbl[i].port_idx)
817 			continue;
818 		tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
819 		    lane_map_tbl[i].lane_idx);
820 		if (tmp == NULL)
821 			continue;
822 		if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
823 			continue;
824 		if (lane != NULL) {
825 			device_printf(sc->dev, "Duplicated mappings found for"
826 			 " lanes: %s and %s\n", lane->name, tmp->name);
827 			return (NULL);
828 		}
829 		lane = tmp;
830 	}
831 	return (lane);
832 }
833 
834 static struct padctl_pad *
835 search_pad(struct padctl_softc *sc, char *pad_name)
836 {
837 	int i;
838 
839 	for (i = 0; i < nitems(pads_tbl); i++) {
840 		if (strcmp(pad_name, pads_tbl[i].name) == 0)
841 			return 	(pads_tbl + i);
842 	}
843 	return (NULL);
844 }
845 
846 static int
847 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
848 {
849 	int i;
850 
851 	for (i = 0; i < lane->nmux; i++) {
852 		if (strcmp(fnc_name, lane->mux[i]) == 0)
853 			return 	(i);
854 	}
855 	return (-1);
856 }
857 
858 static int
859 config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
860 {
861 	uint32_t reg;
862 
863 	reg = RD4(sc, lane->reg);
864 	reg &= ~(lane->mask << lane->shift);
865 	reg |=  (lane->mux_idx & lane->mask) << lane->shift;
866 	WR4(sc, lane->reg, reg);
867 	return (0);
868 }
869 
870 static int
871 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
872 {
873 	struct padctl_lane *lane;
874 	char *name;
875 	char *function;
876 	int rv;
877 
878 	name = NULL;
879 	function = NULL;
880 	rv = OF_getprop_alloc(node, "name", 1, (void **)&name);
881 	if (rv <= 0) {
882 		device_printf(sc->dev, "Cannot read lane name.\n");
883 		return (ENXIO);
884 	}
885 
886 	lane = search_lane(sc, name);
887 	if (lane == NULL) {
888 		device_printf(sc->dev, "Unknown lane: %s\n", name);
889 		rv = ENXIO;
890 		goto end;
891 	}
892 
893 	/* Read function (mux) settings. */
894 	rv = OF_getprop_alloc(node, "nvidia,function", 1, (void **)&function);
895 	if (rv <= 0) {
896 		device_printf(sc->dev, "Cannot read lane function.\n");
897 		rv = ENXIO;
898 		goto end;
899 	}
900 
901 	lane->mux_idx = search_mux(sc, lane, function);
902 	if (lane->mux_idx == ~0) {
903 		device_printf(sc->dev, "Unknown function %s for lane %s\n",
904 		    function, name);
905 		rv = ENXIO;
906 		goto end;
907 	}
908 
909 	rv = config_lane(sc, lane);
910 	if (rv != 0) {
911 		device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
912 		    name, rv);
913 		rv = ENXIO;
914 		goto end;
915 	}
916 	lane->xref = OF_xref_from_node(node);
917 	lane->pad = pad;
918 	lane->enabled = true;
919 	pad->lanes[pad->nlanes++] = lane;
920 	rv = 0;
921 
922 end:
923 	if (name != NULL)
924 		OF_prop_free(name);
925 	if (function != NULL)
926 		OF_prop_free(function);
927 	return (rv);
928 }
929 
930 static int
931 process_pad(struct padctl_softc *sc, phandle_t node)
932 {
933 	phandle_t  xref;
934 	struct padctl_pad *pad;
935 	char *name;
936 	int rv;
937 
938 	name = NULL;
939 	rv = OF_getprop_alloc(node, "name", 1, (void **)&name);
940 	if (rv <= 0) {
941 		device_printf(sc->dev, "Cannot read pad name.\n");
942 		return (ENXIO);
943 	}
944 	pad = search_pad(sc, name);
945 	if (pad == NULL) {
946 		device_printf(sc->dev, "Unknown pad: %s\n", name);
947 		rv = ENXIO;
948 		goto end;
949 	}
950 
951 	/* Read and process associated lanes. */
952 	node = ofw_bus_find_child(node, "lanes");
953 	if (node <= 0) {
954 		device_printf(sc->dev, "Cannot find regulators subnode\n");
955 		rv = ENXIO;
956 		goto end;
957 	}
958 
959 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
960 		if (!fdt_is_enabled(node))
961 			continue;
962 
963 		rv = process_lane(sc, node, pad);
964 		if (rv != 0)
965 			goto end;
966 
967 		xref = OF_xref_from_node(node);
968 		OF_device_register_xref(xref, sc->dev);
969 	}
970 	pad->enabled = true;
971 	rv = 0;
972 end:
973 	if (name != NULL)
974 		OF_prop_free(name);
975 	return (rv);
976 }
977 
978 static int
979 process_port(struct padctl_softc *sc, phandle_t node)
980 {
981 
982 	struct padctl_port *port;
983 	char *name;
984 	int rv;
985 
986 	name = NULL;
987 	rv = OF_getprop_alloc(node, "name", 1, (void **)&name);
988 	if (rv <= 0) {
989 		device_printf(sc->dev, "Cannot read port name.\n");
990 		return (ENXIO);
991 	}
992 
993 	port = search_port(sc, name);
994 	if (port == NULL) {
995 		device_printf(sc->dev, "Unknown port: %s\n", name);
996 		rv = ENXIO;
997 		goto end;
998 	}
999 
1000 	if (port->type == PADCTL_PORT_USB3) {
1001 		rv = OF_getencprop(node,  "nvidia,usb2-companion",
1002 		   &(port->companion), sizeof(port->companion));
1003 		if (rv <= 0) {
1004 			device_printf(sc->dev,
1005 			    "Missing 'nvidia,usb2-companion' property "
1006 			    "for port: %s\n", name);
1007 			rv = ENXIO;
1008 			goto end;
1009 		}
1010 	}
1011 
1012 	if (OF_hasprop(node, "vbus-supply")) {
1013 		rv = regulator_get_by_ofw_property(sc->dev, 0,
1014 		    "vbus-supply", &port->supply_vbus);
1015 		if (rv <= 0) {
1016 			device_printf(sc->dev,
1017 			    "Cannot get 'vbus-supply' regulator "
1018 			    "for port: %s\n", name);
1019 			rv = ENXIO;
1020 			goto end;
1021 		}
1022 	}
1023 
1024 	if (OF_hasprop(node, "nvidia,internal"))
1025 		port->internal = true;
1026 	/* Find assigned lane */
1027 	if (port->lane == NULL) {
1028 		switch(port->type) {
1029 		/* Routing is fixed for USB2, ULPI AND HSIC. */
1030 		case PADCTL_PORT_USB2:
1031 			port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
1032 			    port->idx);
1033 			break;
1034 		case PADCTL_PORT_ULPI:
1035 			port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI,
1036 			    port->idx);
1037 			break;
1038 		case PADCTL_PORT_HSIC:
1039 			port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
1040 			    port->idx);
1041 			break;
1042 		case PADCTL_PORT_USB3:
1043 			port->lane = search_usb3_pad_lane(sc, port->idx);
1044 			break;
1045 		}
1046 	}
1047 	if (port->lane == NULL) {
1048 		device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
1049 		rv = ENXIO;
1050 		goto end;
1051 	}
1052 	port->enabled = true;
1053 	rv = 0;
1054 end:
1055 	if (name != NULL)
1056 		OF_prop_free(name);
1057 	return (rv);
1058 }
1059 
1060 static int
1061 parse_fdt(struct padctl_softc *sc, phandle_t base_node)
1062 {
1063 	phandle_t node;
1064 	int rv;
1065 
1066 	rv = 0;
1067 	node = ofw_bus_find_child(base_node, "pads");
1068 
1069 	if (node <= 0) {
1070 		device_printf(sc->dev, "Cannot find pads subnode.\n");
1071 		return (ENXIO);
1072 	}
1073 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1074 		if (!fdt_is_enabled(node))
1075 			continue;
1076 		rv = process_pad(sc, node);
1077 		if (rv != 0)
1078 			return (rv);
1079 	}
1080 
1081 	node = ofw_bus_find_child(base_node, "ports");
1082 	if (node <= 0) {
1083 		device_printf(sc->dev, "Cannot find ports subnode.\n");
1084 		return (ENXIO);
1085 	}
1086 	for (node = OF_child(node); node != 0; node = OF_peer(node)) {
1087 		if (!fdt_is_enabled(node))
1088 			continue;
1089 		rv = process_port(sc, node);
1090 		if (rv != 0)
1091 			return (rv);
1092 	}
1093 
1094 	return (0);
1095 }
1096 
1097 static void
1098 load_calibration(struct padctl_softc *sc)
1099 {
1100 	uint32_t reg;
1101 
1102 	/* All XUSB pad calibrations are packed into single dword.*/
1103 	reg = tegra_fuse_read_4(FUSE_XUSB_CALIB);
1104 	sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg);
1105 	sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg);
1106 	sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg);
1107 	sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg);
1108 	sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg);
1109 }
1110 
1111 /* -------------------------------------------------------------------------
1112  *
1113  *   BUS functions
1114  */
1115 static int
1116 xusbpadctl_probe(device_t dev)
1117 {
1118 
1119 	if (!ofw_bus_status_okay(dev))
1120 		return (ENXIO);
1121 
1122 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
1123 		return (ENXIO);
1124 
1125 	device_set_desc(dev, "Tegra XUSB phy");
1126 	return (BUS_PROBE_DEFAULT);
1127 }
1128 
1129 static int
1130 xusbpadctl_detach(device_t dev)
1131 {
1132 
1133 	/* This device is always present. */
1134 	return (EBUSY);
1135 }
1136 
1137 static int
1138 xusbpadctl_attach(device_t dev)
1139 {
1140 	struct padctl_softc * sc;
1141 	int i, rid, rv;
1142 	struct padctl_port *port;
1143 	phandle_t node;
1144 
1145 	sc = device_get_softc(dev);
1146 	sc->dev = dev;
1147 	node = ofw_bus_get_node(dev);
1148 
1149 	rid = 0;
1150 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1151 	    RF_ACTIVE);
1152 	if (sc->mem_res == NULL) {
1153 		device_printf(dev, "Cannot allocate memory resources\n");
1154 		return (ENXIO);
1155 	}
1156 
1157 	rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
1158 	if (rv != 0) {
1159 		device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
1160 		return (rv);
1161 	}
1162 	rv = hwreset_deassert(sc->rst);
1163 	if (rv != 0) {
1164 		device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
1165 		return (rv);
1166 	}
1167 
1168 	load_calibration(sc);
1169 
1170 	rv = parse_fdt(sc, node);
1171 	if (rv != 0) {
1172 		device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
1173 		return (rv);
1174 	}
1175 	for (i = 0; i < nitems(ports_tbl); i++) {
1176 		port = ports_tbl + i;
1177 		if (!port->enabled)
1178 			continue;
1179 		if (port->init == NULL)
1180 			continue;
1181 		rv = port->init(sc, port);
1182 		if (rv != 0) {
1183 			device_printf(dev, "Cannot init port '%s'\n",
1184 			    port->name);
1185 			return (rv);
1186 		}
1187 	}
1188 	return (0);
1189 }
1190 
1191 static device_method_t tegra_xusbpadctl_methods[] = {
1192 	/* Device interface */
1193 	DEVMETHOD(device_probe,         xusbpadctl_probe),
1194 	DEVMETHOD(device_attach,        xusbpadctl_attach),
1195 	DEVMETHOD(device_detach,        xusbpadctl_detach),
1196 
1197 	/* phy interface */
1198 	DEVMETHOD(phy_enable,		xusbpadctl_phy_enable),
1199 	DEVMETHOD(phy_map,		xusbpadctl_phy_map),
1200 
1201 	DEVMETHOD_END
1202 };
1203 
1204 static devclass_t tegra_xusbpadctl_devclass;
1205 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
1206     tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
1207 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
1208     tegra_xusbpadctl_devclass, NULL, NULL, 73);
1209