1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/malloc.h> 33 #include <sys/rman.h> 34 35 #include <machine/bus.h> 36 #include <machine/fdt.h> 37 38 #include <dev/hwreset/hwreset.h> 39 #include <dev/phy/phy.h> 40 #include <dev/regulator/regulator.h> 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/fdt/fdt_pinctrl.h> 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <arm/nvidia/tegra_efuse.h> 48 49 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 50 51 #include "phydev_if.h" 52 53 /* FUSE calibration data. */ 54 #define FUSE_XUSB_CALIB 0x0F0 55 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x) (((x) >> 15) & 0x3F); 56 #define FUSE_XUSB_CALIB_HS_IREF_CAP(x) (((x) >> 13) & 0x03); 57 #define FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x) (((x) >> 11) & 0x03); 58 #define FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F); 59 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F); 60 61 /* Registers. */ 62 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 63 64 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 65 #define USB2_PORT_CAP_ULPI_PORT_INTERNAL (1 << 25) 66 #define USB2_PORT_CAP_ULPI_PORT_CAP (1 << 24) 67 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4)) 68 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4)) 69 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4)) 70 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3 71 #define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2 72 #define USB2_PORT_CAP_PORT_CAP_HOST 0x1 73 #define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0 74 75 #define XUSB_PADCTL_SS_PORT_MAP 0x014 76 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4)) 77 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4)) 78 79 #define XUSB_PADCTL_ELPG_PROGRAM 0x01C 80 #define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 81 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 82 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 83 #define ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4)) 84 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (17 + (x) * 4)) 85 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4)) 86 87 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 88 #define IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 89 #define IOPHY_PLL_P0_CTL1_REFCLK_SEL(x) (((x) & 0xF) << 12) 90 #define IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 91 92 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 93 #define IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 94 #define IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 95 #define IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 96 97 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) (0x058 + (x) * 4) 98 #define IOPHY_USB3_PAD_CTL2_CDR_CNTL(x) (((x) & 0x00FF) << 4) 99 #define IOPHY_USB3_PAD_CTL2_RX_EQ(x) (((x) & 0xFFFF) << 8) 100 #define IOPHY_USB3_PAD_CTL2_RX_WANDER(x) (((x) & 0x000F) << 4) 101 #define IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x) (((x) & 0x0003) << 2) 102 #define IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x) (((x) & 0x0003) << 0) 103 104 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x) (0x068 + (x) * 4) 105 106 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x0A0 + (x) * 4) 107 #define USB2_OTG_PAD_CTL0_LSBIAS_SEL (1 << 23) 108 #define USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD (1 << 22) 109 #define USB2_OTG_PAD_CTL0_PD_ZI (1 << 21) 110 #define USB2_OTG_PAD_CTL0_PD2 (1 << 20) 111 #define USB2_OTG_PAD_CTL0_PD (1 << 19) 112 #define USB2_OTG_PAD_CTL0_TERM_EN (1 << 18) 113 #define USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x) (((x) & 0x03) << 16) 114 #define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x03) << 14) 115 #define USB2_OTG_PAD_CTL0_FS_SLEW(x) (((x) & 0x03) << 12) 116 #define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6) 117 #define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0) 118 119 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x0AC + (x) * 4) 120 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x3) << 11) 121 #define USB2_OTG_PAD_CTL1_HS_IREF_CAP(x) (((x) & 0x3) << 9) 122 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x3) << 7) 123 #define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0xF) << 3) 124 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 125 #define USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP (1 << 1) 126 #define USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0) 127 128 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0B8 129 #define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 14) 130 #define USB2_BIAS_PAD_CTL0_PD_TRK (1 << 13) 131 #define USB2_BIAS_PAD_CTL0_PD (1 << 12) 132 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x3) << 9) 133 #define USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x) (((x) & 0x3) << 7) 134 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 5) 135 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 2) 136 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x3) << 0) 137 138 #define XUSB_PADCTL_HSIC_PAD0_CTL0 0x0C8 139 #define HSIC_PAD0_CTL0_HSIC_OPT(x) (((x) & 0xF) << 16) 140 #define HSIC_PAD0_CTL0_TX_SLEWN(x) (((x) & 0xF) << 12) 141 #define HSIC_PAD0_CTL0_TX_SLEWP(x) (((x) & 0xF) << 8) 142 #define HSIC_PAD0_CTL0_TX_RTUNEN(x) (((x) & 0xF) << 4) 143 #define HSIC_PAD0_CTL0_TX_RTUNEP(x) (((x) & 0xF) << 0) 144 145 #define XUSB_PADCTL_USB3_PAD_MUX 0x134 146 #define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 147 #define USB3_PAD_MUX_SATA_IDDQ_DISABLE (1 << 6) 148 149 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 150 #define IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 151 #define IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 152 #define IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 153 #define IOPHY_PLL_S0_CTL1_PLL_RST_L (1 << 1) 154 #define IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 155 156 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13C 157 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140 158 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL4 0x144 159 160 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 161 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 162 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 163 164 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14C 165 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3 0x150 166 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4 0x154 167 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158 168 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15C 169 170 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 171 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 172 173 struct padctl_softc { 174 device_t dev; 175 struct resource *mem_res; 176 hwreset_t rst; 177 int phy_ena_cnt; 178 179 /* Fuses calibration data */ 180 uint32_t hs_curr_level_0; 181 uint32_t hs_curr_level_123; 182 uint32_t hs_iref_cap; 183 uint32_t hs_term_range_adj; 184 uint32_t hs_squelch_level; 185 186 uint32_t hs_curr_level_offset; 187 }; 188 189 static struct ofw_compat_data compat_data[] = { 190 {"nvidia,tegra124-xusb-padctl", 1}, 191 {NULL, 0}, 192 }; 193 194 /* Ports. */ 195 enum padctl_port_type { 196 PADCTL_PORT_USB2, 197 PADCTL_PORT_ULPI, 198 PADCTL_PORT_HSIC, 199 PADCTL_PORT_USB3, 200 }; 201 202 struct padctl_lane; 203 struct padctl_port { 204 enum padctl_port_type type; 205 const char *name; 206 const char *base_name; 207 int idx; 208 int (*init)(struct padctl_softc *sc, 209 struct padctl_port *port); 210 211 /* Runtime data. */ 212 bool enabled; 213 regulator_t supply_vbus; /* USB2, USB3 */ 214 bool internal; /* ULPI, USB2, USB3 */ 215 uint32_t companion; /* USB3 */ 216 struct padctl_lane *lane; 217 }; 218 219 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port); 220 221 #define PORT(t, n, p, i) { \ 222 .type = t, \ 223 .name = n "-" #p, \ 224 .base_name = n, \ 225 .idx = p, \ 226 .init = i, \ 227 } 228 static struct padctl_port ports_tbl[] = { 229 PORT(PADCTL_PORT_USB2, "usb2", 0, NULL), 230 PORT(PADCTL_PORT_USB2, "usb2", 1, NULL), 231 PORT(PADCTL_PORT_USB2, "usb2", 2, NULL), 232 PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL), 233 PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL), 234 PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL), 235 PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init), 236 PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init), 237 }; 238 239 /* Pads - a group of lannes. */ 240 enum padctl_pad_type { 241 PADCTL_PAD_USB2, 242 PADCTL_PAD_ULPI, 243 PADCTL_PAD_HSIC, 244 PADCTL_PAD_PCIE, 245 PADCTL_PAD_SATA, 246 }; 247 248 struct padctl_lane; 249 struct padctl_pad { 250 const char *name; 251 enum padctl_pad_type type; 252 int (*powerup)(struct padctl_softc *sc, 253 struct padctl_lane *lane); 254 int (*powerdown)(struct padctl_softc *sc, 255 struct padctl_lane *lane); 256 /* Runtime data. */ 257 bool enabled; 258 struct padctl_lane *lanes[8]; /* Safe maximum value. */ 259 int nlanes; 260 }; 261 262 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 263 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 264 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 265 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 266 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 267 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 268 269 #define PAD(n, t, u, d) { \ 270 .name = n, \ 271 .type = t, \ 272 .powerup = u, \ 273 .powerdown = d, \ 274 } 275 static struct padctl_pad pads_tbl[] = { 276 PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown), 277 PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL), 278 PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL), 279 PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown), 280 PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown), 281 }; 282 283 /* Lanes. */ 284 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"}; 285 static char *usb_mux[] = {"snps", "xusb"}; 286 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"}; 287 288 struct padctl_lane { 289 const char *name; 290 int idx; 291 bus_size_t reg; 292 uint32_t shift; 293 uint32_t mask; 294 char **mux; 295 int nmux; 296 /* Runtime data. */ 297 bool enabled; 298 struct padctl_pad *pad; 299 struct padctl_port *port; 300 int mux_idx; 301 302 }; 303 304 #define LANE(n, p, r, s, m, mx) { \ 305 .name = n "-" #p, \ 306 .idx = p, \ 307 .reg = r, \ 308 .shift = s, \ 309 .mask = m, \ 310 .mux = mx, \ 311 .nmux = nitems(mx), \ 312 } 313 static struct padctl_lane lanes_tbl[] = { 314 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, otg_mux), 315 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, otg_mux), 316 LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, otg_mux), 317 LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux), 318 LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux), 319 LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux), 320 LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux), 321 LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux), 322 LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux), 323 LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux), 324 LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux), 325 LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux), 326 }; 327 328 /* Define all possible mappings for USB3 port lanes */ 329 struct padctl_lane_map { 330 int port_idx; 331 enum padctl_pad_type pad_type; 332 int lane_idx; 333 }; 334 335 #define LANE_MAP(pi, pt, li) { \ 336 .port_idx = pi, \ 337 .pad_type = pt, \ 338 .lane_idx = li, \ 339 } 340 static struct padctl_lane_map lane_map_tbl[] = { 341 LANE_MAP(0, PADCTL_PAD_PCIE, 0), /* port USB3-0 -> lane PCIE-0 */ 342 LANE_MAP(1, PADCTL_PAD_PCIE, 1), /* port USB3-1 -> lane PCIE-1 */ 343 /* -- or -- */ 344 LANE_MAP(1, PADCTL_PAD_SATA, 0), /* port USB3-1 -> lane SATA-0 */ 345 }; 346 347 /* Phy class and methods. */ 348 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable); 349 static phynode_method_t xusbpadctl_phynode_methods[] = { 350 PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable), 351 PHYNODEMETHOD_END 352 353 }; 354 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class, 355 xusbpadctl_phynode_methods, 0, phynode_class); 356 357 static struct padctl_port *search_lane_port(struct padctl_softc *sc, 358 struct padctl_lane *lane); 359 /* ------------------------------------------------------------------------- 360 * 361 * PHY functions 362 */ 363 static int 364 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port) 365 { 366 uint32_t reg; 367 368 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); 369 if (port->internal) 370 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); 371 else 372 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); 373 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); 374 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); 375 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 376 377 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); 378 reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0); 379 reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0); 380 reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0); 381 reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24); 382 reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070); 383 reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF); 384 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); 385 386 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), 387 0x002008EE); 388 389 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 390 reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx); 391 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 392 DELAY(100); 393 394 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 395 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx); 396 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 397 DELAY(100); 398 399 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 400 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx); 401 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 402 DELAY(100); 403 404 return (0); 405 } 406 407 static int 408 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 409 { 410 uint32_t reg; 411 int i; 412 413 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 414 reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0); 415 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 416 DELAY(100); 417 418 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 419 reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN; 420 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN; 421 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 422 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); 423 DELAY(100); 424 425 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 426 reg |= IOPHY_PLL_P0_CTL1_PLL_RST; 427 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 428 DELAY(100); 429 430 for (i = 100; i > 0; i--) { 431 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 432 if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) 433 break; 434 DELAY(10); 435 } 436 if (i <= 0) { 437 device_printf(sc->dev, "Failed to power up PCIe phy\n"); 438 return (ETIMEDOUT); 439 } 440 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 441 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 442 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 443 444 return (0); 445 } 446 447 static int 448 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 449 { 450 uint32_t reg; 451 452 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 453 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 454 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 455 456 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 457 reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST; 458 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 459 DELAY(100); 460 461 return (0); 462 463 } 464 465 static int 466 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 467 { 468 uint32_t reg; 469 int i; 470 471 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 472 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 473 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ; 474 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 475 476 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 477 reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 478 reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ; 479 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 480 481 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 482 reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE; 483 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 484 485 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 486 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 487 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 488 489 for (i = 100; i >= 0; i--) { 490 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 491 if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 492 break; 493 DELAY(100); 494 } 495 if (i <= 0) { 496 device_printf(sc->dev, "Failed to power up SATA phy\n"); 497 return (ETIMEDOUT); 498 } 499 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 500 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 501 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 502 503 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 504 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE; 505 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 506 507 return (0); 508 } 509 510 static int 511 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 512 { 513 uint32_t reg; 514 515 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 516 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE; 517 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 518 519 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 520 reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L; 521 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 522 DELAY(100); 523 524 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 525 reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE; 526 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 527 DELAY(100); 528 529 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 530 reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 531 reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ; 532 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 533 DELAY(100); 534 535 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 536 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 537 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ; 538 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 539 DELAY(100); 540 541 return (0); 542 } 543 544 static int 545 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 546 { 547 uint32_t reg; 548 struct padctl_port *port; 549 int rv; 550 551 port = search_lane_port(sc, lane); 552 if (port == NULL) { 553 device_printf(sc->dev, "Cannot find port for lane: %s\n", 554 lane->name); 555 } 556 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 557 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0); 558 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0); 559 reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level); 560 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5); 561 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 562 563 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); 564 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); 565 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); 566 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); 567 568 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); 569 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0); 570 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0); 571 reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0); 572 reg &= ~USB2_OTG_PAD_CTL0_PD; 573 reg &= ~USB2_OTG_PAD_CTL0_PD2; 574 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI; 575 576 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14); 577 if (lane->idx == 0) { 578 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0); 579 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3); 580 } else { 581 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123); 582 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0); 583 } 584 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); 585 586 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); 587 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0); 588 reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0); 589 reg &= ~USB2_OTG_PAD_CTL1_PD_DR; 590 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP; 591 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP; 592 593 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); 594 reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap); 595 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); 596 597 if (port != NULL && port->supply_vbus != NULL) { 598 rv = regulator_enable(port->supply_vbus); 599 if (rv != 0) { 600 device_printf(sc->dev, 601 "Cannot enable vbus regulator\n"); 602 return (rv); 603 } 604 } 605 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 606 reg &= ~USB2_BIAS_PAD_CTL0_PD; 607 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 608 609 return (0); 610 } 611 612 static int 613 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 614 { 615 uint32_t reg; 616 struct padctl_port *port; 617 int rv; 618 619 port = search_lane_port(sc, lane); 620 if (port == NULL) { 621 device_printf(sc->dev, "Cannot find port for lane: %s\n", 622 lane->name); 623 } 624 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 625 reg |= USB2_BIAS_PAD_CTL0_PD; 626 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 627 628 if (port != NULL && port->supply_vbus != NULL) { 629 rv = regulator_enable(port->supply_vbus); 630 if (rv != 0) { 631 device_printf(sc->dev, 632 "Cannot disable vbus regulator\n"); 633 return (rv); 634 } 635 } 636 return (0); 637 } 638 639 static int 640 phy_powerup(struct padctl_softc *sc) 641 { 642 uint32_t reg; 643 644 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 645 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 646 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 647 DELAY(100); 648 649 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 650 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 651 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 652 DELAY(100); 653 654 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 655 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 656 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 657 DELAY(100); 658 659 return (0); 660 } 661 662 static int 663 phy_powerdown(struct padctl_softc *sc) 664 { 665 uint32_t reg; 666 667 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 668 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 669 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 670 DELAY(100); 671 672 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 673 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 674 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 675 DELAY(100); 676 677 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 678 reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 679 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 680 DELAY(100); 681 682 return (0); 683 } 684 685 static int 686 xusbpadctl_phy_enable(struct phynode *phy, bool enable) 687 { 688 device_t dev; 689 intptr_t id; 690 struct padctl_softc *sc; 691 struct padctl_lane *lane; 692 struct padctl_pad *pad; 693 int rv; 694 695 dev = phynode_get_device(phy); 696 id = phynode_get_id(phy); 697 sc = device_get_softc(dev); 698 699 if (id < 0 || id >= nitems(lanes_tbl)) { 700 device_printf(dev, "Unknown phy: %d\n", id); 701 return (ENXIO); 702 } 703 lane = lanes_tbl + id; 704 if (!lane->enabled) { 705 device_printf(dev, "Lane is not enabled/configured: %s\n", 706 lane->name); 707 return (ENXIO); 708 } 709 pad = lane->pad; 710 if (enable) { 711 if (sc->phy_ena_cnt == 0) { 712 rv = phy_powerup(sc); 713 if (rv != 0) 714 return (rv); 715 } 716 sc->phy_ena_cnt++; 717 } 718 719 if (enable) 720 rv = pad->powerup(sc, lane); 721 else 722 rv = pad->powerdown(sc, lane); 723 if (rv != 0) 724 return (rv); 725 726 if (!enable) { 727 if (sc->phy_ena_cnt == 1) { 728 rv = phy_powerdown(sc); 729 if (rv != 0) 730 return (rv); 731 } 732 sc->phy_ena_cnt--; 733 } 734 735 return (0); 736 } 737 738 /* ------------------------------------------------------------------------- 739 * 740 * FDT processing 741 */ 742 static struct padctl_port * 743 search_port(struct padctl_softc *sc, char *port_name) 744 { 745 int i; 746 747 for (i = 0; i < nitems(ports_tbl); i++) { 748 if (strcmp(port_name, ports_tbl[i].name) == 0) 749 return (&ports_tbl[i]); 750 } 751 return (NULL); 752 } 753 754 static struct padctl_port * 755 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane) 756 { 757 int i; 758 759 for (i = 0; i < nitems(ports_tbl); i++) { 760 if (!ports_tbl[i].enabled) 761 continue; 762 if (ports_tbl[i].lane == lane) 763 return (ports_tbl + i); 764 } 765 return (NULL); 766 } 767 768 static struct padctl_lane * 769 search_lane(struct padctl_softc *sc, char *lane_name) 770 { 771 int i; 772 773 for (i = 0; i < nitems(lanes_tbl); i++) { 774 if (strcmp(lane_name, lanes_tbl[i].name) == 0) 775 return (lanes_tbl + i); 776 } 777 return (NULL); 778 } 779 780 static struct padctl_lane * 781 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx) 782 { 783 int i; 784 785 for (i = 0; i < nitems(lanes_tbl); i++) { 786 if (!lanes_tbl[i].enabled) 787 continue; 788 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx) 789 return (lanes_tbl + i); 790 } 791 return (NULL); 792 } 793 794 static struct padctl_lane * 795 search_usb3_pad_lane(struct padctl_softc *sc, int idx) 796 { 797 int i; 798 struct padctl_lane *lane, *tmp; 799 800 lane = NULL; 801 for (i = 0; i < nitems(lane_map_tbl); i++) { 802 if (idx != lane_map_tbl[i].port_idx) 803 continue; 804 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type, 805 lane_map_tbl[i].lane_idx); 806 if (tmp == NULL) 807 continue; 808 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0) 809 continue; 810 if (lane != NULL) { 811 device_printf(sc->dev, "Duplicated mappings found for" 812 " lanes: %s and %s\n", lane->name, tmp->name); 813 return (NULL); 814 } 815 lane = tmp; 816 } 817 return (lane); 818 } 819 820 static struct padctl_pad * 821 search_pad(struct padctl_softc *sc, char *pad_name) 822 { 823 int i; 824 825 for (i = 0; i < nitems(pads_tbl); i++) { 826 if (strcmp(pad_name, pads_tbl[i].name) == 0) 827 return (pads_tbl + i); 828 } 829 return (NULL); 830 } 831 832 static int 833 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name) 834 { 835 int i; 836 837 for (i = 0; i < lane->nmux; i++) { 838 if (strcmp(fnc_name, lane->mux[i]) == 0) 839 return (i); 840 } 841 return (-1); 842 } 843 844 static int 845 config_lane(struct padctl_softc *sc, struct padctl_lane *lane) 846 { 847 uint32_t reg; 848 849 reg = RD4(sc, lane->reg); 850 reg &= ~(lane->mask << lane->shift); 851 reg |= (lane->mux_idx & lane->mask) << lane->shift; 852 WR4(sc, lane->reg, reg); 853 return (0); 854 } 855 856 static int 857 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad) 858 { 859 struct padctl_lane *lane; 860 struct phynode *phynode; 861 struct phynode_init_def phy_init; 862 char *name; 863 char *function; 864 int rv; 865 866 name = NULL; 867 function = NULL; 868 rv = OF_getprop_alloc(node, "name", (void **)&name); 869 if (rv <= 0) { 870 device_printf(sc->dev, "Cannot read lane name.\n"); 871 return (ENXIO); 872 } 873 874 lane = search_lane(sc, name); 875 if (lane == NULL) { 876 device_printf(sc->dev, "Unknown lane: %s\n", name); 877 rv = ENXIO; 878 goto end; 879 } 880 881 /* Read function (mux) settings. */ 882 rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function); 883 if (rv <= 0) { 884 device_printf(sc->dev, "Cannot read lane function.\n"); 885 rv = ENXIO; 886 goto end; 887 } 888 889 lane->mux_idx = search_mux(sc, lane, function); 890 if (lane->mux_idx == ~0) { 891 device_printf(sc->dev, "Unknown function %s for lane %s\n", 892 function, name); 893 rv = ENXIO; 894 goto end; 895 } 896 897 rv = config_lane(sc, lane); 898 if (rv != 0) { 899 device_printf(sc->dev, "Cannot configure lane: %s: %d\n", 900 name, rv); 901 rv = ENXIO; 902 goto end; 903 } 904 lane->pad = pad; 905 lane->enabled = true; 906 pad->lanes[pad->nlanes++] = lane; 907 908 /* Create and register phy. */ 909 bzero(&phy_init, sizeof(phy_init)); 910 phy_init.id = lane - lanes_tbl; 911 phy_init.ofw_node = node; 912 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init); 913 if (phynode == NULL) { 914 device_printf(sc->dev, "Cannot create phy\n"); 915 rv = ENXIO; 916 goto end; 917 } 918 if (phynode_register(phynode) == NULL) { 919 device_printf(sc->dev, "Cannot create phy\n"); 920 return (ENXIO); 921 } 922 923 rv = 0; 924 925 end: 926 if (name != NULL) 927 OF_prop_free(name); 928 if (function != NULL) 929 OF_prop_free(function); 930 return (rv); 931 } 932 933 static int 934 process_pad(struct padctl_softc *sc, phandle_t node) 935 { 936 struct padctl_pad *pad; 937 char *name; 938 int rv; 939 940 name = NULL; 941 rv = OF_getprop_alloc(node, "name", (void **)&name); 942 if (rv <= 0) { 943 device_printf(sc->dev, "Cannot read pad name.\n"); 944 return (ENXIO); 945 } 946 pad = search_pad(sc, name); 947 if (pad == NULL) { 948 device_printf(sc->dev, "Unknown pad: %s\n", name); 949 rv = ENXIO; 950 goto end; 951 } 952 953 /* Read and process associated lanes. */ 954 node = ofw_bus_find_child(node, "lanes"); 955 if (node <= 0) { 956 device_printf(sc->dev, "Cannot find regulators subnode\n"); 957 rv = ENXIO; 958 goto end; 959 } 960 961 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 962 if (!ofw_bus_node_status_okay(node)) 963 continue; 964 965 rv = process_lane(sc, node, pad); 966 if (rv != 0) 967 goto end; 968 } 969 pad->enabled = true; 970 rv = 0; 971 end: 972 if (name != NULL) 973 OF_prop_free(name); 974 return (rv); 975 } 976 977 static int 978 process_port(struct padctl_softc *sc, phandle_t node) 979 { 980 981 struct padctl_port *port; 982 char *name; 983 int rv; 984 985 name = NULL; 986 rv = OF_getprop_alloc(node, "name", (void **)&name); 987 if (rv <= 0) { 988 device_printf(sc->dev, "Cannot read port name.\n"); 989 return (ENXIO); 990 } 991 992 port = search_port(sc, name); 993 if (port == NULL) { 994 device_printf(sc->dev, "Unknown port: %s\n", name); 995 rv = ENXIO; 996 goto end; 997 } 998 999 if (port->type == PADCTL_PORT_USB3) { 1000 rv = OF_getencprop(node, "nvidia,usb2-companion", 1001 &(port->companion), sizeof(port->companion)); 1002 if (rv <= 0) { 1003 device_printf(sc->dev, 1004 "Missing 'nvidia,usb2-companion' property " 1005 "for port: %s\n", name); 1006 rv = ENXIO; 1007 goto end; 1008 } 1009 } 1010 1011 if (OF_hasprop(node, "vbus-supply")) { 1012 rv = regulator_get_by_ofw_property(sc->dev, 0, 1013 "vbus-supply", &port->supply_vbus); 1014 if (rv <= 0) { 1015 device_printf(sc->dev, 1016 "Cannot get 'vbus-supply' regulator " 1017 "for port: %s\n", name); 1018 rv = ENXIO; 1019 goto end; 1020 } 1021 } 1022 1023 if (OF_hasprop(node, "nvidia,internal")) 1024 port->internal = true; 1025 /* Find assigned lane */ 1026 if (port->lane == NULL) { 1027 switch(port->type) { 1028 /* Routing is fixed for USB2, ULPI AND HSIC. */ 1029 case PADCTL_PORT_USB2: 1030 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2, 1031 port->idx); 1032 break; 1033 case PADCTL_PORT_ULPI: 1034 port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI, 1035 port->idx); 1036 break; 1037 case PADCTL_PORT_HSIC: 1038 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC, 1039 port->idx); 1040 break; 1041 case PADCTL_PORT_USB3: 1042 port->lane = search_usb3_pad_lane(sc, port->idx); 1043 break; 1044 } 1045 } 1046 if (port->lane == NULL) { 1047 device_printf(sc->dev, "Cannot find lane for port: %s\n", name); 1048 rv = ENXIO; 1049 goto end; 1050 } 1051 port->enabled = true; 1052 rv = 0; 1053 end: 1054 if (name != NULL) 1055 OF_prop_free(name); 1056 return (rv); 1057 } 1058 1059 static int 1060 parse_fdt(struct padctl_softc *sc, phandle_t base_node) 1061 { 1062 phandle_t node; 1063 int rv; 1064 1065 rv = 0; 1066 node = ofw_bus_find_child(base_node, "pads"); 1067 1068 if (node <= 0) { 1069 device_printf(sc->dev, "Cannot find pads subnode.\n"); 1070 return (ENXIO); 1071 } 1072 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1073 if (!ofw_bus_node_status_okay(node)) 1074 continue; 1075 rv = process_pad(sc, node); 1076 if (rv != 0) 1077 return (rv); 1078 } 1079 1080 node = ofw_bus_find_child(base_node, "ports"); 1081 if (node <= 0) { 1082 device_printf(sc->dev, "Cannot find ports subnode.\n"); 1083 return (ENXIO); 1084 } 1085 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1086 if (!ofw_bus_node_status_okay(node)) 1087 continue; 1088 rv = process_port(sc, node); 1089 if (rv != 0) 1090 return (rv); 1091 } 1092 1093 return (0); 1094 } 1095 1096 static void 1097 load_calibration(struct padctl_softc *sc) 1098 { 1099 uint32_t reg; 1100 1101 /* All XUSB pad calibrations are packed into single dword.*/ 1102 reg = tegra_fuse_read_4(FUSE_XUSB_CALIB); 1103 sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg); 1104 sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg); 1105 sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg); 1106 sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg); 1107 sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg); 1108 } 1109 1110 /* ------------------------------------------------------------------------- 1111 * 1112 * BUS functions 1113 */ 1114 static int 1115 xusbpadctl_probe(device_t dev) 1116 { 1117 1118 if (!ofw_bus_status_okay(dev)) 1119 return (ENXIO); 1120 1121 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 1122 return (ENXIO); 1123 1124 device_set_desc(dev, "Tegra XUSB phy"); 1125 return (BUS_PROBE_DEFAULT); 1126 } 1127 1128 static int 1129 xusbpadctl_detach(device_t dev) 1130 { 1131 1132 /* This device is always present. */ 1133 return (EBUSY); 1134 } 1135 1136 static int 1137 xusbpadctl_attach(device_t dev) 1138 { 1139 struct padctl_softc * sc; 1140 int i, rid, rv; 1141 struct padctl_port *port; 1142 phandle_t node; 1143 1144 sc = device_get_softc(dev); 1145 sc->dev = dev; 1146 node = ofw_bus_get_node(dev); 1147 1148 rid = 0; 1149 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1150 RF_ACTIVE); 1151 if (sc->mem_res == NULL) { 1152 device_printf(dev, "Cannot allocate memory resources\n"); 1153 return (ENXIO); 1154 } 1155 1156 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst); 1157 if (rv != 0) { 1158 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv); 1159 return (rv); 1160 } 1161 rv = hwreset_deassert(sc->rst); 1162 if (rv != 0) { 1163 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv); 1164 return (rv); 1165 } 1166 1167 load_calibration(sc); 1168 1169 rv = parse_fdt(sc, node); 1170 if (rv != 0) { 1171 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv); 1172 return (rv); 1173 } 1174 for (i = 0; i < nitems(ports_tbl); i++) { 1175 port = ports_tbl + i; 1176 if (!port->enabled) 1177 continue; 1178 if (port->init == NULL) 1179 continue; 1180 rv = port->init(sc, port); 1181 if (rv != 0) { 1182 device_printf(dev, "Cannot init port '%s'\n", 1183 port->name); 1184 return (rv); 1185 } 1186 } 1187 return (0); 1188 } 1189 1190 static device_method_t tegra_xusbpadctl_methods[] = { 1191 /* Device interface */ 1192 DEVMETHOD(device_probe, xusbpadctl_probe), 1193 DEVMETHOD(device_attach, xusbpadctl_attach), 1194 DEVMETHOD(device_detach, xusbpadctl_detach), 1195 1196 DEVMETHOD_END 1197 }; 1198 1199 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver, 1200 tegra_xusbpadctl_methods, sizeof(struct padctl_softc)); 1201 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver, 1202 NULL, NULL, 73); 1203