1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/malloc.h> 34 #include <sys/rman.h> 35 36 #include <machine/bus.h> 37 #include <machine/fdt.h> 38 39 #include <dev/extres/hwreset/hwreset.h> 40 #include <dev/extres/phy/phy.h> 41 #include <dev/extres/regulator/regulator.h> 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/fdt/fdt_pinctrl.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <arm/nvidia/tegra_efuse.h> 49 50 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 51 52 #include "phydev_if.h" 53 54 /* FUSE calibration data. */ 55 #define FUSE_XUSB_CALIB 0x0F0 56 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(x) (((x) >> 15) & 0x3F); 57 #define FUSE_XUSB_CALIB_HS_IREF_CAP(x) (((x) >> 13) & 0x03); 58 #define FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(x) (((x) >> 11) & 0x03); 59 #define FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F); 60 #define FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F); 61 62 /* Registers. */ 63 #define XUSB_PADCTL_USB2_PAD_MUX 0x004 64 65 #define XUSB_PADCTL_USB2_PORT_CAP 0x008 66 #define USB2_PORT_CAP_ULPI_PORT_INTERNAL (1 << 25) 67 #define USB2_PORT_CAP_ULPI_PORT_CAP (1 << 24) 68 #define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4)) 69 #define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4)) 70 #define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4)) 71 #define USB2_PORT_CAP_PORT_CAP_OTG 0x3 72 #define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2 73 #define USB2_PORT_CAP_PORT_CAP_HOST 0x1 74 #define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0 75 76 #define XUSB_PADCTL_SS_PORT_MAP 0x014 77 #define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4)) 78 #define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4)) 79 80 #define XUSB_PADCTL_ELPG_PROGRAM 0x01C 81 #define ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) 82 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) 83 #define ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) 84 #define ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4)) 85 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (17 + (x) * 4)) 86 #define ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4)) 87 88 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 89 #define IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) 90 #define IOPHY_PLL_P0_CTL1_REFCLK_SEL(x) (((x) & 0xF) << 12) 91 #define IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) 92 93 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 94 #define IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) 95 #define IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) 96 #define IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) 97 98 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(x) (0x058 + (x) * 4) 99 #define IOPHY_USB3_PAD_CTL2_CDR_CNTL(x) (((x) & 0x00FF) << 4) 100 #define IOPHY_USB3_PAD_CTL2_RX_EQ(x) (((x) & 0xFFFF) << 8) 101 #define IOPHY_USB3_PAD_CTL2_RX_WANDER(x) (((x) & 0x000F) << 4) 102 #define IOPHY_USB3_PAD_CTL2_RX_TERM_CNTL(x) (((x) & 0x0003) << 2) 103 #define IOPHY_USB3_PAD_CTL2_TX_TERM_CNTL(x) (((x) & 0x0003) << 0) 104 105 #define XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(x) (0x068 + (x) * 4) 106 107 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x0A0 + (x) * 4) 108 #define USB2_OTG_PAD_CTL0_LSBIAS_SEL (1 << 23) 109 #define USB2_OTG_PAD_CTL0_DISCON_DETECT_METHOD (1 << 22) 110 #define USB2_OTG_PAD_CTL0_PD_ZI (1 << 21) 111 #define USB2_OTG_PAD_CTL0_PD2 (1 << 20) 112 #define USB2_OTG_PAD_CTL0_PD (1 << 19) 113 #define USB2_OTG_PAD_CTL0_TERM_EN (1 << 18) 114 #define USB2_OTG_PAD_CTL0_LS_LS_FSLEW(x) (((x) & 0x03) << 16) 115 #define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x03) << 14) 116 #define USB2_OTG_PAD_CTL0_FS_SLEW(x) (((x) & 0x03) << 12) 117 #define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6) 118 #define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0) 119 120 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x0AC + (x) * 4) 121 #define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x3) << 11) 122 #define USB2_OTG_PAD_CTL1_HS_IREF_CAP(x) (((x) & 0x3) << 9) 123 #define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x3) << 7) 124 #define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0xF) << 3) 125 #define USB2_OTG_PAD_CTL1_PD_DR (1 << 2) 126 #define USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP (1 << 1) 127 #define USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP (1 << 0) 128 129 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0B8 130 #define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 14) 131 #define USB2_BIAS_PAD_CTL0_PD_TRK (1 << 13) 132 #define USB2_BIAS_PAD_CTL0_PD (1 << 12) 133 #define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x3) << 9) 134 #define USB2_BIAS_PAD_CTL0_VBUS_LEVEL(x) (((x) & 0x3) << 7) 135 #define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 5) 136 #define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 2) 137 #define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x3) << 0) 138 139 #define XUSB_PADCTL_HSIC_PAD0_CTL0 0x0C8 140 #define HSIC_PAD0_CTL0_HSIC_OPT(x) (((x) & 0xF) << 16) 141 #define HSIC_PAD0_CTL0_TX_SLEWN(x) (((x) & 0xF) << 12) 142 #define HSIC_PAD0_CTL0_TX_SLEWP(x) (((x) & 0xF) << 8) 143 #define HSIC_PAD0_CTL0_TX_RTUNEN(x) (((x) & 0xF) << 4) 144 #define HSIC_PAD0_CTL0_TX_RTUNEP(x) (((x) & 0xF) << 0) 145 146 #define XUSB_PADCTL_USB3_PAD_MUX 0x134 147 #define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x))) 148 #define USB3_PAD_MUX_SATA_IDDQ_DISABLE (1 << 6) 149 150 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 151 #define IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) 152 #define IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) 153 #define IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) 154 #define IOPHY_PLL_S0_CTL1_PLL_RST_L (1 << 1) 155 #define IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) 156 157 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL2 0x13C 158 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL3 0x140 159 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL4 0x144 160 161 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 162 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) 163 #define IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) 164 165 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL2 0x14C 166 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL3 0x150 167 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL4 0x154 168 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL5 0x158 169 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL6 0x15C 170 171 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 172 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 173 174 struct padctl_softc { 175 device_t dev; 176 struct resource *mem_res; 177 hwreset_t rst; 178 int phy_ena_cnt; 179 180 /* Fuses calibration data */ 181 uint32_t hs_curr_level_0; 182 uint32_t hs_curr_level_123; 183 uint32_t hs_iref_cap; 184 uint32_t hs_term_range_adj; 185 uint32_t hs_squelch_level; 186 187 uint32_t hs_curr_level_offset; 188 }; 189 190 static struct ofw_compat_data compat_data[] = { 191 {"nvidia,tegra124-xusb-padctl", 1}, 192 {NULL, 0}, 193 }; 194 195 /* Ports. */ 196 enum padctl_port_type { 197 PADCTL_PORT_USB2, 198 PADCTL_PORT_ULPI, 199 PADCTL_PORT_HSIC, 200 PADCTL_PORT_USB3, 201 }; 202 203 struct padctl_lane; 204 struct padctl_port { 205 enum padctl_port_type type; 206 const char *name; 207 const char *base_name; 208 int idx; 209 int (*init)(struct padctl_softc *sc, 210 struct padctl_port *port); 211 212 /* Runtime data. */ 213 bool enabled; 214 regulator_t supply_vbus; /* USB2, USB3 */ 215 bool internal; /* ULPI, USB2, USB3 */ 216 uint32_t companion; /* USB3 */ 217 struct padctl_lane *lane; 218 }; 219 220 static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port); 221 222 #define PORT(t, n, p, i) { \ 223 .type = t, \ 224 .name = n "-" #p, \ 225 .base_name = n, \ 226 .idx = p, \ 227 .init = i, \ 228 } 229 static struct padctl_port ports_tbl[] = { 230 PORT(PADCTL_PORT_USB2, "usb2", 0, NULL), 231 PORT(PADCTL_PORT_USB2, "usb2", 1, NULL), 232 PORT(PADCTL_PORT_USB2, "usb2", 2, NULL), 233 PORT(PADCTL_PORT_ULPI, "ulpi", 0, NULL), 234 PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL), 235 PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL), 236 PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init), 237 PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init), 238 }; 239 240 /* Pads - a group of lannes. */ 241 enum padctl_pad_type { 242 PADCTL_PAD_USB2, 243 PADCTL_PAD_ULPI, 244 PADCTL_PAD_HSIC, 245 PADCTL_PAD_PCIE, 246 PADCTL_PAD_SATA, 247 }; 248 249 struct padctl_lane; 250 struct padctl_pad { 251 const char *name; 252 enum padctl_pad_type type; 253 int (*powerup)(struct padctl_softc *sc, 254 struct padctl_lane *lane); 255 int (*powerdown)(struct padctl_softc *sc, 256 struct padctl_lane *lane); 257 /* Runtime data. */ 258 bool enabled; 259 struct padctl_lane *lanes[8]; /* Safe maximum value. */ 260 int nlanes; 261 }; 262 263 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 264 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 265 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 266 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 267 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane); 268 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane); 269 270 #define PAD(n, t, u, d) { \ 271 .name = n, \ 272 .type = t, \ 273 .powerup = u, \ 274 .powerdown = d, \ 275 } 276 static struct padctl_pad pads_tbl[] = { 277 PAD("usb2", PADCTL_PAD_USB2, usb2_powerup, usb2_powerdown), 278 PAD("ulpi", PADCTL_PAD_ULPI, NULL, NULL), 279 PAD("hsic", PADCTL_PAD_HSIC, NULL, NULL), 280 PAD("pcie", PADCTL_PAD_PCIE, pcie_powerup, pcie_powerdown), 281 PAD("sata", PADCTL_PAD_SATA, sata_powerup, sata_powerdown), 282 }; 283 284 /* Lanes. */ 285 static char *otg_mux[] = {"snps", "xusb", "uart", "rsvd"}; 286 static char *usb_mux[] = {"snps", "xusb"}; 287 static char *pci_mux[] = {"pcie", "usb3-ss", "sata", "rsvd"}; 288 289 struct padctl_lane { 290 const char *name; 291 int idx; 292 bus_size_t reg; 293 uint32_t shift; 294 uint32_t mask; 295 char **mux; 296 int nmux; 297 /* Runtime data. */ 298 bool enabled; 299 struct padctl_pad *pad; 300 struct padctl_port *port; 301 int mux_idx; 302 303 }; 304 305 #define LANE(n, p, r, s, m, mx) { \ 306 .name = n "-" #p, \ 307 .idx = p, \ 308 .reg = r, \ 309 .shift = s, \ 310 .mask = m, \ 311 .mux = mx, \ 312 .nmux = nitems(mx), \ 313 } 314 static struct padctl_lane lanes_tbl[] = { 315 LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, otg_mux), 316 LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, otg_mux), 317 LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, otg_mux), 318 LANE("ulpi", 0, XUSB_PADCTL_USB2_PAD_MUX, 12, 0x1, usb_mux), 319 LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, usb_mux), 320 LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, usb_mux), 321 LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux), 322 LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux), 323 LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux), 324 LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux), 325 LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux), 326 LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 26, 0x3, pci_mux), 327 }; 328 329 /* Define all possible mappings for USB3 port lanes */ 330 struct padctl_lane_map { 331 int port_idx; 332 enum padctl_pad_type pad_type; 333 int lane_idx; 334 }; 335 336 #define LANE_MAP(pi, pt, li) { \ 337 .port_idx = pi, \ 338 .pad_type = pt, \ 339 .lane_idx = li, \ 340 } 341 static struct padctl_lane_map lane_map_tbl[] = { 342 LANE_MAP(0, PADCTL_PAD_PCIE, 0), /* port USB3-0 -> lane PCIE-0 */ 343 LANE_MAP(1, PADCTL_PAD_PCIE, 1), /* port USB3-1 -> lane PCIE-1 */ 344 /* -- or -- */ 345 LANE_MAP(1, PADCTL_PAD_SATA, 0), /* port USB3-1 -> lane SATA-0 */ 346 }; 347 348 /* Phy class and methods. */ 349 static int xusbpadctl_phy_enable(struct phynode *phy, bool enable); 350 static phynode_method_t xusbpadctl_phynode_methods[] = { 351 PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable), 352 PHYNODEMETHOD_END 353 354 }; 355 DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class, 356 xusbpadctl_phynode_methods, 0, phynode_class); 357 358 static struct padctl_port *search_lane_port(struct padctl_softc *sc, 359 struct padctl_lane *lane); 360 /* ------------------------------------------------------------------------- 361 * 362 * PHY functions 363 */ 364 static int 365 usb3_port_init(struct padctl_softc *sc, struct padctl_port *port) 366 { 367 uint32_t reg; 368 369 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); 370 if (port->internal) 371 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); 372 else 373 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); 374 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); 375 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); 376 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 377 378 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); 379 reg &= ~IOPHY_USB3_PAD_CTL2_CDR_CNTL(~0); 380 reg &= ~IOPHY_USB3_PAD_CTL2_RX_EQ(~0); 381 reg &= ~IOPHY_USB3_PAD_CTL2_RX_WANDER(~0); 382 reg |= IOPHY_USB3_PAD_CTL2_CDR_CNTL(0x24); 383 reg |= IOPHY_USB3_PAD_CTL2_RX_EQ(0xF070); 384 reg |= IOPHY_USB3_PAD_CTL2_RX_WANDER(0xF); 385 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); 386 387 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), 388 0x002008EE); 389 390 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 391 reg &= ~ELPG_PROGRAM_SSP_ELPG_VCORE_DOWN(port->idx); 392 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 393 DELAY(100); 394 395 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 396 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN_EARLY(port->idx); 397 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 398 DELAY(100); 399 400 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 401 reg &= ~ELPG_PROGRAM_SSP_ELPG_CLAMP_EN(port->idx); 402 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 403 DELAY(100); 404 405 return (0); 406 } 407 408 static int 409 pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 410 { 411 uint32_t reg; 412 int i; 413 414 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 415 reg &= ~IOPHY_PLL_P0_CTL1_REFCLK_SEL(~0); 416 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 417 DELAY(100); 418 419 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); 420 reg |= IOPHY_PLL_P0_CTL2_REFCLKBUF_EN; 421 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_EN; 422 reg |= IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; 423 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); 424 DELAY(100); 425 426 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 427 reg |= IOPHY_PLL_P0_CTL1_PLL_RST; 428 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 429 DELAY(100); 430 431 for (i = 100; i > 0; i--) { 432 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 433 if (reg & IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) 434 break; 435 DELAY(10); 436 } 437 if (i <= 0) { 438 device_printf(sc->dev, "Failed to power up PCIe phy\n"); 439 return (ETIMEDOUT); 440 } 441 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 442 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 443 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 444 445 return (0); 446 } 447 448 static int 449 pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 450 { 451 uint32_t reg; 452 453 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 454 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); 455 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 456 457 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); 458 reg &= ~IOPHY_PLL_P0_CTL1_PLL_RST; 459 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 460 DELAY(100); 461 462 return (0); 463 464 } 465 466 static int 467 sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 468 { 469 uint32_t reg; 470 int i; 471 472 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 473 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 474 reg &= ~IOPHY_MISC_PAD_S0_CTL1_IDDQ; 475 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 476 477 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 478 reg &= ~IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 479 reg &= ~IOPHY_PLL_S0_CTL1_PLL_IDDQ; 480 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 481 482 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 483 reg |= IOPHY_PLL_S0_CTL1_PLL1_MODE; 484 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 485 486 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 487 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 488 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 489 490 for (i = 100; i >= 0; i--) { 491 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 492 if (reg & IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 493 break; 494 DELAY(100); 495 } 496 if (i <= 0) { 497 device_printf(sc->dev, "Failed to power up SATA phy\n"); 498 return (ETIMEDOUT); 499 } 500 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 501 reg |= IOPHY_PLL_S0_CTL1_PLL_RST_L; 502 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 503 504 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 505 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE; 506 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 507 508 return (0); 509 } 510 511 static int 512 sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 513 { 514 uint32_t reg; 515 516 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); 517 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE; 518 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); 519 520 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 521 reg &= ~IOPHY_PLL_S0_CTL1_PLL_RST_L; 522 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 523 DELAY(100); 524 525 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 526 reg &= ~IOPHY_PLL_S0_CTL1_PLL1_MODE; 527 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 528 DELAY(100); 529 530 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); 531 reg |= IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; 532 reg |= IOPHY_PLL_S0_CTL1_PLL_IDDQ; 533 WR4(sc, XUSB_PADCTL_IOPHY_PLL_S0_CTL1, reg); 534 DELAY(100); 535 536 reg = RD4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); 537 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; 538 reg |= IOPHY_MISC_PAD_S0_CTL1_IDDQ; 539 WR4(sc, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1, reg); 540 DELAY(100); 541 542 return (0); 543 } 544 545 static int 546 usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane) 547 { 548 uint32_t reg; 549 struct padctl_port *port; 550 int rv; 551 552 port = search_lane_port(sc, lane); 553 if (port == NULL) { 554 device_printf(sc->dev, "Cannot find port for lane: %s\n", 555 lane->name); 556 } 557 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 558 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0); 559 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0); 560 reg |= USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(sc->hs_squelch_level); 561 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(5); 562 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 563 564 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); 565 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); 566 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); 567 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); 568 569 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); 570 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0); 571 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0); 572 reg &= ~USB2_OTG_PAD_CTL0_LS_RSLEW(~0); 573 reg &= ~USB2_OTG_PAD_CTL0_PD; 574 reg &= ~USB2_OTG_PAD_CTL0_PD2; 575 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI; 576 577 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14); 578 if (lane->idx == 0) { 579 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_0); 580 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(3); 581 } else { 582 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level_123); 583 reg |= USB2_OTG_PAD_CTL0_LS_RSLEW(0); 584 } 585 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); 586 587 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); 588 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0); 589 reg &= ~USB2_OTG_PAD_CTL1_HS_IREF_CAP(~0); 590 reg &= ~USB2_OTG_PAD_CTL1_PD_DR; 591 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP; 592 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP; 593 594 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); 595 reg |= USB2_OTG_PAD_CTL1_HS_IREF_CAP(sc->hs_iref_cap); 596 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); 597 598 if (port != NULL && port->supply_vbus != NULL) { 599 rv = regulator_enable(port->supply_vbus); 600 if (rv != 0) { 601 device_printf(sc->dev, 602 "Cannot enable vbus regulator\n"); 603 return (rv); 604 } 605 } 606 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 607 reg &= ~USB2_BIAS_PAD_CTL0_PD; 608 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 609 610 return (0); 611 } 612 613 static int 614 usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane) 615 { 616 uint32_t reg; 617 struct padctl_port *port; 618 int rv; 619 620 port = search_lane_port(sc, lane); 621 if (port == NULL) { 622 device_printf(sc->dev, "Cannot find port for lane: %s\n", 623 lane->name); 624 } 625 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); 626 reg |= USB2_BIAS_PAD_CTL0_PD; 627 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); 628 629 if (port != NULL && port->supply_vbus != NULL) { 630 rv = regulator_enable(port->supply_vbus); 631 if (rv != 0) { 632 device_printf(sc->dev, 633 "Cannot disable vbus regulator\n"); 634 return (rv); 635 } 636 } 637 return (0); 638 } 639 640 static int 641 phy_powerup(struct padctl_softc *sc) 642 { 643 uint32_t reg; 644 645 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 646 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 647 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 648 DELAY(100); 649 650 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 651 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 652 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 653 DELAY(100); 654 655 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 656 reg &= ~ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 657 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 658 DELAY(100); 659 660 return (0); 661 } 662 663 static int 664 phy_powerdown(struct padctl_softc *sc) 665 { 666 uint32_t reg; 667 668 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 669 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; 670 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 671 DELAY(100); 672 673 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 674 reg |= ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; 675 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 676 DELAY(100); 677 678 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); 679 reg |= ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; 680 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 681 DELAY(100); 682 683 return (0); 684 } 685 686 static int 687 xusbpadctl_phy_enable(struct phynode *phy, bool enable) 688 { 689 device_t dev; 690 intptr_t id; 691 struct padctl_softc *sc; 692 struct padctl_lane *lane; 693 struct padctl_pad *pad; 694 int rv; 695 696 dev = phynode_get_device(phy); 697 id = phynode_get_id(phy); 698 sc = device_get_softc(dev); 699 700 if (id < 0 || id >= nitems(lanes_tbl)) { 701 device_printf(dev, "Unknown phy: %d\n", id); 702 return (ENXIO); 703 } 704 lane = lanes_tbl + id; 705 if (!lane->enabled) { 706 device_printf(dev, "Lane is not enabled/configured: %s\n", 707 lane->name); 708 return (ENXIO); 709 } 710 pad = lane->pad; 711 if (enable) { 712 if (sc->phy_ena_cnt == 0) { 713 rv = phy_powerup(sc); 714 if (rv != 0) 715 return (rv); 716 } 717 sc->phy_ena_cnt++; 718 } 719 720 if (enable) 721 rv = pad->powerup(sc, lane); 722 else 723 rv = pad->powerdown(sc, lane); 724 if (rv != 0) 725 return (rv); 726 727 if (!enable) { 728 if (sc->phy_ena_cnt == 1) { 729 rv = phy_powerdown(sc); 730 if (rv != 0) 731 return (rv); 732 } 733 sc->phy_ena_cnt--; 734 } 735 736 return (0); 737 } 738 739 /* ------------------------------------------------------------------------- 740 * 741 * FDT processing 742 */ 743 static struct padctl_port * 744 search_port(struct padctl_softc *sc, char *port_name) 745 { 746 int i; 747 748 for (i = 0; i < nitems(ports_tbl); i++) { 749 if (strcmp(port_name, ports_tbl[i].name) == 0) 750 return (&ports_tbl[i]); 751 } 752 return (NULL); 753 } 754 755 static struct padctl_port * 756 search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane) 757 { 758 int i; 759 760 for (i = 0; i < nitems(ports_tbl); i++) { 761 if (!ports_tbl[i].enabled) 762 continue; 763 if (ports_tbl[i].lane == lane) 764 return (ports_tbl + i); 765 } 766 return (NULL); 767 } 768 769 static struct padctl_lane * 770 search_lane(struct padctl_softc *sc, char *lane_name) 771 { 772 int i; 773 774 for (i = 0; i < nitems(lanes_tbl); i++) { 775 if (strcmp(lane_name, lanes_tbl[i].name) == 0) 776 return (lanes_tbl + i); 777 } 778 return (NULL); 779 } 780 781 static struct padctl_lane * 782 search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx) 783 { 784 int i; 785 786 for (i = 0; i < nitems(lanes_tbl); i++) { 787 if (!lanes_tbl[i].enabled) 788 continue; 789 if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx) 790 return (lanes_tbl + i); 791 } 792 return (NULL); 793 } 794 795 static struct padctl_lane * 796 search_usb3_pad_lane(struct padctl_softc *sc, int idx) 797 { 798 int i; 799 struct padctl_lane *lane, *tmp; 800 801 lane = NULL; 802 for (i = 0; i < nitems(lane_map_tbl); i++) { 803 if (idx != lane_map_tbl[i].port_idx) 804 continue; 805 tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type, 806 lane_map_tbl[i].lane_idx); 807 if (tmp == NULL) 808 continue; 809 if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0) 810 continue; 811 if (lane != NULL) { 812 device_printf(sc->dev, "Duplicated mappings found for" 813 " lanes: %s and %s\n", lane->name, tmp->name); 814 return (NULL); 815 } 816 lane = tmp; 817 } 818 return (lane); 819 } 820 821 static struct padctl_pad * 822 search_pad(struct padctl_softc *sc, char *pad_name) 823 { 824 int i; 825 826 for (i = 0; i < nitems(pads_tbl); i++) { 827 if (strcmp(pad_name, pads_tbl[i].name) == 0) 828 return (pads_tbl + i); 829 } 830 return (NULL); 831 } 832 833 static int 834 search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name) 835 { 836 int i; 837 838 for (i = 0; i < lane->nmux; i++) { 839 if (strcmp(fnc_name, lane->mux[i]) == 0) 840 return (i); 841 } 842 return (-1); 843 } 844 845 static int 846 config_lane(struct padctl_softc *sc, struct padctl_lane *lane) 847 { 848 uint32_t reg; 849 850 reg = RD4(sc, lane->reg); 851 reg &= ~(lane->mask << lane->shift); 852 reg |= (lane->mux_idx & lane->mask) << lane->shift; 853 WR4(sc, lane->reg, reg); 854 return (0); 855 } 856 857 static int 858 process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad) 859 { 860 struct padctl_lane *lane; 861 struct phynode *phynode; 862 struct phynode_init_def phy_init; 863 char *name; 864 char *function; 865 int rv; 866 867 name = NULL; 868 function = NULL; 869 rv = OF_getprop_alloc(node, "name", (void **)&name); 870 if (rv <= 0) { 871 device_printf(sc->dev, "Cannot read lane name.\n"); 872 return (ENXIO); 873 } 874 875 lane = search_lane(sc, name); 876 if (lane == NULL) { 877 device_printf(sc->dev, "Unknown lane: %s\n", name); 878 rv = ENXIO; 879 goto end; 880 } 881 882 /* Read function (mux) settings. */ 883 rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function); 884 if (rv <= 0) { 885 device_printf(sc->dev, "Cannot read lane function.\n"); 886 rv = ENXIO; 887 goto end; 888 } 889 890 lane->mux_idx = search_mux(sc, lane, function); 891 if (lane->mux_idx == ~0) { 892 device_printf(sc->dev, "Unknown function %s for lane %s\n", 893 function, name); 894 rv = ENXIO; 895 goto end; 896 } 897 898 rv = config_lane(sc, lane); 899 if (rv != 0) { 900 device_printf(sc->dev, "Cannot configure lane: %s: %d\n", 901 name, rv); 902 rv = ENXIO; 903 goto end; 904 } 905 lane->pad = pad; 906 lane->enabled = true; 907 pad->lanes[pad->nlanes++] = lane; 908 909 /* Create and register phy. */ 910 bzero(&phy_init, sizeof(phy_init)); 911 phy_init.id = lane - lanes_tbl; 912 phy_init.ofw_node = node; 913 phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init); 914 if (phynode == NULL) { 915 device_printf(sc->dev, "Cannot create phy\n"); 916 rv = ENXIO; 917 goto end; 918 } 919 if (phynode_register(phynode) == NULL) { 920 device_printf(sc->dev, "Cannot create phy\n"); 921 return (ENXIO); 922 } 923 924 rv = 0; 925 926 end: 927 if (name != NULL) 928 OF_prop_free(name); 929 if (function != NULL) 930 OF_prop_free(function); 931 return (rv); 932 } 933 934 static int 935 process_pad(struct padctl_softc *sc, phandle_t node) 936 { 937 struct padctl_pad *pad; 938 char *name; 939 int rv; 940 941 name = NULL; 942 rv = OF_getprop_alloc(node, "name", (void **)&name); 943 if (rv <= 0) { 944 device_printf(sc->dev, "Cannot read pad name.\n"); 945 return (ENXIO); 946 } 947 pad = search_pad(sc, name); 948 if (pad == NULL) { 949 device_printf(sc->dev, "Unknown pad: %s\n", name); 950 rv = ENXIO; 951 goto end; 952 } 953 954 /* Read and process associated lanes. */ 955 node = ofw_bus_find_child(node, "lanes"); 956 if (node <= 0) { 957 device_printf(sc->dev, "Cannot find regulators subnode\n"); 958 rv = ENXIO; 959 goto end; 960 } 961 962 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 963 if (!ofw_bus_node_status_okay(node)) 964 continue; 965 966 rv = process_lane(sc, node, pad); 967 if (rv != 0) 968 goto end; 969 } 970 pad->enabled = true; 971 rv = 0; 972 end: 973 if (name != NULL) 974 OF_prop_free(name); 975 return (rv); 976 } 977 978 static int 979 process_port(struct padctl_softc *sc, phandle_t node) 980 { 981 982 struct padctl_port *port; 983 char *name; 984 int rv; 985 986 name = NULL; 987 rv = OF_getprop_alloc(node, "name", (void **)&name); 988 if (rv <= 0) { 989 device_printf(sc->dev, "Cannot read port name.\n"); 990 return (ENXIO); 991 } 992 993 port = search_port(sc, name); 994 if (port == NULL) { 995 device_printf(sc->dev, "Unknown port: %s\n", name); 996 rv = ENXIO; 997 goto end; 998 } 999 1000 if (port->type == PADCTL_PORT_USB3) { 1001 rv = OF_getencprop(node, "nvidia,usb2-companion", 1002 &(port->companion), sizeof(port->companion)); 1003 if (rv <= 0) { 1004 device_printf(sc->dev, 1005 "Missing 'nvidia,usb2-companion' property " 1006 "for port: %s\n", name); 1007 rv = ENXIO; 1008 goto end; 1009 } 1010 } 1011 1012 if (OF_hasprop(node, "vbus-supply")) { 1013 rv = regulator_get_by_ofw_property(sc->dev, 0, 1014 "vbus-supply", &port->supply_vbus); 1015 if (rv <= 0) { 1016 device_printf(sc->dev, 1017 "Cannot get 'vbus-supply' regulator " 1018 "for port: %s\n", name); 1019 rv = ENXIO; 1020 goto end; 1021 } 1022 } 1023 1024 if (OF_hasprop(node, "nvidia,internal")) 1025 port->internal = true; 1026 /* Find assigned lane */ 1027 if (port->lane == NULL) { 1028 switch(port->type) { 1029 /* Routing is fixed for USB2, ULPI AND HSIC. */ 1030 case PADCTL_PORT_USB2: 1031 port->lane = search_pad_lane(sc, PADCTL_PAD_USB2, 1032 port->idx); 1033 break; 1034 case PADCTL_PORT_ULPI: 1035 port->lane = search_pad_lane(sc, PADCTL_PAD_ULPI, 1036 port->idx); 1037 break; 1038 case PADCTL_PORT_HSIC: 1039 port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC, 1040 port->idx); 1041 break; 1042 case PADCTL_PORT_USB3: 1043 port->lane = search_usb3_pad_lane(sc, port->idx); 1044 break; 1045 } 1046 } 1047 if (port->lane == NULL) { 1048 device_printf(sc->dev, "Cannot find lane for port: %s\n", name); 1049 rv = ENXIO; 1050 goto end; 1051 } 1052 port->enabled = true; 1053 rv = 0; 1054 end: 1055 if (name != NULL) 1056 OF_prop_free(name); 1057 return (rv); 1058 } 1059 1060 static int 1061 parse_fdt(struct padctl_softc *sc, phandle_t base_node) 1062 { 1063 phandle_t node; 1064 int rv; 1065 1066 rv = 0; 1067 node = ofw_bus_find_child(base_node, "pads"); 1068 1069 if (node <= 0) { 1070 device_printf(sc->dev, "Cannot find pads subnode.\n"); 1071 return (ENXIO); 1072 } 1073 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1074 if (!ofw_bus_node_status_okay(node)) 1075 continue; 1076 rv = process_pad(sc, node); 1077 if (rv != 0) 1078 return (rv); 1079 } 1080 1081 node = ofw_bus_find_child(base_node, "ports"); 1082 if (node <= 0) { 1083 device_printf(sc->dev, "Cannot find ports subnode.\n"); 1084 return (ENXIO); 1085 } 1086 for (node = OF_child(node); node != 0; node = OF_peer(node)) { 1087 if (!ofw_bus_node_status_okay(node)) 1088 continue; 1089 rv = process_port(sc, node); 1090 if (rv != 0) 1091 return (rv); 1092 } 1093 1094 return (0); 1095 } 1096 1097 static void 1098 load_calibration(struct padctl_softc *sc) 1099 { 1100 uint32_t reg; 1101 1102 /* All XUSB pad calibrations are packed into single dword.*/ 1103 reg = tegra_fuse_read_4(FUSE_XUSB_CALIB); 1104 sc->hs_curr_level_0 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_0(reg); 1105 sc->hs_curr_level_123 = FUSE_XUSB_CALIB_HS_CURR_LEVEL_123(reg); 1106 sc->hs_iref_cap = FUSE_XUSB_CALIB_HS_IREF_CAP(reg); 1107 sc->hs_squelch_level = FUSE_XUSB_CALIB_HS_SQUELCH_LEVEL(reg); 1108 sc->hs_term_range_adj = FUSE_XUSB_CALIB_HS_TERM_RANGE_ADJ(reg); 1109 } 1110 1111 /* ------------------------------------------------------------------------- 1112 * 1113 * BUS functions 1114 */ 1115 static int 1116 xusbpadctl_probe(device_t dev) 1117 { 1118 1119 if (!ofw_bus_status_okay(dev)) 1120 return (ENXIO); 1121 1122 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 1123 return (ENXIO); 1124 1125 device_set_desc(dev, "Tegra XUSB phy"); 1126 return (BUS_PROBE_DEFAULT); 1127 } 1128 1129 static int 1130 xusbpadctl_detach(device_t dev) 1131 { 1132 1133 /* This device is always present. */ 1134 return (EBUSY); 1135 } 1136 1137 static int 1138 xusbpadctl_attach(device_t dev) 1139 { 1140 struct padctl_softc * sc; 1141 int i, rid, rv; 1142 struct padctl_port *port; 1143 phandle_t node; 1144 1145 sc = device_get_softc(dev); 1146 sc->dev = dev; 1147 node = ofw_bus_get_node(dev); 1148 1149 rid = 0; 1150 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1151 RF_ACTIVE); 1152 if (sc->mem_res == NULL) { 1153 device_printf(dev, "Cannot allocate memory resources\n"); 1154 return (ENXIO); 1155 } 1156 1157 rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst); 1158 if (rv != 0) { 1159 device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv); 1160 return (rv); 1161 } 1162 rv = hwreset_deassert(sc->rst); 1163 if (rv != 0) { 1164 device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv); 1165 return (rv); 1166 } 1167 1168 load_calibration(sc); 1169 1170 rv = parse_fdt(sc, node); 1171 if (rv != 0) { 1172 device_printf(dev, "Cannot parse fdt configuration: %d\n", rv); 1173 return (rv); 1174 } 1175 for (i = 0; i < nitems(ports_tbl); i++) { 1176 port = ports_tbl + i; 1177 if (!port->enabled) 1178 continue; 1179 if (port->init == NULL) 1180 continue; 1181 rv = port->init(sc, port); 1182 if (rv != 0) { 1183 device_printf(dev, "Cannot init port '%s'\n", 1184 port->name); 1185 return (rv); 1186 } 1187 } 1188 return (0); 1189 } 1190 1191 static device_method_t tegra_xusbpadctl_methods[] = { 1192 /* Device interface */ 1193 DEVMETHOD(device_probe, xusbpadctl_probe), 1194 DEVMETHOD(device_attach, xusbpadctl_attach), 1195 DEVMETHOD(device_detach, xusbpadctl_detach), 1196 1197 DEVMETHOD_END 1198 }; 1199 1200 static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver, 1201 tegra_xusbpadctl_methods, sizeof(struct padctl_softc)); 1202 EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver, 1203 NULL, NULL, 73); 1204