xref: /freebsd/sys/arm/nvidia/tegra124/tegra124_machdep.c (revision 92fa5c23d98675c7ab9e360a9bcd616bc60c71f8)
1ef2ee5d0SMichal Meloun /*-
2ef2ee5d0SMichal Meloun  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3ef2ee5d0SMichal Meloun  * All rights reserved.
4ef2ee5d0SMichal Meloun  *
5ef2ee5d0SMichal Meloun  * Redistribution and use in source and binary forms, with or without
6ef2ee5d0SMichal Meloun  * modification, are permitted provided that the following conditions
7ef2ee5d0SMichal Meloun  * are met:
8ef2ee5d0SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
9ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
10ef2ee5d0SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
11ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
12ef2ee5d0SMichal Meloun  *    documentation and/or other materials provided with the distribution.
13ef2ee5d0SMichal Meloun  *
14ef2ee5d0SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15ef2ee5d0SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16ef2ee5d0SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17ef2ee5d0SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18ef2ee5d0SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19ef2ee5d0SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20ef2ee5d0SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21ef2ee5d0SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22ef2ee5d0SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23ef2ee5d0SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24ef2ee5d0SMichal Meloun  * SUCH DAMAGE.
25ef2ee5d0SMichal Meloun  */
26ef2ee5d0SMichal Meloun 
27ef2ee5d0SMichal Meloun #include "opt_platform.h"
28ef2ee5d0SMichal Meloun 
29ef2ee5d0SMichal Meloun #include <sys/cdefs.h>
30ef2ee5d0SMichal Meloun __FBSDID("$FreeBSD$");
31ef2ee5d0SMichal Meloun 
32ef2ee5d0SMichal Meloun #include <sys/param.h>
33ef2ee5d0SMichal Meloun #include <sys/systm.h>
34ef2ee5d0SMichal Meloun #include <sys/bus.h>
35ef2ee5d0SMichal Meloun #include <sys/reboot.h>
3630b72b68SRuslan Bukin #include <sys/devmap.h>
37ef2ee5d0SMichal Meloun 
38ef2ee5d0SMichal Meloun #include <vm/vm.h>
39ef2ee5d0SMichal Meloun 
40ef2ee5d0SMichal Meloun #include <machine/bus.h>
41ef2ee5d0SMichal Meloun #include <machine/fdt.h>
42ef2ee5d0SMichal Meloun #include <machine/intr.h>
43ef2ee5d0SMichal Meloun #include <machine/machdep.h>
44ef2ee5d0SMichal Meloun #include <machine/platformvar.h>
45ef2ee5d0SMichal Meloun 
46ef2ee5d0SMichal Meloun #include <dev/fdt/fdt_common.h>
47ef2ee5d0SMichal Meloun #include <dev/ofw/openfirm.h>
48ef2ee5d0SMichal Meloun 
49ef2ee5d0SMichal Meloun #include <arm/nvidia/tegra124/tegra124_mp.h>
50ef2ee5d0SMichal Meloun 
51ef2ee5d0SMichal Meloun #include "platform_if.h"
52ef2ee5d0SMichal Meloun 
53ef2ee5d0SMichal Meloun #define	PMC_PHYSBASE		0x7000e400
54ef2ee5d0SMichal Meloun #define	PMC_SIZE		0x400
55ef2ee5d0SMichal Meloun #define	PMC_CONTROL_REG		0x0
56ef2ee5d0SMichal Meloun #define	PMC_SCRATCH0		0x50
57ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_RECOVERY	(1 << 31)
58ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_BOOTLOADER	(1 << 30)
59ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_RCM		(1 << 1)
60ef2ee5d0SMichal Meloun #define	 PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \
61ef2ee5d0SMichal Meloun 					PMC_SCRATCH0_MODE_BOOTLOADER | \
62ef2ee5d0SMichal Meloun 					PMC_SCRATCH0_MODE_RCM)
63ef2ee5d0SMichal Meloun 
64ef2ee5d0SMichal Meloun static vm_offset_t
65ef2ee5d0SMichal Meloun tegra124_lastaddr(platform_t plat)
66ef2ee5d0SMichal Meloun {
67ef2ee5d0SMichal Meloun 
6830b72b68SRuslan Bukin 	return (devmap_lastaddr());
69ef2ee5d0SMichal Meloun }
70ef2ee5d0SMichal Meloun 
71ef2ee5d0SMichal Meloun static int
72ef2ee5d0SMichal Meloun tegra124_attach(platform_t plat)
73ef2ee5d0SMichal Meloun {
74ef2ee5d0SMichal Meloun 
75ef2ee5d0SMichal Meloun 	return (0);
76ef2ee5d0SMichal Meloun }
77ef2ee5d0SMichal Meloun 
78ef2ee5d0SMichal Meloun static void
79ef2ee5d0SMichal Meloun tegra124_late_init(platform_t plat)
80ef2ee5d0SMichal Meloun {
81ef2ee5d0SMichal Meloun 
82ef2ee5d0SMichal Meloun }
83ef2ee5d0SMichal Meloun 
84ef2ee5d0SMichal Meloun /*
85ef2ee5d0SMichal Meloun  * Set up static device mappings.
86ef2ee5d0SMichal Meloun  *
87ef2ee5d0SMichal Meloun  */
88ef2ee5d0SMichal Meloun static int
89ef2ee5d0SMichal Meloun tegra124_devmap_init(platform_t plat)
90ef2ee5d0SMichal Meloun {
91ef2ee5d0SMichal Meloun 
9230b72b68SRuslan Bukin 	devmap_add_entry(0x70000000, 0x01000000);
93ef2ee5d0SMichal Meloun 	return (0);
94ef2ee5d0SMichal Meloun }
95ef2ee5d0SMichal Meloun 
960dbb8873SAndrew Turner static void
970dbb8873SAndrew Turner tegra124_cpu_reset(platform_t plat)
98ef2ee5d0SMichal Meloun {
99ef2ee5d0SMichal Meloun 	bus_space_handle_t pmc;
100ef2ee5d0SMichal Meloun 	uint32_t reg;
101ef2ee5d0SMichal Meloun 
102ef2ee5d0SMichal Meloun 	printf("Resetting...\n");
103ef2ee5d0SMichal Meloun 	bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc);
104ef2ee5d0SMichal Meloun 
105ef2ee5d0SMichal Meloun 	reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
106ef2ee5d0SMichal Meloun 	reg &= PMC_SCRATCH0_MODE_MASK;
107ef2ee5d0SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0,
108ef2ee5d0SMichal Meloun 	   reg | PMC_SCRATCH0_MODE_BOOTLOADER); 	/* boot to bootloader */
109ef2ee5d0SMichal Meloun 	bus_space_read_4(fdtbus_bs_tag, pmc, PMC_SCRATCH0);
110ef2ee5d0SMichal Meloun 
111ef2ee5d0SMichal Meloun 	reg = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
112ef2ee5d0SMichal Meloun 	spinlock_enter();
113ef2ee5d0SMichal Meloun 	dsb();
114ef2ee5d0SMichal Meloun 	bus_space_write_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG, reg | 0x10);
115ef2ee5d0SMichal Meloun 	bus_space_read_4(fdtbus_bs_tag, pmc, PMC_CONTROL_REG);
116ef2ee5d0SMichal Meloun 	while(1)
117ef2ee5d0SMichal Meloun 		;
118ef2ee5d0SMichal Meloun 
119ef2ee5d0SMichal Meloun }
120ef2ee5d0SMichal Meloun 
121ef2ee5d0SMichal Meloun /*
122ef2ee5d0SMichal Meloun  * Early putc routine for EARLY_PRINTF support.  To use, add to kernel config:
123ef2ee5d0SMichal Meloun  *   option SOCDEV_PA=0x02000000
124ef2ee5d0SMichal Meloun  *   option SOCDEV_VA=0x02000000
125ef2ee5d0SMichal Meloun  *   option EARLY_PRINTF
126ef2ee5d0SMichal Meloun  */
127ef2ee5d0SMichal Meloun #if 0
128ef2ee5d0SMichal Meloun static void
129ef2ee5d0SMichal Meloun tegra124_early_putc(int c)
130ef2ee5d0SMichal Meloun {
131ef2ee5d0SMichal Meloun 	volatile uint32_t * UART_STAT_REG = (uint32_t *)0x02020098;
132ef2ee5d0SMichal Meloun 	volatile uint32_t * UART_TX_REG   = (uint32_t *)0x02020040;
133ef2ee5d0SMichal Meloun 	const uint32_t      UART_TXRDY    = (1 << 3);
134ef2ee5d0SMichal Meloun 
135ef2ee5d0SMichal Meloun 	while ((*UART_STAT_REG & UART_TXRDY) == 0)
136ef2ee5d0SMichal Meloun 		continue;
137ef2ee5d0SMichal Meloun 	*UART_TX_REG = c;
138ef2ee5d0SMichal Meloun }
139ef2ee5d0SMichal Meloun early_putc_t *early_putc = tegra124_early_putc;
140ef2ee5d0SMichal Meloun #endif
141ef2ee5d0SMichal Meloun 
142ef2ee5d0SMichal Meloun static platform_method_t tegra124_methods[] = {
143ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_attach,		tegra124_attach),
144ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_lastaddr,	tegra124_lastaddr),
145ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_devmap_init,	tegra124_devmap_init),
146ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_late_init,	tegra124_late_init),
1470dbb8873SAndrew Turner 	PLATFORMMETHOD(platform_cpu_reset,	tegra124_cpu_reset),
1480dbb8873SAndrew Turner 
149ef2ee5d0SMichal Meloun #ifdef SMP
150ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_mp_start_ap,	tegra124_mp_start_ap),
151ef2ee5d0SMichal Meloun 	PLATFORMMETHOD(platform_mp_setmaxid,	tegra124_mp_setmaxid),
152ef2ee5d0SMichal Meloun #endif
153ef2ee5d0SMichal Meloun 	PLATFORMMETHOD_END,
154ef2ee5d0SMichal Meloun };
155ef2ee5d0SMichal Meloun 
156*92fa5c23SMichal Meloun FDT_PLATFORM_DEF(tegra124, "Nvidia Jetson-TK1", 0, "nvidia,jetson-tk1", 120);
157