1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 37 #include <machine/bus.h> 38 39 #include <dev/extres/clk/clk.h> 40 41 #include <gnu/dts/include/dt-bindings/clock/tegra124-car.h> 42 #include "tegra124_car.h" 43 44 /* #define TEGRA_PLL_DEBUG */ 45 #ifdef TEGRA_PLL_DEBUG 46 #define dprintf(...) printf(__VA_ARGS__) 47 #else 48 #define dprintf(...) 49 #endif 50 51 /* All PLLs. */ 52 enum pll_type { 53 PLL_M, 54 PLL_X, 55 PLL_C, 56 PLL_C2, 57 PLL_C3, 58 PLL_C4, 59 PLL_P, 60 PLL_A, 61 PLL_U, 62 PLL_D, 63 PLL_D2, 64 PLL_DP, 65 PLL_E, 66 PLL_REFE}; 67 68 /* Common base register bits. */ 69 #define PLL_BASE_BYPASS (1U << 31) 70 #define PLL_BASE_ENABLE (1 << 30) 71 #define PLL_BASE_REFDISABLE (1 << 29) 72 #define PLL_BASE_LOCK (1 << 27) 73 #define PLL_BASE_DIVM_SHIFT 0 74 #define PLL_BASE_DIVN_SHIFT 8 75 76 #define PLLRE_MISC_LOCK (1 << 24) 77 78 #define PLL_MISC_LOCK_ENABLE (1 << 18) 79 #define PLLC_MISC_LOCK_ENABLE (1 << 24) 80 #define PLLDU_MISC_LOCK_ENABLE (1 << 22) 81 #define PLLRE_MISC_LOCK_ENABLE (1 << 30) 82 #define PLLSS_MISC_LOCK_ENABLE (1 << 30) 83 84 #define PLLC_IDDQ_BIT 26 85 #define PLLX_IDDQ_BIT 3 86 #define PLLRE_IDDQ_BIT 16 87 #define PLLSS_IDDQ_BIT 19 88 89 #define PLL_LOCK_TIMEOUT 1000 90 91 /* Post divider <-> register value mapping. */ 92 struct pdiv_table { 93 uint32_t divider; /* real divider */ 94 uint32_t value; /* register value */ 95 }; 96 97 /* Bits definition of M, N and P fields. */ 98 struct mnp_bits { 99 uint32_t m_width; 100 uint32_t n_width; 101 uint32_t p_width; 102 uint32_t p_shift; 103 }; 104 105 struct clk_pll_def { 106 struct clknode_init_def clkdef; 107 enum pll_type type; 108 uint32_t base_reg; 109 uint32_t misc_reg; 110 uint32_t lock_mask; 111 uint32_t lock_enable; 112 uint32_t iddq_reg; 113 uint32_t iddq_mask; 114 uint32_t flags; 115 struct pdiv_table *pdiv_table; 116 struct mnp_bits mnp_bits; 117 }; 118 119 #define PLL(_id, cname, pname) \ 120 .clkdef.id = _id, \ 121 .clkdef.name = cname, \ 122 .clkdef.parent_names = (const char *[]){pname}, \ 123 .clkdef.parent_cnt = 1, \ 124 .clkdef.flags = CLK_NODE_STATIC_STRINGS 125 126 /* Tegra K1 PLLs 127 PLLM: Clock source for EMC 2x clock 128 PLLX: Clock source for the fast CPU cluster and the shadow CPU 129 PLLC: Clock source for general use 130 PLLC2: Clock source for engine scaling 131 PLLC3: Clock source for engine scaling 132 PLLC4: Clock source for ISP/VI units 133 PLLP: Clock source for most peripherals 134 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) 135 PLLU: Clock source for USB PHY, provides 12/60/480 MHz 136 PLLD: Clock sources for the DSI and display subsystem 137 PLLD2: Clock sources for the DSI and display subsystem 138 refPLLe: 139 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) 140 PLLDP: Clock source for eDP/LVDS (spread spectrum) 141 142 DFLLCPU: DFLL clock source for the fast CPU cluster 143 GPCPLL: Clock source for the GPU 144 */ 145 146 static struct pdiv_table pllm_map[] = { 147 {1, 0}, 148 {2, 1}, 149 {0, 0} 150 }; 151 152 static struct pdiv_table pllxc_map[] = { 153 { 1, 0}, 154 { 2, 1}, 155 { 3, 2}, 156 { 4, 3}, 157 { 5, 4}, 158 { 6, 5}, 159 { 8, 6}, 160 {10, 7}, 161 {12, 8}, 162 {16, 9}, 163 {12, 10}, 164 {16, 11}, 165 {20, 12}, 166 {24, 13}, 167 {32, 14}, 168 { 0, 0} 169 }; 170 171 static struct pdiv_table pllc_map[] = { 172 { 1, 0}, 173 { 2, 1}, 174 { 3, 2}, 175 { 4, 3}, 176 { 6, 4}, 177 { 8, 5}, 178 {12, 6}, 179 {16, 7}, 180 { 0, 0} 181 }; 182 183 static struct pdiv_table pll12g_ssd_esd_map[] = { 184 { 1, 0}, 185 { 2, 1}, 186 { 3, 2}, 187 { 4, 3}, 188 { 5, 4}, 189 { 6, 5}, 190 { 8, 6}, 191 {10, 7}, 192 {12, 8}, 193 {16, 9}, 194 {12, 10}, 195 {16, 11}, 196 {20, 12}, 197 {24, 13}, 198 {32, 14}, 199 { 0, 0} 200 }; 201 202 static struct pdiv_table pllu_map[] = { 203 {1, 1}, 204 {2, 0}, 205 {0, 0} 206 }; 207 208 static struct clk_pll_def pll_clks[] = { 209 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 210 { 211 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"), 212 .type = PLL_M, 213 .base_reg = PLLM_BASE, 214 .misc_reg = PLLM_MISC, 215 .lock_mask = PLL_BASE_LOCK, 216 .lock_enable = PLL_MISC_LOCK_ENABLE, 217 .pdiv_table = pllm_map, 218 .mnp_bits = {8, 8, 1, 20}, 219 }, 220 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 221 { 222 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"), 223 .type = PLL_X, 224 .base_reg = PLLX_BASE, 225 .misc_reg = PLLX_MISC, 226 .lock_mask = PLL_BASE_LOCK, 227 .lock_enable = PLL_MISC_LOCK_ENABLE, 228 .iddq_reg = PLLX_MISC3, 229 .iddq_mask = 1 << PLLX_IDDQ_BIT, 230 .pdiv_table = pllxc_map, 231 .mnp_bits = {8, 8, 4, 20}, 232 }, 233 /* PLLC: 600 MHz Clock source for general use */ 234 { 235 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 236 .type = PLL_C, 237 .base_reg = PLLC_BASE, 238 .misc_reg = PLLC_MISC, 239 .lock_mask = PLL_BASE_LOCK, 240 .lock_enable = PLLC_MISC_LOCK_ENABLE, 241 .iddq_reg = PLLC_MISC, 242 .iddq_mask = 1 << PLLC_IDDQ_BIT, 243 .pdiv_table = pllc_map, 244 .mnp_bits = {8, 8, 4, 20}, 245 }, 246 /* PLLC2: 600 MHz Clock source for engine scaling */ 247 { 248 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 249 .type = PLL_C2, 250 .base_reg = PLLC2_BASE, 251 .misc_reg = PLLC2_MISC, 252 .lock_mask = PLL_BASE_LOCK, 253 .lock_enable = PLL_MISC_LOCK_ENABLE, 254 .pdiv_table = pllc_map, 255 .mnp_bits = {2, 8, 3, 20}, 256 }, 257 /* PLLC3: 600 MHz Clock source for engine scaling */ 258 { 259 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 260 .type = PLL_C3, 261 .base_reg = PLLC3_BASE, 262 .misc_reg = PLLC3_MISC, 263 .lock_mask = PLL_BASE_LOCK, 264 .lock_enable = PLL_MISC_LOCK_ENABLE, 265 .pdiv_table = pllc_map, 266 .mnp_bits = {2, 8, 3, 20}, 267 }, 268 /* PLLC4: 600 MHz Clock source for ISP/VI units */ 269 { 270 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"), 271 .type = PLL_C4, 272 .base_reg = PLLC4_BASE, 273 .misc_reg = PLLC4_MISC, 274 .lock_mask = PLL_BASE_LOCK, 275 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 276 .iddq_reg = PLLC4_BASE, 277 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 278 .pdiv_table = pll12g_ssd_esd_map, 279 .mnp_bits = {8, 8, 4, 20}, 280 }, 281 /* PLLP: 408 MHz Clock source for most peripherals */ 282 { 283 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 284 .type = PLL_P, 285 .base_reg = PLLP_BASE, 286 .misc_reg = PLLP_MISC, 287 .lock_mask = PLL_BASE_LOCK, 288 .lock_enable = PLL_MISC_LOCK_ENABLE, 289 .mnp_bits = {5, 10, 3, 20}, 290 }, 291 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */ 292 { 293 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"), 294 .type = PLL_A, 295 .base_reg = PLLA_BASE, 296 .misc_reg = PLLA_MISC, 297 .lock_mask = PLL_BASE_LOCK, 298 .lock_enable = PLL_MISC_LOCK_ENABLE, 299 .mnp_bits = {5, 10, 3, 20}, 300 }, 301 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 302 { 303 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"), 304 .type = PLL_U, 305 .base_reg = PLLU_BASE, 306 .misc_reg = PLLU_MISC, 307 .lock_mask = PLL_BASE_LOCK, 308 .lock_enable = PLLDU_MISC_LOCK_ENABLE, 309 .pdiv_table = pllu_map, 310 .mnp_bits = {5, 10, 1, 20}, 311 }, 312 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */ 313 { 314 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"), 315 .type = PLL_D, 316 .base_reg = PLLD_BASE, 317 .misc_reg = PLLD_MISC, 318 .lock_mask = PLL_BASE_LOCK, 319 .lock_enable = PLL_MISC_LOCK_ENABLE, 320 .mnp_bits = {5, 11, 3, 20}, 321 }, 322 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */ 323 { 324 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 325 .type = PLL_D2, 326 .base_reg = PLLD2_BASE, 327 .misc_reg = PLLD2_MISC, 328 .lock_mask = PLL_BASE_LOCK, 329 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 330 .iddq_reg = PLLD2_BASE, 331 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 332 .pdiv_table = pll12g_ssd_esd_map, 333 .mnp_bits = {8, 8, 4, 20}, 334 }, 335 /* refPLLe: */ 336 { 337 PLL(0, "pllREFE_out", "osc_div_clk"), 338 .type = PLL_REFE, 339 .base_reg = PLLRE_BASE, 340 .misc_reg = PLLRE_MISC, 341 .lock_mask = PLLRE_MISC_LOCK, 342 .lock_enable = PLLRE_MISC_LOCK_ENABLE, 343 .iddq_reg = PLLRE_MISC, 344 .iddq_mask = 1 << PLLRE_IDDQ_BIT, 345 .mnp_bits = {8, 8, 4, 16}, 346 }, 347 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */ 348 { 349 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"), 350 .type = PLL_E, 351 .base_reg = PLLE_BASE, 352 .misc_reg = PLLE_MISC, 353 .lock_mask = PLLE_MISC_LOCK, 354 .lock_enable = PLLE_MISC_LOCK_ENABLE, 355 .mnp_bits = {8, 8, 4, 24}, 356 }, 357 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */ 358 { 359 PLL(0, "pllDP_out0", "pllDP_src"), 360 .type = PLL_DP, 361 .base_reg = PLLDP_BASE, 362 .misc_reg = PLLDP_MISC, 363 .lock_mask = PLL_BASE_LOCK, 364 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 365 .iddq_reg = PLLDP_BASE, 366 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 367 .pdiv_table = pll12g_ssd_esd_map, 368 .mnp_bits = {8, 8, 4, 20}, 369 }, 370 }; 371 372 static int tegra124_pll_init(struct clknode *clk, device_t dev); 373 static int tegra124_pll_set_gate(struct clknode *clk, bool enable); 374 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq); 375 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, 376 uint64_t *fout, int flags, int *stop); 377 struct pll_sc { 378 device_t clkdev; 379 enum pll_type type; 380 uint32_t base_reg; 381 uint32_t misc_reg; 382 uint32_t lock_mask; 383 uint32_t lock_enable; 384 uint32_t iddq_reg; 385 uint32_t iddq_mask; 386 uint32_t flags; 387 struct pdiv_table *pdiv_table; 388 struct mnp_bits mnp_bits; 389 }; 390 391 static clknode_method_t tegra124_pll_methods[] = { 392 /* Device interface */ 393 CLKNODEMETHOD(clknode_init, tegra124_pll_init), 394 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate), 395 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc), 396 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq), 397 CLKNODEMETHOD_END 398 }; 399 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods, 400 sizeof(struct pll_sc), clknode_class); 401 402 static int 403 pll_enable(struct pll_sc *sc) 404 { 405 uint32_t reg; 406 407 408 RD4(sc, sc->base_reg, ®); 409 if (sc->type != PLL_E) 410 reg &= ~PLL_BASE_BYPASS; 411 reg |= PLL_BASE_ENABLE; 412 WR4(sc, sc->base_reg, reg); 413 return (0); 414 } 415 416 static int 417 pll_disable(struct pll_sc *sc) 418 { 419 uint32_t reg; 420 421 RD4(sc, sc->base_reg, ®); 422 if (sc->type != PLL_E) 423 reg |= PLL_BASE_BYPASS; 424 reg &= ~PLL_BASE_ENABLE; 425 WR4(sc, sc->base_reg, reg); 426 return (0); 427 } 428 429 static uint32_t 430 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 431 { 432 struct pdiv_table *tbl; 433 434 tbl = sc->pdiv_table; 435 if (tbl == NULL) 436 return (ffs(p_div)); 437 438 while (tbl->divider != 0) { 439 if (p_div <= tbl->divider) 440 return (tbl->value); 441 tbl++; 442 } 443 return ~0; 444 } 445 446 static uint32_t 447 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 448 { 449 struct pdiv_table *tbl; 450 451 tbl = sc->pdiv_table; 452 if (tbl != NULL) { 453 while (tbl->divider) { 454 if (reg == tbl->value) 455 return (tbl->divider); 456 tbl++; 457 } 458 return (0); 459 } 460 return (1 << reg); 461 } 462 463 static uint32_t 464 get_masked(uint32_t val, uint32_t shift, uint32_t width) 465 { 466 467 return ((val >> shift) & ((1 << width) - 1)); 468 } 469 470 static uint32_t 471 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 472 { 473 474 val &= ~(((1 << width) - 1) << shift); 475 val |= (v & ((1 << width) - 1)) << shift; 476 return (val); 477 } 478 479 static void 480 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 481 { 482 uint32_t val; 483 struct mnp_bits *mnp_bits; 484 485 mnp_bits = &sc->mnp_bits; 486 RD4(sc, sc->base_reg, &val); 487 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 488 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 489 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 490 } 491 492 static uint32_t 493 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 494 uint32_t p) 495 { 496 struct mnp_bits *mnp_bits; 497 498 mnp_bits = &sc->mnp_bits; 499 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 500 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 501 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 502 return (val); 503 } 504 505 static bool 506 is_locked(struct pll_sc *sc) 507 { 508 uint32_t reg; 509 510 switch (sc->type) { 511 case PLL_REFE: 512 RD4(sc, sc->misc_reg, ®); 513 reg &= PLLRE_MISC_LOCK; 514 break; 515 516 case PLL_E: 517 RD4(sc, sc->misc_reg, ®); 518 reg &= PLLE_MISC_LOCK; 519 break; 520 521 default: 522 RD4(sc, sc->base_reg, ®); 523 reg &= PLL_BASE_LOCK; 524 break; 525 } 526 return (reg != 0); 527 } 528 529 static int 530 wait_for_lock(struct pll_sc *sc) 531 { 532 int i; 533 534 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 535 if (is_locked(sc)) 536 break; 537 DELAY(10); 538 } 539 if (i <= 0) { 540 printf("PLL lock timeout\n"); 541 return (ETIMEDOUT); 542 } 543 return (0); 544 } 545 546 static int 547 plle_enable(struct pll_sc *sc) 548 { 549 uint32_t reg; 550 int rv; 551 struct mnp_bits *mnp_bits; 552 uint32_t pll_m = 1; 553 uint32_t pll_n = 200; 554 uint32_t pll_p = 13; 555 uint32_t pll_cml = 13; 556 557 mnp_bits = &sc->mnp_bits; 558 559 560 /* Disable lock override. */ 561 RD4(sc, sc->base_reg, ®); 562 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 563 WR4(sc, sc->base_reg, reg); 564 565 RD4(sc, PLLE_AUX, ®); 566 reg |= PLLE_AUX_ENABLE_SWCTL; 567 reg &= ~PLLE_AUX_SEQ_ENABLE; 568 WR4(sc, PLLE_AUX, reg); 569 DELAY(10); 570 571 RD4(sc, sc->misc_reg, ®); 572 reg |= PLLE_MISC_LOCK_ENABLE; 573 reg |= PLLE_MISC_IDDQ_SWCTL; 574 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 575 reg |= PLLE_MISC_PTS; 576 reg |= PLLE_MISC_VREG_BG_CTRL_MASK; 577 reg |= PLLE_MISC_VREG_CTRL_MASK; 578 WR4(sc, sc->misc_reg, reg); 579 DELAY(10); 580 581 RD4(sc, PLLE_SS_CNTL, ®); 582 reg |= PLLE_SS_CNTL_DISABLE; 583 WR4(sc, PLLE_SS_CNTL, reg); 584 585 RD4(sc, sc->base_reg, ®); 586 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p); 587 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 588 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT; 589 WR4(sc, sc->base_reg, reg); 590 DELAY(10); 591 592 pll_enable(sc); 593 rv = wait_for_lock(sc); 594 if (rv != 0) 595 return (rv); 596 597 RD4(sc, PLLE_SS_CNTL, ®); 598 reg &= ~PLLE_SS_CNTL_SSCCENTER; 599 reg &= ~PLLE_SS_CNTL_SSCINVERT; 600 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK; 601 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL; 602 WR4(sc, PLLE_SS_CNTL, reg); 603 reg &= ~PLLE_SS_CNTL_SSCBYP; 604 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 605 WR4(sc, PLLE_SS_CNTL, reg); 606 DELAY(10); 607 608 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 609 WR4(sc, PLLE_SS_CNTL, reg); 610 DELAY(10); 611 612 /* HW control of brick pll. */ 613 RD4(sc, sc->misc_reg, ®); 614 reg &= ~PLLE_MISC_IDDQ_SWCTL; 615 WR4(sc, sc->misc_reg, reg); 616 617 RD4(sc, PLLE_AUX, ®); 618 reg |= PLLE_AUX_USE_LOCKDET; 619 reg |= PLLE_AUX_SEQ_START_STATE; 620 reg &= ~PLLE_AUX_ENABLE_SWCTL; 621 reg &= ~PLLE_AUX_SS_SWCTL; 622 WR4(sc, PLLE_AUX, reg); 623 reg |= PLLE_AUX_SEQ_START_STATE; 624 DELAY(10); 625 reg |= PLLE_AUX_SEQ_ENABLE; 626 WR4(sc, PLLE_AUX, reg); 627 628 RD4(sc, XUSBIO_PLL_CFG0, ®); 629 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 630 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE; 631 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 632 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 633 WR4(sc, XUSBIO_PLL_CFG0, reg); 634 DELAY(10); 635 636 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 637 WR4(sc, XUSBIO_PLL_CFG0, reg); 638 639 640 /* Enable HW control and unreset SATA PLL. */ 641 RD4(sc, SATA_PLL_CFG0, ®); 642 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 643 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 644 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 645 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 646 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 647 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 648 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 649 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 650 reg |= SATA_PLL_CFG0_SEQ_START_STATE; 651 WR4(sc, SATA_PLL_CFG0, reg); 652 DELAY(10); 653 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 654 WR4(sc, SATA_PLL_CFG0, reg); 655 656 /* Enable HW control of PCIe PLL. */ 657 RD4(sc, PCIE_PLL_CFG0, ®); 658 reg |= PCIE_PLL_CFG0_SEQ_ENABLE; 659 WR4(sc, PCIE_PLL_CFG0, reg); 660 661 return (0); 662 } 663 664 static int 665 tegra124_pll_set_gate(struct clknode *clknode, bool enable) 666 { 667 int rv; 668 struct pll_sc *sc; 669 670 sc = clknode_get_softc(clknode); 671 if (enable == 0) { 672 rv = pll_disable(sc); 673 return(rv); 674 } 675 676 if (sc->type == PLL_E) 677 rv = plle_enable(sc); 678 else 679 rv = pll_enable(sc); 680 return (rv); 681 } 682 683 static int 684 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 685 uint32_t m, uint32_t n, uint32_t p) 686 { 687 uint32_t reg; 688 struct mnp_bits *mnp_bits; 689 int rv; 690 691 mnp_bits = &sc->mnp_bits; 692 if (m >= (1 << mnp_bits->m_width)) 693 return (ERANGE); 694 if (n >= (1 << mnp_bits->n_width)) 695 return (ERANGE); 696 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 697 return (ERANGE); 698 699 if (flags & CLK_SET_DRYRUN) { 700 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 701 (*fout != (((fin / m) * n) /p))) 702 return (ERANGE); 703 704 *fout = ((fin / m) * n) /p; 705 return (0); 706 } 707 708 pll_disable(sc); 709 710 /* take pll out of IDDQ */ 711 if (sc->iddq_reg != 0) 712 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 713 714 RD4(sc, sc->base_reg, ®); 715 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 716 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 717 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 718 mnp_bits->p_width); 719 WR4(sc, sc->base_reg, reg); 720 721 /* Enable PLL. */ 722 RD4(sc, sc->base_reg, ®); 723 reg |= PLL_BASE_ENABLE; 724 WR4(sc, sc->base_reg, reg); 725 726 /* Enable lock detection. */ 727 RD4(sc, sc->misc_reg, ®); 728 reg |= sc->lock_enable; 729 WR4(sc, sc->misc_reg, reg); 730 731 rv = wait_for_lock(sc); 732 if (rv != 0) { 733 /* Disable PLL */ 734 RD4(sc, sc->base_reg, ®); 735 reg &= ~PLL_BASE_ENABLE; 736 WR4(sc, sc->base_reg, reg); 737 return (rv); 738 } 739 RD4(sc, sc->misc_reg, ®); 740 741 pll_enable(sc); 742 *fout = ((fin / m) * n) / p; 743 return 0; 744 } 745 746 static int 747 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 748 { 749 uint32_t m, n, p; 750 751 p = 1; 752 m = 5; 753 n = (*fout * p * m + fin / 2)/ fin; 754 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 755 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 756 } 757 758 static int 759 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 760 { 761 uint32_t m, n, p; 762 763 764 p = 2; 765 m = 1; 766 n = (*fout * p * m + fin / 2)/ fin; 767 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 768 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 769 } 770 771 static int 772 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 773 { 774 uint32_t m, n, p; 775 776 p = 2; 777 m = 1; 778 n = (*fout * p * m + fin / 2)/ fin; 779 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 780 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 781 } 782 783 784 785 static int 786 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 787 { 788 uint32_t m, n, p; 789 790 m = 1; 791 p = 1; 792 n = *fout * p * m / fin; 793 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 794 } 795 796 static int 797 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 798 { 799 uint32_t reg; 800 uint32_t m, n, p; 801 struct mnp_bits *mnp_bits; 802 int rv; 803 804 mnp_bits = &sc->mnp_bits; 805 806 p = 1; 807 m = 1; 808 n = (*fout * p * m + fin / 2)/ fin; 809 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 810 811 if (m >= (1 << mnp_bits->m_width)) 812 return (ERANGE); 813 if (n >= (1 << mnp_bits->n_width)) 814 return (ERANGE); 815 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 816 return (ERANGE); 817 818 if (flags & CLK_SET_DRYRUN) { 819 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 820 (*fout != (((fin / m) * n) /p))) 821 return (ERANGE); 822 *fout = ((fin / m) * n) /p; 823 return (0); 824 } 825 826 /* PLLX doesn't have bypass, disable it first. */ 827 RD4(sc, sc->base_reg, ®); 828 reg &= ~PLL_BASE_ENABLE; 829 WR4(sc, sc->base_reg, reg); 830 831 /* Set PLL. */ 832 RD4(sc, sc->base_reg, ®); 833 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 834 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 835 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 836 mnp_bits->p_width); 837 WR4(sc, sc->base_reg, reg); 838 RD4(sc, sc->base_reg, ®); 839 DELAY(100); 840 841 /* Enable lock detection. */ 842 RD4(sc, sc->misc_reg, ®); 843 reg |= sc->lock_enable; 844 WR4(sc, sc->misc_reg, reg); 845 846 /* Enable PLL. */ 847 RD4(sc, sc->base_reg, ®); 848 reg |= PLL_BASE_ENABLE; 849 WR4(sc, sc->base_reg, reg); 850 851 rv = wait_for_lock(sc); 852 if (rv != 0) { 853 /* Disable PLL */ 854 RD4(sc, sc->base_reg, ®); 855 reg &= ~PLL_BASE_ENABLE; 856 WR4(sc, sc->base_reg, reg); 857 return (rv); 858 } 859 RD4(sc, sc->misc_reg, ®); 860 861 *fout = ((fin / m) * n) / p; 862 return (0); 863 } 864 865 static int 866 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 867 int flags, int *stop) 868 { 869 *stop = 1; 870 int rv; 871 struct pll_sc *sc; 872 873 sc = clknode_get_softc(clknode); 874 dprintf("%s: Requested freq: %llu, input freq: %llu\n", __func__, 875 *fout, fin); 876 switch (sc->type) { 877 case PLL_A: 878 rv = plla_set_freq(sc, fin, fout, flags); 879 break; 880 case PLL_C: 881 rv = pllc_set_freq(sc, fin, fout, flags); 882 break; 883 case PLL_D2: 884 rv = plld2_set_freq(sc, fin, fout, flags); 885 break; 886 887 case PLL_REFE: 888 rv = pllrefe_set_freq(sc, fin, fout, flags); 889 break; 890 891 case PLL_X: 892 rv = pllx_set_freq(sc, fin, fout, flags); 893 break; 894 895 case PLL_U: 896 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 897 rv = 0; 898 else 899 rv = ERANGE; 900 break; 901 default: 902 rv = ENXIO; 903 break; 904 } 905 return (rv); 906 } 907 908 909 static int 910 tegra124_pll_init(struct clknode *clk, device_t dev) 911 { 912 struct pll_sc *sc; 913 uint32_t reg; 914 915 sc = clknode_get_softc(clk); 916 917 /* If PLL is enabled, enable lock detect too. */ 918 RD4(sc, sc->base_reg, ®); 919 if (reg & PLL_BASE_ENABLE) { 920 RD4(sc, sc->misc_reg, ®); 921 reg |= sc->lock_enable; 922 WR4(sc, sc->misc_reg, reg); 923 } 924 925 clknode_init_parent_idx(clk, 0); 926 return(0); 927 } 928 929 static int 930 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq) 931 { 932 struct pll_sc *sc; 933 uint32_t m, n, p, pr; 934 uint32_t reg, misc_reg; 935 int locked; 936 937 sc = clknode_get_softc(clk); 938 939 RD4(sc, sc->base_reg, ®); 940 RD4(sc, sc->misc_reg, &misc_reg); 941 942 get_divisors(sc, &m, &n, &pr); 943 if (sc->type != PLL_E) 944 p = reg_to_pdiv(sc, pr); 945 else 946 p = 2 * (pr - 1); 947 locked = is_locked(sc); 948 949 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 950 "e: %d, r: %d, o: %d - %s\n", __func__, 951 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 952 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 953 locked ? "locked" : "unlocked"); 954 955 if ((m == 0) || (n == 0) || (p == 0)) { 956 *freq = 0; 957 return (EINVAL); 958 } 959 *freq = ((*freq / m) * n) / p; 960 return (0); 961 } 962 963 static int 964 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 965 { 966 struct clknode *clk; 967 struct pll_sc *sc; 968 969 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef); 970 if (clk == NULL) 971 return (ENXIO); 972 973 sc = clknode_get_softc(clk); 974 sc->clkdev = clknode_get_device(clk); 975 sc->type = clkdef->type; 976 sc->base_reg = clkdef->base_reg; 977 sc->misc_reg = clkdef->misc_reg; 978 sc->lock_mask = clkdef->lock_mask; 979 sc->lock_enable = clkdef->lock_enable; 980 sc->iddq_reg = clkdef->iddq_reg; 981 sc->iddq_mask = clkdef->iddq_mask; 982 sc->flags = clkdef->flags; 983 sc->pdiv_table = clkdef->pdiv_table; 984 sc->mnp_bits = clkdef->mnp_bits; 985 clknode_register(clkdom, clk); 986 return (0); 987 } 988 989 static void config_utmi_pll(struct tegra124_car_softc *sc) 990 { 991 uint32_t reg; 992 /* 993 * XXX Simplified UTMIP settings for 12MHz base clock. 994 */ 995 #define ENABLE_DELAY_COUNT 0x02 996 #define STABLE_COUNT 0x2F 997 #define ACTIVE_DELAY_COUNT 0x04 998 #define XTAL_FREQ_COUNT 0x76 999 1000 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1001 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1002 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1003 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1004 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1005 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1006 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1007 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1008 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1009 1010 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1011 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1012 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1013 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1014 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1015 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1016 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1017 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1018 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1019 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1020 1021 /* Prepare UTMIP requencer. */ 1022 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1023 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1024 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1025 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1026 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1027 1028 /* Powerup UTMIP. */ 1029 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1030 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1031 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1032 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1033 DELAY(10); 1034 1035 /* SW override for UTMIPLL */ 1036 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1037 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1038 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1039 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1040 DELAY(10); 1041 1042 /* HW control of UTMIPLL. */ 1043 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1044 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1045 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1046 } 1047 1048 void 1049 tegra124_init_plls(struct tegra124_car_softc *sc) 1050 { 1051 int i, rv; 1052 1053 for (i = 0; i < nitems(pll_clks); i++) { 1054 rv = pll_register(sc->clkdom, pll_clks + i); 1055 if (rv != 0) 1056 panic("pll_register failed"); 1057 } 1058 config_utmi_pll(sc); 1059 1060 } 1061