1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 37 #include <machine/bus.h> 38 39 #include <dev/extres/clk/clk.h> 40 41 #include <dt-bindings/clock/tegra124-car.h> 42 #include "tegra124_car.h" 43 44 /* #define TEGRA_PLL_DEBUG */ 45 #ifdef TEGRA_PLL_DEBUG 46 #define dprintf(...) printf(__VA_ARGS__) 47 #else 48 #define dprintf(...) 49 #endif 50 51 /* All PLLs. */ 52 enum pll_type { 53 PLL_M, 54 PLL_X, 55 PLL_C, 56 PLL_C2, 57 PLL_C3, 58 PLL_C4, 59 PLL_P, 60 PLL_A, 61 PLL_U, 62 PLL_D, 63 PLL_D2, 64 PLL_DP, 65 PLL_E, 66 PLL_REFE}; 67 68 /* Common base register bits. */ 69 #define PLL_BASE_BYPASS (1U << 31) 70 #define PLL_BASE_ENABLE (1 << 30) 71 #define PLL_BASE_REFDISABLE (1 << 29) 72 #define PLL_BASE_LOCK (1 << 27) 73 #define PLL_BASE_DIVM_SHIFT 0 74 #define PLL_BASE_DIVN_SHIFT 8 75 76 #define PLLRE_MISC_LOCK (1 << 24) 77 78 #define PLL_MISC_LOCK_ENABLE (1 << 18) 79 #define PLLC_MISC_LOCK_ENABLE (1 << 24) 80 #define PLLDU_MISC_LOCK_ENABLE (1 << 22) 81 #define PLLRE_MISC_LOCK_ENABLE (1 << 30) 82 #define PLLSS_MISC_LOCK_ENABLE (1 << 30) 83 84 #define PLLC_IDDQ_BIT 26 85 #define PLLX_IDDQ_BIT 3 86 #define PLLRE_IDDQ_BIT 16 87 #define PLLSS_IDDQ_BIT 19 88 89 #define PLL_LOCK_TIMEOUT 5000 90 91 /* Post divider <-> register value mapping. */ 92 struct pdiv_table { 93 uint32_t divider; /* real divider */ 94 uint32_t value; /* register value */ 95 }; 96 97 /* Bits definition of M, N and P fields. */ 98 struct mnp_bits { 99 uint32_t m_width; 100 uint32_t n_width; 101 uint32_t p_width; 102 uint32_t p_shift; 103 }; 104 105 struct clk_pll_def { 106 struct clknode_init_def clkdef; 107 enum pll_type type; 108 uint32_t base_reg; 109 uint32_t misc_reg; 110 uint32_t lock_mask; 111 uint32_t lock_enable; 112 uint32_t iddq_reg; 113 uint32_t iddq_mask; 114 uint32_t flags; 115 struct pdiv_table *pdiv_table; 116 struct mnp_bits mnp_bits; 117 }; 118 119 #define PLL(_id, cname, pname) \ 120 .clkdef.id = _id, \ 121 .clkdef.name = cname, \ 122 .clkdef.parent_names = (const char *[]){pname}, \ 123 .clkdef.parent_cnt = 1, \ 124 .clkdef.flags = CLK_NODE_STATIC_STRINGS 125 126 /* Tegra K1 PLLs 127 PLLM: Clock source for EMC 2x clock 128 PLLX: Clock source for the fast CPU cluster and the shadow CPU 129 PLLC: Clock source for general use 130 PLLC2: Clock source for engine scaling 131 PLLC3: Clock source for engine scaling 132 PLLC4: Clock source for ISP/VI units 133 PLLP: Clock source for most peripherals 134 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) 135 PLLU: Clock source for USB PHY, provides 12/60/480 MHz 136 PLLD: Clock sources for the DSI and display subsystem 137 PLLD2: Clock sources for the DSI and display subsystem 138 refPLLe: 139 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) 140 PLLDP: Clock source for eDP/LVDS (spread spectrum) 141 142 DFLLCPU: DFLL clock source for the fast CPU cluster 143 GPCPLL: Clock source for the GPU 144 */ 145 146 static struct pdiv_table pllm_map[] = { 147 {1, 0}, 148 {2, 1}, 149 {0, 0} 150 }; 151 152 static struct pdiv_table pllxc_map[] = { 153 { 1, 0}, 154 { 2, 1}, 155 { 3, 2}, 156 { 4, 3}, 157 { 5, 4}, 158 { 6, 5}, 159 { 8, 6}, 160 {10, 7}, 161 {12, 8}, 162 {16, 9}, 163 {12, 10}, 164 {16, 11}, 165 {20, 12}, 166 {24, 13}, 167 {32, 14}, 168 { 0, 0} 169 }; 170 171 static struct pdiv_table pllc_map[] = { 172 { 1, 0}, 173 { 2, 1}, 174 { 3, 2}, 175 { 4, 3}, 176 { 6, 4}, 177 { 8, 5}, 178 {12, 6}, 179 {16, 7}, 180 { 0, 0} 181 }; 182 183 static struct pdiv_table pll12g_ssd_esd_map[] = { 184 { 1, 0}, 185 { 2, 1}, 186 { 3, 2}, 187 { 4, 3}, 188 { 5, 4}, 189 { 6, 5}, 190 { 8, 6}, 191 {10, 7}, 192 {12, 8}, 193 {16, 9}, 194 {12, 10}, 195 {16, 11}, 196 {20, 12}, 197 {24, 13}, 198 {32, 14}, 199 { 0, 0} 200 }; 201 202 static struct pdiv_table pllu_map[] = { 203 {1, 1}, 204 {2, 0}, 205 {0, 0} 206 }; 207 208 static struct pdiv_table pllrefe_map[] = { 209 {1, 0}, 210 {2, 1}, 211 {3, 2}, 212 {4, 3}, 213 {5, 4}, 214 {6, 5}, 215 {0, 0}, 216 }; 217 218 static struct clk_pll_def pll_clks[] = { 219 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 220 { 221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"), 222 .type = PLL_M, 223 .base_reg = PLLM_BASE, 224 .misc_reg = PLLM_MISC, 225 .lock_mask = PLL_BASE_LOCK, 226 .lock_enable = PLL_MISC_LOCK_ENABLE, 227 .pdiv_table = pllm_map, 228 .mnp_bits = {8, 8, 1, 20}, 229 }, 230 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 231 { 232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"), 233 .type = PLL_X, 234 .base_reg = PLLX_BASE, 235 .misc_reg = PLLX_MISC, 236 .lock_mask = PLL_BASE_LOCK, 237 .lock_enable = PLL_MISC_LOCK_ENABLE, 238 .iddq_reg = PLLX_MISC3, 239 .iddq_mask = 1 << PLLX_IDDQ_BIT, 240 .pdiv_table = pllxc_map, 241 .mnp_bits = {8, 8, 4, 20}, 242 }, 243 /* PLLC: 600 MHz Clock source for general use */ 244 { 245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 246 .type = PLL_C, 247 .base_reg = PLLC_BASE, 248 .misc_reg = PLLC_MISC, 249 .lock_mask = PLL_BASE_LOCK, 250 .lock_enable = PLLC_MISC_LOCK_ENABLE, 251 .iddq_reg = PLLC_MISC, 252 .iddq_mask = 1 << PLLC_IDDQ_BIT, 253 .pdiv_table = pllc_map, 254 .mnp_bits = {8, 8, 4, 20}, 255 }, 256 /* PLLC2: 600 MHz Clock source for engine scaling */ 257 { 258 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 259 .type = PLL_C2, 260 .base_reg = PLLC2_BASE, 261 .misc_reg = PLLC2_MISC, 262 .lock_mask = PLL_BASE_LOCK, 263 .lock_enable = PLL_MISC_LOCK_ENABLE, 264 .pdiv_table = pllc_map, 265 .mnp_bits = {2, 8, 3, 20}, 266 }, 267 /* PLLC3: 600 MHz Clock source for engine scaling */ 268 { 269 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 270 .type = PLL_C3, 271 .base_reg = PLLC3_BASE, 272 .misc_reg = PLLC3_MISC, 273 .lock_mask = PLL_BASE_LOCK, 274 .lock_enable = PLL_MISC_LOCK_ENABLE, 275 .pdiv_table = pllc_map, 276 .mnp_bits = {2, 8, 3, 20}, 277 }, 278 /* PLLC4: 600 MHz Clock source for ISP/VI units */ 279 { 280 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"), 281 .type = PLL_C4, 282 .base_reg = PLLC4_BASE, 283 .misc_reg = PLLC4_MISC, 284 .lock_mask = PLL_BASE_LOCK, 285 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 286 .iddq_reg = PLLC4_BASE, 287 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 288 .pdiv_table = pll12g_ssd_esd_map, 289 .mnp_bits = {8, 8, 4, 20}, 290 }, 291 /* PLLP: 408 MHz Clock source for most peripherals */ 292 { 293 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 294 .type = PLL_P, 295 .base_reg = PLLP_BASE, 296 .misc_reg = PLLP_MISC, 297 .lock_mask = PLL_BASE_LOCK, 298 .lock_enable = PLL_MISC_LOCK_ENABLE, 299 .mnp_bits = {5, 10, 3, 20}, 300 }, 301 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */ 302 { 303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"), 304 .type = PLL_A, 305 .base_reg = PLLA_BASE, 306 .misc_reg = PLLA_MISC, 307 .lock_mask = PLL_BASE_LOCK, 308 .lock_enable = PLL_MISC_LOCK_ENABLE, 309 .mnp_bits = {5, 10, 3, 20}, 310 }, 311 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 312 { 313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"), 314 .type = PLL_U, 315 .base_reg = PLLU_BASE, 316 .misc_reg = PLLU_MISC, 317 .lock_mask = PLL_BASE_LOCK, 318 .lock_enable = PLLDU_MISC_LOCK_ENABLE, 319 .pdiv_table = pllu_map, 320 .mnp_bits = {5, 10, 1, 20}, 321 }, 322 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */ 323 { 324 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"), 325 .type = PLL_D, 326 .base_reg = PLLD_BASE, 327 .misc_reg = PLLD_MISC, 328 .lock_mask = PLL_BASE_LOCK, 329 .lock_enable = PLL_MISC_LOCK_ENABLE, 330 .mnp_bits = {5, 11, 3, 20}, 331 }, 332 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */ 333 { 334 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 335 .type = PLL_D2, 336 .base_reg = PLLD2_BASE, 337 .misc_reg = PLLD2_MISC, 338 .lock_mask = PLL_BASE_LOCK, 339 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 340 .iddq_reg = PLLD2_BASE, 341 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 342 .pdiv_table = pll12g_ssd_esd_map, 343 .mnp_bits = {8, 8, 4, 20}, 344 }, 345 /* refPLLe: */ 346 { 347 PLL(0, "pllREFE_out", "osc_div_clk"), 348 .type = PLL_REFE, 349 .base_reg = PLLRE_BASE, 350 .misc_reg = PLLRE_MISC, 351 .lock_mask = PLLRE_MISC_LOCK, 352 .lock_enable = PLLRE_MISC_LOCK_ENABLE, 353 .iddq_reg = PLLRE_MISC, 354 .iddq_mask = 1 << PLLRE_IDDQ_BIT, 355 .pdiv_table = pllrefe_map, 356 .mnp_bits = {8, 8, 4, 16}, 357 }, 358 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */ 359 { 360 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"), 361 .type = PLL_E, 362 .base_reg = PLLE_BASE, 363 .misc_reg = PLLE_MISC, 364 .lock_mask = PLLE_MISC_LOCK, 365 .lock_enable = PLLE_MISC_LOCK_ENABLE, 366 .mnp_bits = {8, 8, 4, 24}, 367 }, 368 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */ 369 { 370 PLL(0, "pllDP_out0", "pllDP_src"), 371 .type = PLL_DP, 372 .base_reg = PLLDP_BASE, 373 .misc_reg = PLLDP_MISC, 374 .lock_mask = PLL_BASE_LOCK, 375 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 376 .iddq_reg = PLLDP_BASE, 377 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 378 .pdiv_table = pll12g_ssd_esd_map, 379 .mnp_bits = {8, 8, 4, 20}, 380 }, 381 }; 382 383 static int tegra124_pll_init(struct clknode *clk, device_t dev); 384 static int tegra124_pll_set_gate(struct clknode *clk, bool enable); 385 static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled); 386 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq); 387 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, 388 uint64_t *fout, int flags, int *stop); 389 struct pll_sc { 390 device_t clkdev; 391 enum pll_type type; 392 uint32_t base_reg; 393 uint32_t misc_reg; 394 uint32_t lock_mask; 395 uint32_t lock_enable; 396 uint32_t iddq_reg; 397 uint32_t iddq_mask; 398 uint32_t flags; 399 struct pdiv_table *pdiv_table; 400 struct mnp_bits mnp_bits; 401 }; 402 403 static clknode_method_t tegra124_pll_methods[] = { 404 /* Device interface */ 405 CLKNODEMETHOD(clknode_init, tegra124_pll_init), 406 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate), 407 CLKNODEMETHOD(clknode_get_gate, tegra124_pll_get_gate), 408 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc), 409 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq), 410 CLKNODEMETHOD_END 411 }; 412 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods, 413 sizeof(struct pll_sc), clknode_class); 414 415 static int 416 pll_enable(struct pll_sc *sc) 417 { 418 uint32_t reg; 419 420 RD4(sc, sc->base_reg, ®); 421 if (sc->type != PLL_E) 422 reg &= ~PLL_BASE_BYPASS; 423 reg |= PLL_BASE_ENABLE; 424 WR4(sc, sc->base_reg, reg); 425 return (0); 426 } 427 428 static int 429 pll_disable(struct pll_sc *sc) 430 { 431 uint32_t reg; 432 433 RD4(sc, sc->base_reg, ®); 434 if (sc->type != PLL_E) 435 reg |= PLL_BASE_BYPASS; 436 reg &= ~PLL_BASE_ENABLE; 437 WR4(sc, sc->base_reg, reg); 438 return (0); 439 } 440 441 static uint32_t 442 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 443 { 444 struct pdiv_table *tbl; 445 446 tbl = sc->pdiv_table; 447 if (tbl == NULL) 448 return (ffs(p_div) - 1); 449 450 while (tbl->divider != 0) { 451 if (p_div <= tbl->divider) 452 return (tbl->value); 453 tbl++; 454 } 455 return (0xFFFFFFFF); 456 } 457 458 static uint32_t 459 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 460 { 461 struct pdiv_table *tbl; 462 463 tbl = sc->pdiv_table; 464 if (tbl == NULL) 465 return (1 << reg); 466 467 while (tbl->divider) { 468 if (reg == tbl->value) 469 return (tbl->divider); 470 tbl++; 471 } 472 return (0); 473 } 474 475 static uint32_t 476 get_masked(uint32_t val, uint32_t shift, uint32_t width) 477 { 478 479 return ((val >> shift) & ((1 << width) - 1)); 480 } 481 482 static uint32_t 483 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 484 { 485 486 val &= ~(((1 << width) - 1) << shift); 487 val |= (v & ((1 << width) - 1)) << shift; 488 return (val); 489 } 490 491 static void 492 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 493 { 494 uint32_t val; 495 struct mnp_bits *mnp_bits; 496 497 mnp_bits = &sc->mnp_bits; 498 RD4(sc, sc->base_reg, &val); 499 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 500 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 501 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 502 } 503 504 static uint32_t 505 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 506 uint32_t p) 507 { 508 struct mnp_bits *mnp_bits; 509 510 mnp_bits = &sc->mnp_bits; 511 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 512 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 513 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 514 return (val); 515 } 516 517 static bool 518 is_locked(struct pll_sc *sc) 519 { 520 uint32_t reg; 521 522 switch (sc->type) { 523 case PLL_REFE: 524 RD4(sc, sc->misc_reg, ®); 525 reg &= PLLRE_MISC_LOCK; 526 break; 527 528 case PLL_E: 529 RD4(sc, sc->misc_reg, ®); 530 reg &= PLLE_MISC_LOCK; 531 break; 532 533 default: 534 RD4(sc, sc->base_reg, ®); 535 reg &= PLL_BASE_LOCK; 536 break; 537 } 538 return (reg != 0); 539 } 540 541 static int 542 wait_for_lock(struct pll_sc *sc) 543 { 544 int i; 545 546 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 547 if (is_locked(sc)) 548 break; 549 DELAY(10); 550 } 551 if (i <= 0) { 552 printf("PLL lock timeout\n"); 553 return (ETIMEDOUT); 554 } 555 return (0); 556 } 557 558 static int 559 plle_enable(struct pll_sc *sc) 560 { 561 uint32_t reg; 562 int rv; 563 struct mnp_bits *mnp_bits; 564 uint32_t pll_m = 1; 565 uint32_t pll_n = 200; 566 uint32_t pll_p = 13; 567 uint32_t pll_cml = 13; 568 569 mnp_bits = &sc->mnp_bits; 570 571 /* Disable lock override. */ 572 RD4(sc, sc->base_reg, ®); 573 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 574 WR4(sc, sc->base_reg, reg); 575 576 RD4(sc, PLLE_AUX, ®); 577 reg |= PLLE_AUX_ENABLE_SWCTL; 578 reg &= ~PLLE_AUX_SEQ_ENABLE; 579 WR4(sc, PLLE_AUX, reg); 580 DELAY(10); 581 582 RD4(sc, sc->misc_reg, ®); 583 reg |= PLLE_MISC_LOCK_ENABLE; 584 reg |= PLLE_MISC_IDDQ_SWCTL; 585 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 586 reg |= PLLE_MISC_PTS; 587 reg |= PLLE_MISC_VREG_BG_CTRL_MASK; 588 reg |= PLLE_MISC_VREG_CTRL_MASK; 589 WR4(sc, sc->misc_reg, reg); 590 DELAY(10); 591 592 RD4(sc, PLLE_SS_CNTL, ®); 593 reg |= PLLE_SS_CNTL_DISABLE; 594 WR4(sc, PLLE_SS_CNTL, reg); 595 596 RD4(sc, sc->base_reg, ®); 597 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p); 598 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 599 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT; 600 WR4(sc, sc->base_reg, reg); 601 DELAY(10); 602 603 pll_enable(sc); 604 rv = wait_for_lock(sc); 605 if (rv != 0) 606 return (rv); 607 608 RD4(sc, PLLE_SS_CNTL, ®); 609 reg &= ~PLLE_SS_CNTL_SSCCENTER; 610 reg &= ~PLLE_SS_CNTL_SSCINVERT; 611 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK; 612 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL; 613 WR4(sc, PLLE_SS_CNTL, reg); 614 reg &= ~PLLE_SS_CNTL_SSCBYP; 615 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 616 WR4(sc, PLLE_SS_CNTL, reg); 617 DELAY(10); 618 619 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 620 WR4(sc, PLLE_SS_CNTL, reg); 621 DELAY(10); 622 623 /* HW control of brick pll. */ 624 RD4(sc, sc->misc_reg, ®); 625 reg &= ~PLLE_MISC_IDDQ_SWCTL; 626 WR4(sc, sc->misc_reg, reg); 627 628 RD4(sc, PLLE_AUX, ®); 629 reg |= PLLE_AUX_USE_LOCKDET; 630 reg |= PLLE_AUX_SEQ_START_STATE; 631 reg &= ~PLLE_AUX_ENABLE_SWCTL; 632 reg &= ~PLLE_AUX_SS_SWCTL; 633 WR4(sc, PLLE_AUX, reg); 634 reg |= PLLE_AUX_SEQ_START_STATE; 635 DELAY(10); 636 reg |= PLLE_AUX_SEQ_ENABLE; 637 WR4(sc, PLLE_AUX, reg); 638 639 RD4(sc, XUSBIO_PLL_CFG0, ®); 640 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 641 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE; 642 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 643 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 644 WR4(sc, XUSBIO_PLL_CFG0, reg); 645 DELAY(10); 646 647 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 648 WR4(sc, XUSBIO_PLL_CFG0, reg); 649 650 /* Enable HW control and unreset SATA PLL. */ 651 RD4(sc, SATA_PLL_CFG0, ®); 652 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 653 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 654 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 655 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 656 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 657 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 658 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 659 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 660 reg |= SATA_PLL_CFG0_SEQ_START_STATE; 661 WR4(sc, SATA_PLL_CFG0, reg); 662 DELAY(10); 663 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 664 WR4(sc, SATA_PLL_CFG0, reg); 665 666 /* Enable HW control of PCIe PLL. */ 667 RD4(sc, PCIE_PLL_CFG0, ®); 668 reg |= PCIE_PLL_CFG0_SEQ_ENABLE; 669 WR4(sc, PCIE_PLL_CFG0, reg); 670 671 return (0); 672 } 673 674 static int 675 tegra124_pll_set_gate(struct clknode *clknode, bool enable) 676 { 677 int rv; 678 struct pll_sc *sc; 679 680 sc = clknode_get_softc(clknode); 681 if (enable == 0) { 682 rv = pll_disable(sc); 683 return(rv); 684 } 685 686 if (sc->type == PLL_E) 687 rv = plle_enable(sc); 688 else 689 rv = pll_enable(sc); 690 return (rv); 691 } 692 693 static int 694 tegra124_pll_get_gate(struct clknode *clknode, bool *enabled) 695 { 696 uint32_t reg; 697 struct pll_sc *sc; 698 699 sc = clknode_get_softc(clknode); 700 RD4(sc, sc->base_reg, ®); 701 *enabled = reg & PLL_BASE_ENABLE ? true: false; 702 WR4(sc, sc->base_reg, reg); 703 return (0); 704 } 705 706 static int 707 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 708 uint32_t m, uint32_t n, uint32_t p) 709 { 710 uint32_t reg; 711 struct mnp_bits *mnp_bits; 712 int rv; 713 714 mnp_bits = &sc->mnp_bits; 715 if (m >= (1 << mnp_bits->m_width)) 716 return (ERANGE); 717 if (n >= (1 << mnp_bits->n_width)) 718 return (ERANGE); 719 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 720 return (ERANGE); 721 722 if (flags & CLK_SET_DRYRUN) { 723 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 724 (*fout != (((fin / m) * n) /p))) 725 return (ERANGE); 726 727 *fout = ((fin / m) * n) /p; 728 729 return (0); 730 } 731 732 pll_disable(sc); 733 734 /* take pll out of IDDQ */ 735 if (sc->iddq_reg != 0) 736 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 737 738 RD4(sc, sc->base_reg, ®); 739 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 740 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 741 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 742 mnp_bits->p_width); 743 WR4(sc, sc->base_reg, reg); 744 745 /* Enable PLL. */ 746 RD4(sc, sc->base_reg, ®); 747 reg |= PLL_BASE_ENABLE; 748 WR4(sc, sc->base_reg, reg); 749 750 /* Enable lock detection. */ 751 RD4(sc, sc->misc_reg, ®); 752 reg |= sc->lock_enable; 753 WR4(sc, sc->misc_reg, reg); 754 755 rv = wait_for_lock(sc); 756 if (rv != 0) { 757 /* Disable PLL */ 758 RD4(sc, sc->base_reg, ®); 759 reg &= ~PLL_BASE_ENABLE; 760 WR4(sc, sc->base_reg, reg); 761 return (rv); 762 } 763 RD4(sc, sc->misc_reg, ®); 764 765 pll_enable(sc); 766 *fout = ((fin / m) * n) / p; 767 return 0; 768 } 769 770 static int 771 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 772 { 773 uint32_t m, n, p; 774 775 p = 1; 776 m = 5; 777 n = (*fout * p * m + fin / 2)/ fin; 778 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 779 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 780 } 781 782 static int 783 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 784 { 785 uint32_t m, n, p; 786 787 p = 2; 788 m = 1; 789 n = (*fout * p * m + fin / 2)/ fin; 790 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 791 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 792 } 793 794 /* 795 * PLLD2 is used as source for pixel clock for HDMI. 796 * We must be able to set it frequency very flexibly and 797 * precisely (within 5% tolerance limit allowed by HDMI specs). 798 * 799 * For this reason, it is necessary to search the full state space. 800 * Fortunately, thanks to early cycle terminations, performance 801 * is within acceptable limits. 802 */ 803 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ 804 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */ 805 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */ 806 #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */ 807 808 static int 809 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 810 { 811 uint32_t m, n, p; 812 uint32_t best_m, best_n, best_p; 813 uint64_t vco, pfd; 814 int64_t err, best_err; 815 struct mnp_bits *mnp_bits; 816 struct pdiv_table *tbl; 817 int p_idx, rv; 818 819 mnp_bits = &sc->mnp_bits; 820 tbl = sc->pdiv_table; 821 best_err = INT64_MAX; 822 823 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { 824 p = tbl[p_idx].divider; 825 826 /* Check constraints */ 827 vco = *fout * p; 828 if (vco < PLLD2_VCO_MIN) 829 continue; 830 if (vco > PLLD2_VCO_MAX) 831 break; 832 833 for (m = 1; m < (1 << mnp_bits->m_width); m++) { 834 n = (*fout * p * m + fin / 2) / fin; 835 836 /* Check constraints */ 837 if (n == 0) 838 continue; 839 if (n >= (1 << mnp_bits->n_width)) 840 break; 841 vco = (fin * n) / m; 842 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) 843 continue; 844 pfd = fin / m; 845 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) 846 continue; 847 848 /* Constraints passed, save best result */ 849 err = *fout - vco / p; 850 if (err < 0) 851 err = -err; 852 if (err < best_err) { 853 best_err = err; 854 best_p = p; 855 best_m = m; 856 best_n = n; 857 } 858 if (err == 0) 859 goto done; 860 } 861 } 862 done: 863 /* 864 * HDMI specification allows 5% pixel clock tolerance, 865 * we will by a slightly stricter 866 */ 867 if (best_err > ((*fout * 100) / 4)) 868 return (ERANGE); 869 870 if (flags & CLK_SET_DRYRUN) 871 return (0); 872 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); 873 /* XXXX Panic for rv == ERANGE ? */ 874 return (rv); 875 } 876 877 static int 878 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 879 { 880 uint32_t m, n, p; 881 882 m = 1; 883 p = 1; 884 n = *fout * p * m / fin; 885 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 886 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 887 } 888 889 static int 890 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 891 { 892 uint32_t reg; 893 uint32_t m, n, p; 894 struct mnp_bits *mnp_bits; 895 int rv; 896 897 mnp_bits = &sc->mnp_bits; 898 899 p = 1; 900 m = 1; 901 n = (*fout * p * m + fin / 2)/ fin; 902 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 903 904 if (m >= (1 << mnp_bits->m_width)) 905 return (ERANGE); 906 if (n >= (1 << mnp_bits->n_width)) 907 return (ERANGE); 908 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 909 return (ERANGE); 910 911 if (flags & CLK_SET_DRYRUN) { 912 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 913 (*fout != (((fin / m) * n) /p))) 914 return (ERANGE); 915 *fout = ((fin / m) * n) /p; 916 return (0); 917 } 918 919 /* PLLX doesn't have bypass, disable it first. */ 920 RD4(sc, sc->base_reg, ®); 921 reg &= ~PLL_BASE_ENABLE; 922 WR4(sc, sc->base_reg, reg); 923 924 /* Set PLL. */ 925 RD4(sc, sc->base_reg, ®); 926 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 927 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 928 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 929 mnp_bits->p_width); 930 WR4(sc, sc->base_reg, reg); 931 RD4(sc, sc->base_reg, ®); 932 DELAY(100); 933 934 /* Enable lock detection. */ 935 RD4(sc, sc->misc_reg, ®); 936 reg |= sc->lock_enable; 937 WR4(sc, sc->misc_reg, reg); 938 939 /* Enable PLL. */ 940 RD4(sc, sc->base_reg, ®); 941 reg |= PLL_BASE_ENABLE; 942 WR4(sc, sc->base_reg, reg); 943 944 rv = wait_for_lock(sc); 945 if (rv != 0) { 946 /* Disable PLL */ 947 RD4(sc, sc->base_reg, ®); 948 reg &= ~PLL_BASE_ENABLE; 949 WR4(sc, sc->base_reg, reg); 950 return (rv); 951 } 952 RD4(sc, sc->misc_reg, ®); 953 954 *fout = ((fin / m) * n) / p; 955 return (0); 956 } 957 958 static int 959 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 960 int flags, int *stop) 961 { 962 *stop = 1; 963 int rv; 964 struct pll_sc *sc; 965 966 sc = clknode_get_softc(clknode); 967 dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__, 968 clknode_get_name(clknode), *fout, fin); 969 switch (sc->type) { 970 case PLL_A: 971 rv = plla_set_freq(sc, fin, fout, flags); 972 break; 973 case PLL_C: 974 rv = pllc_set_freq(sc, fin, fout, flags); 975 break; 976 case PLL_D2: 977 rv = plld2_set_freq(sc, fin, fout, flags); 978 break; 979 980 case PLL_REFE: 981 rv = pllrefe_set_freq(sc, fin, fout, flags); 982 break; 983 984 case PLL_X: 985 rv = pllx_set_freq(sc, fin, fout, flags); 986 break; 987 988 case PLL_U: 989 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 990 rv = 0; 991 else 992 rv = ERANGE; 993 break; 994 default: 995 rv = ENXIO; 996 break; 997 } 998 999 return (rv); 1000 } 1001 1002 static int 1003 tegra124_pll_init(struct clknode *clk, device_t dev) 1004 { 1005 struct pll_sc *sc; 1006 uint32_t reg; 1007 1008 sc = clknode_get_softc(clk); 1009 1010 /* If PLL is enabled, enable lock detect too. */ 1011 RD4(sc, sc->base_reg, ®); 1012 if (reg & PLL_BASE_ENABLE) { 1013 RD4(sc, sc->misc_reg, ®); 1014 reg |= sc->lock_enable; 1015 WR4(sc, sc->misc_reg, reg); 1016 } 1017 if (sc->type == PLL_REFE) { 1018 RD4(sc, sc->misc_reg, ®); 1019 reg &= ~(1 << 29); /* Diasble lock override */ 1020 WR4(sc, sc->misc_reg, reg); 1021 } 1022 1023 clknode_init_parent_idx(clk, 0); 1024 return(0); 1025 } 1026 1027 static int 1028 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq) 1029 { 1030 struct pll_sc *sc; 1031 uint32_t m, n, p, pr; 1032 uint32_t reg, misc_reg; 1033 int locked; 1034 1035 sc = clknode_get_softc(clk); 1036 1037 RD4(sc, sc->base_reg, ®); 1038 RD4(sc, sc->misc_reg, &misc_reg); 1039 1040 get_divisors(sc, &m, &n, &pr); 1041 if (sc->type != PLL_E) 1042 p = reg_to_pdiv(sc, pr); 1043 else 1044 p = 2 * (pr - 1); 1045 locked = is_locked(sc); 1046 1047 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 1048 "e: %d, r: %d, o: %d - %s\n", __func__, 1049 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 1050 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 1051 locked ? "locked" : "unlocked"); 1052 1053 if ((m == 0) || (n == 0) || (p == 0)) { 1054 *freq = 0; 1055 return (EINVAL); 1056 } 1057 *freq = ((*freq / m) * n) / p; 1058 return (0); 1059 } 1060 1061 static int 1062 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 1063 { 1064 struct clknode *clk; 1065 struct pll_sc *sc; 1066 1067 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef); 1068 if (clk == NULL) 1069 return (ENXIO); 1070 1071 sc = clknode_get_softc(clk); 1072 sc->clkdev = clknode_get_device(clk); 1073 sc->type = clkdef->type; 1074 sc->base_reg = clkdef->base_reg; 1075 sc->misc_reg = clkdef->misc_reg; 1076 sc->lock_mask = clkdef->lock_mask; 1077 sc->lock_enable = clkdef->lock_enable; 1078 sc->iddq_reg = clkdef->iddq_reg; 1079 sc->iddq_mask = clkdef->iddq_mask; 1080 sc->flags = clkdef->flags; 1081 sc->pdiv_table = clkdef->pdiv_table; 1082 sc->mnp_bits = clkdef->mnp_bits; 1083 clknode_register(clkdom, clk); 1084 return (0); 1085 } 1086 1087 static void config_utmi_pll(struct tegra124_car_softc *sc) 1088 { 1089 uint32_t reg; 1090 /* 1091 * XXX Simplified UTMIP settings for 12MHz base clock. 1092 */ 1093 #define ENABLE_DELAY_COUNT 0x02 1094 #define STABLE_COUNT 0x2F 1095 #define ACTIVE_DELAY_COUNT 0x04 1096 #define XTAL_FREQ_COUNT 0x76 1097 1098 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1099 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1100 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1101 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1102 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1103 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1104 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1105 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1106 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1107 1108 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1109 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1110 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1111 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1112 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1113 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1114 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1115 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1116 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1117 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1118 1119 /* Prepare UTMIP requencer. */ 1120 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1121 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1122 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1123 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1124 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1125 1126 /* Powerup UTMIP. */ 1127 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1128 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1129 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1130 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1131 DELAY(10); 1132 1133 /* SW override for UTMIPLL */ 1134 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1135 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1136 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1137 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1138 DELAY(10); 1139 1140 /* HW control of UTMIPLL. */ 1141 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1142 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1143 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1144 } 1145 1146 void 1147 tegra124_init_plls(struct tegra124_car_softc *sc) 1148 { 1149 int i, rv; 1150 1151 for (i = 0; i < nitems(pll_clks); i++) { 1152 rv = pll_register(sc->clkdom, pll_clks + i); 1153 if (rv != 0) 1154 panic("pll_register failed"); 1155 } 1156 config_utmi_pll(sc); 1157 1158 } 1159