1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/lock.h> 32 #include <sys/mutex.h> 33 #include <sys/rman.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/extres/clk/clk.h> 38 39 #include <dt-bindings/clock/tegra124-car.h> 40 #include "tegra124_car.h" 41 42 /* #define TEGRA_PLL_DEBUG */ 43 #ifdef TEGRA_PLL_DEBUG 44 #define dprintf(...) printf(__VA_ARGS__) 45 #else 46 #define dprintf(...) 47 #endif 48 49 /* All PLLs. */ 50 enum pll_type { 51 PLL_M, 52 PLL_X, 53 PLL_C, 54 PLL_C2, 55 PLL_C3, 56 PLL_C4, 57 PLL_P, 58 PLL_A, 59 PLL_U, 60 PLL_D, 61 PLL_D2, 62 PLL_DP, 63 PLL_E, 64 PLL_REFE}; 65 66 /* Common base register bits. */ 67 #define PLL_BASE_BYPASS (1U << 31) 68 #define PLL_BASE_ENABLE (1 << 30) 69 #define PLL_BASE_REFDISABLE (1 << 29) 70 #define PLL_BASE_LOCK (1 << 27) 71 #define PLL_BASE_DIVM_SHIFT 0 72 #define PLL_BASE_DIVN_SHIFT 8 73 74 #define PLLRE_MISC_LOCK (1 << 24) 75 76 #define PLL_MISC_LOCK_ENABLE (1 << 18) 77 #define PLLC_MISC_LOCK_ENABLE (1 << 24) 78 #define PLLDU_MISC_LOCK_ENABLE (1 << 22) 79 #define PLLRE_MISC_LOCK_ENABLE (1 << 30) 80 #define PLLSS_MISC_LOCK_ENABLE (1 << 30) 81 82 #define PLLC_IDDQ_BIT 26 83 #define PLLX_IDDQ_BIT 3 84 #define PLLRE_IDDQ_BIT 16 85 #define PLLSS_IDDQ_BIT 19 86 87 #define PLL_LOCK_TIMEOUT 5000 88 89 /* Post divider <-> register value mapping. */ 90 struct pdiv_table { 91 uint32_t divider; /* real divider */ 92 uint32_t value; /* register value */ 93 }; 94 95 /* Bits definition of M, N and P fields. */ 96 struct mnp_bits { 97 uint32_t m_width; 98 uint32_t n_width; 99 uint32_t p_width; 100 uint32_t p_shift; 101 }; 102 103 struct clk_pll_def { 104 struct clknode_init_def clkdef; 105 enum pll_type type; 106 uint32_t base_reg; 107 uint32_t misc_reg; 108 uint32_t lock_mask; 109 uint32_t lock_enable; 110 uint32_t iddq_reg; 111 uint32_t iddq_mask; 112 uint32_t flags; 113 struct pdiv_table *pdiv_table; 114 struct mnp_bits mnp_bits; 115 }; 116 117 #define PLL(_id, cname, pname) \ 118 .clkdef.id = _id, \ 119 .clkdef.name = cname, \ 120 .clkdef.parent_names = (const char *[]){pname}, \ 121 .clkdef.parent_cnt = 1, \ 122 .clkdef.flags = CLK_NODE_STATIC_STRINGS 123 124 /* Tegra K1 PLLs 125 PLLM: Clock source for EMC 2x clock 126 PLLX: Clock source for the fast CPU cluster and the shadow CPU 127 PLLC: Clock source for general use 128 PLLC2: Clock source for engine scaling 129 PLLC3: Clock source for engine scaling 130 PLLC4: Clock source for ISP/VI units 131 PLLP: Clock source for most peripherals 132 PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) 133 PLLU: Clock source for USB PHY, provides 12/60/480 MHz 134 PLLD: Clock sources for the DSI and display subsystem 135 PLLD2: Clock sources for the DSI and display subsystem 136 refPLLe: 137 PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) 138 PLLDP: Clock source for eDP/LVDS (spread spectrum) 139 140 DFLLCPU: DFLL clock source for the fast CPU cluster 141 GPCPLL: Clock source for the GPU 142 */ 143 144 static struct pdiv_table pllm_map[] = { 145 {1, 0}, 146 {2, 1}, 147 {0, 0} 148 }; 149 150 static struct pdiv_table pllxc_map[] = { 151 { 1, 0}, 152 { 2, 1}, 153 { 3, 2}, 154 { 4, 3}, 155 { 5, 4}, 156 { 6, 5}, 157 { 8, 6}, 158 {10, 7}, 159 {12, 8}, 160 {16, 9}, 161 {12, 10}, 162 {16, 11}, 163 {20, 12}, 164 {24, 13}, 165 {32, 14}, 166 { 0, 0} 167 }; 168 169 static struct pdiv_table pllc_map[] = { 170 { 1, 0}, 171 { 2, 1}, 172 { 3, 2}, 173 { 4, 3}, 174 { 6, 4}, 175 { 8, 5}, 176 {12, 6}, 177 {16, 7}, 178 { 0, 0} 179 }; 180 181 static struct pdiv_table pll12g_ssd_esd_map[] = { 182 { 1, 0}, 183 { 2, 1}, 184 { 3, 2}, 185 { 4, 3}, 186 { 5, 4}, 187 { 6, 5}, 188 { 8, 6}, 189 {10, 7}, 190 {12, 8}, 191 {16, 9}, 192 {12, 10}, 193 {16, 11}, 194 {20, 12}, 195 {24, 13}, 196 {32, 14}, 197 { 0, 0} 198 }; 199 200 static struct pdiv_table pllu_map[] = { 201 {1, 1}, 202 {2, 0}, 203 {0, 0} 204 }; 205 206 static struct pdiv_table pllrefe_map[] = { 207 {1, 0}, 208 {2, 1}, 209 {3, 2}, 210 {4, 3}, 211 {5, 4}, 212 {6, 5}, 213 {0, 0}, 214 }; 215 216 static struct clk_pll_def pll_clks[] = { 217 /* PLLM: 880 MHz Clock source for EMC 2x clock */ 218 { 219 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"), 220 .type = PLL_M, 221 .base_reg = PLLM_BASE, 222 .misc_reg = PLLM_MISC, 223 .lock_mask = PLL_BASE_LOCK, 224 .lock_enable = PLL_MISC_LOCK_ENABLE, 225 .pdiv_table = pllm_map, 226 .mnp_bits = {8, 8, 1, 20}, 227 }, 228 /* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */ 229 { 230 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"), 231 .type = PLL_X, 232 .base_reg = PLLX_BASE, 233 .misc_reg = PLLX_MISC, 234 .lock_mask = PLL_BASE_LOCK, 235 .lock_enable = PLL_MISC_LOCK_ENABLE, 236 .iddq_reg = PLLX_MISC3, 237 .iddq_mask = 1 << PLLX_IDDQ_BIT, 238 .pdiv_table = pllxc_map, 239 .mnp_bits = {8, 8, 4, 20}, 240 }, 241 /* PLLC: 600 MHz Clock source for general use */ 242 { 243 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"), 244 .type = PLL_C, 245 .base_reg = PLLC_BASE, 246 .misc_reg = PLLC_MISC, 247 .lock_mask = PLL_BASE_LOCK, 248 .lock_enable = PLLC_MISC_LOCK_ENABLE, 249 .iddq_reg = PLLC_MISC, 250 .iddq_mask = 1 << PLLC_IDDQ_BIT, 251 .pdiv_table = pllc_map, 252 .mnp_bits = {8, 8, 4, 20}, 253 }, 254 /* PLLC2: 600 MHz Clock source for engine scaling */ 255 { 256 PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"), 257 .type = PLL_C2, 258 .base_reg = PLLC2_BASE, 259 .misc_reg = PLLC2_MISC, 260 .lock_mask = PLL_BASE_LOCK, 261 .lock_enable = PLL_MISC_LOCK_ENABLE, 262 .pdiv_table = pllc_map, 263 .mnp_bits = {2, 8, 3, 20}, 264 }, 265 /* PLLC3: 600 MHz Clock source for engine scaling */ 266 { 267 PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"), 268 .type = PLL_C3, 269 .base_reg = PLLC3_BASE, 270 .misc_reg = PLLC3_MISC, 271 .lock_mask = PLL_BASE_LOCK, 272 .lock_enable = PLL_MISC_LOCK_ENABLE, 273 .pdiv_table = pllc_map, 274 .mnp_bits = {2, 8, 3, 20}, 275 }, 276 /* PLLC4: 600 MHz Clock source for ISP/VI units */ 277 { 278 PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"), 279 .type = PLL_C4, 280 .base_reg = PLLC4_BASE, 281 .misc_reg = PLLC4_MISC, 282 .lock_mask = PLL_BASE_LOCK, 283 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 284 .iddq_reg = PLLC4_BASE, 285 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 286 .pdiv_table = pll12g_ssd_esd_map, 287 .mnp_bits = {8, 8, 4, 20}, 288 }, 289 /* PLLP: 408 MHz Clock source for most peripherals */ 290 { 291 PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"), 292 .type = PLL_P, 293 .base_reg = PLLP_BASE, 294 .misc_reg = PLLP_MISC, 295 .lock_mask = PLL_BASE_LOCK, 296 .lock_enable = PLL_MISC_LOCK_ENABLE, 297 .mnp_bits = {5, 10, 3, 20}, 298 }, 299 /* PLLA: Audio clock sources: (11.2896 MHz, 12.288 MHz, 24.576 MHz) */ 300 { 301 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"), 302 .type = PLL_A, 303 .base_reg = PLLA_BASE, 304 .misc_reg = PLLA_MISC, 305 .lock_mask = PLL_BASE_LOCK, 306 .lock_enable = PLL_MISC_LOCK_ENABLE, 307 .mnp_bits = {5, 10, 3, 20}, 308 }, 309 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */ 310 { 311 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"), 312 .type = PLL_U, 313 .base_reg = PLLU_BASE, 314 .misc_reg = PLLU_MISC, 315 .lock_mask = PLL_BASE_LOCK, 316 .lock_enable = PLLDU_MISC_LOCK_ENABLE, 317 .pdiv_table = pllu_map, 318 .mnp_bits = {5, 10, 1, 20}, 319 }, 320 /* PLLD: 600 MHz Clock sources for the DSI and display subsystem */ 321 { 322 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"), 323 .type = PLL_D, 324 .base_reg = PLLD_BASE, 325 .misc_reg = PLLD_MISC, 326 .lock_mask = PLL_BASE_LOCK, 327 .lock_enable = PLL_MISC_LOCK_ENABLE, 328 .mnp_bits = {5, 11, 3, 20}, 329 }, 330 /* PLLD2: 600 MHz Clock sources for the DSI and display subsystem */ 331 { 332 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"), 333 .type = PLL_D2, 334 .base_reg = PLLD2_BASE, 335 .misc_reg = PLLD2_MISC, 336 .lock_mask = PLL_BASE_LOCK, 337 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 338 .iddq_reg = PLLD2_BASE, 339 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 340 .pdiv_table = pll12g_ssd_esd_map, 341 .mnp_bits = {8, 8, 4, 20}, 342 }, 343 /* refPLLe: */ 344 { 345 PLL(0, "pllREFE_out", "osc_div_clk"), 346 .type = PLL_REFE, 347 .base_reg = PLLRE_BASE, 348 .misc_reg = PLLRE_MISC, 349 .lock_mask = PLLRE_MISC_LOCK, 350 .lock_enable = PLLRE_MISC_LOCK_ENABLE, 351 .iddq_reg = PLLRE_MISC, 352 .iddq_mask = 1 << PLLRE_IDDQ_BIT, 353 .pdiv_table = pllrefe_map, 354 .mnp_bits = {8, 8, 4, 16}, 355 }, 356 /* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */ 357 { 358 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"), 359 .type = PLL_E, 360 .base_reg = PLLE_BASE, 361 .misc_reg = PLLE_MISC, 362 .lock_mask = PLLE_MISC_LOCK, 363 .lock_enable = PLLE_MISC_LOCK_ENABLE, 364 .mnp_bits = {8, 8, 4, 24}, 365 }, 366 /* PLLDP: 600 MHz Clock source for eDP/LVDS (spread spectrum) */ 367 { 368 PLL(0, "pllDP_out0", "pllDP_src"), 369 .type = PLL_DP, 370 .base_reg = PLLDP_BASE, 371 .misc_reg = PLLDP_MISC, 372 .lock_mask = PLL_BASE_LOCK, 373 .lock_enable = PLLSS_MISC_LOCK_ENABLE, 374 .iddq_reg = PLLDP_BASE, 375 .iddq_mask = 1 << PLLSS_IDDQ_BIT, 376 .pdiv_table = pll12g_ssd_esd_map, 377 .mnp_bits = {8, 8, 4, 20}, 378 }, 379 }; 380 381 static int tegra124_pll_init(struct clknode *clk, device_t dev); 382 static int tegra124_pll_set_gate(struct clknode *clk, bool enable); 383 static int tegra124_pll_get_gate(struct clknode *clk, bool *enabled); 384 static int tegra124_pll_recalc(struct clknode *clk, uint64_t *freq); 385 static int tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, 386 uint64_t *fout, int flags, int *stop); 387 struct pll_sc { 388 device_t clkdev; 389 enum pll_type type; 390 uint32_t base_reg; 391 uint32_t misc_reg; 392 uint32_t lock_mask; 393 uint32_t lock_enable; 394 uint32_t iddq_reg; 395 uint32_t iddq_mask; 396 uint32_t flags; 397 struct pdiv_table *pdiv_table; 398 struct mnp_bits mnp_bits; 399 }; 400 401 static clknode_method_t tegra124_pll_methods[] = { 402 /* Device interface */ 403 CLKNODEMETHOD(clknode_init, tegra124_pll_init), 404 CLKNODEMETHOD(clknode_set_gate, tegra124_pll_set_gate), 405 CLKNODEMETHOD(clknode_get_gate, tegra124_pll_get_gate), 406 CLKNODEMETHOD(clknode_recalc_freq, tegra124_pll_recalc), 407 CLKNODEMETHOD(clknode_set_freq, tegra124_pll_set_freq), 408 CLKNODEMETHOD_END 409 }; 410 DEFINE_CLASS_1(tegra124_pll, tegra124_pll_class, tegra124_pll_methods, 411 sizeof(struct pll_sc), clknode_class); 412 413 static int 414 pll_enable(struct pll_sc *sc) 415 { 416 uint32_t reg; 417 418 RD4(sc, sc->base_reg, ®); 419 if (sc->type != PLL_E) 420 reg &= ~PLL_BASE_BYPASS; 421 reg |= PLL_BASE_ENABLE; 422 WR4(sc, sc->base_reg, reg); 423 return (0); 424 } 425 426 static int 427 pll_disable(struct pll_sc *sc) 428 { 429 uint32_t reg; 430 431 RD4(sc, sc->base_reg, ®); 432 if (sc->type != PLL_E) 433 reg |= PLL_BASE_BYPASS; 434 reg &= ~PLL_BASE_ENABLE; 435 WR4(sc, sc->base_reg, reg); 436 return (0); 437 } 438 439 static uint32_t 440 pdiv_to_reg(struct pll_sc *sc, uint32_t p_div) 441 { 442 struct pdiv_table *tbl; 443 444 tbl = sc->pdiv_table; 445 if (tbl == NULL) 446 return (ffs(p_div) - 1); 447 448 while (tbl->divider != 0) { 449 if (p_div <= tbl->divider) 450 return (tbl->value); 451 tbl++; 452 } 453 return (0xFFFFFFFF); 454 } 455 456 static uint32_t 457 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) 458 { 459 struct pdiv_table *tbl; 460 461 tbl = sc->pdiv_table; 462 if (tbl == NULL) 463 return (1 << reg); 464 465 while (tbl->divider) { 466 if (reg == tbl->value) 467 return (tbl->divider); 468 tbl++; 469 } 470 return (0); 471 } 472 473 static uint32_t 474 get_masked(uint32_t val, uint32_t shift, uint32_t width) 475 { 476 477 return ((val >> shift) & ((1 << width) - 1)); 478 } 479 480 static uint32_t 481 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) 482 { 483 484 val &= ~(((1 << width) - 1) << shift); 485 val |= (v & ((1 << width) - 1)) << shift; 486 return (val); 487 } 488 489 static void 490 get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p) 491 { 492 uint32_t val; 493 struct mnp_bits *mnp_bits; 494 495 mnp_bits = &sc->mnp_bits; 496 RD4(sc, sc->base_reg, &val); 497 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 498 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 499 *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width); 500 } 501 502 static uint32_t 503 set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n, 504 uint32_t p) 505 { 506 struct mnp_bits *mnp_bits; 507 508 mnp_bits = &sc->mnp_bits; 509 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 510 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 511 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); 512 return (val); 513 } 514 515 static bool 516 is_locked(struct pll_sc *sc) 517 { 518 uint32_t reg; 519 520 switch (sc->type) { 521 case PLL_REFE: 522 RD4(sc, sc->misc_reg, ®); 523 reg &= PLLRE_MISC_LOCK; 524 break; 525 526 case PLL_E: 527 RD4(sc, sc->misc_reg, ®); 528 reg &= PLLE_MISC_LOCK; 529 break; 530 531 default: 532 RD4(sc, sc->base_reg, ®); 533 reg &= PLL_BASE_LOCK; 534 break; 535 } 536 return (reg != 0); 537 } 538 539 static int 540 wait_for_lock(struct pll_sc *sc) 541 { 542 int i; 543 544 for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) { 545 if (is_locked(sc)) 546 break; 547 DELAY(10); 548 } 549 if (i <= 0) { 550 printf("PLL lock timeout\n"); 551 return (ETIMEDOUT); 552 } 553 return (0); 554 } 555 556 static int 557 plle_enable(struct pll_sc *sc) 558 { 559 uint32_t reg; 560 int rv; 561 uint32_t pll_m = 1; 562 uint32_t pll_n = 200; 563 uint32_t pll_p = 13; 564 uint32_t pll_cml = 13; 565 566 /* Disable lock override. */ 567 RD4(sc, sc->base_reg, ®); 568 reg &= ~PLLE_BASE_LOCK_OVERRIDE; 569 WR4(sc, sc->base_reg, reg); 570 571 RD4(sc, PLLE_AUX, ®); 572 reg |= PLLE_AUX_ENABLE_SWCTL; 573 reg &= ~PLLE_AUX_SEQ_ENABLE; 574 WR4(sc, PLLE_AUX, reg); 575 DELAY(10); 576 577 RD4(sc, sc->misc_reg, ®); 578 reg |= PLLE_MISC_LOCK_ENABLE; 579 reg |= PLLE_MISC_IDDQ_SWCTL; 580 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; 581 reg |= PLLE_MISC_PTS; 582 reg |= PLLE_MISC_VREG_BG_CTRL_MASK; 583 reg |= PLLE_MISC_VREG_CTRL_MASK; 584 WR4(sc, sc->misc_reg, reg); 585 DELAY(10); 586 587 RD4(sc, PLLE_SS_CNTL, ®); 588 reg |= PLLE_SS_CNTL_DISABLE; 589 WR4(sc, PLLE_SS_CNTL, reg); 590 591 RD4(sc, sc->base_reg, ®); 592 reg = set_divisors(sc, reg, pll_m, pll_n, pll_p); 593 reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); 594 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT; 595 WR4(sc, sc->base_reg, reg); 596 DELAY(10); 597 598 pll_enable(sc); 599 rv = wait_for_lock(sc); 600 if (rv != 0) 601 return (rv); 602 603 RD4(sc, PLLE_SS_CNTL, ®); 604 reg &= ~PLLE_SS_CNTL_SSCCENTER; 605 reg &= ~PLLE_SS_CNTL_SSCINVERT; 606 reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK; 607 reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL; 608 WR4(sc, PLLE_SS_CNTL, reg); 609 reg &= ~PLLE_SS_CNTL_SSCBYP; 610 reg &= ~PLLE_SS_CNTL_BYPASS_SS; 611 WR4(sc, PLLE_SS_CNTL, reg); 612 DELAY(10); 613 614 reg &= ~PLLE_SS_CNTL_INTERP_RESET; 615 WR4(sc, PLLE_SS_CNTL, reg); 616 DELAY(10); 617 618 /* HW control of brick pll. */ 619 RD4(sc, sc->misc_reg, ®); 620 reg &= ~PLLE_MISC_IDDQ_SWCTL; 621 WR4(sc, sc->misc_reg, reg); 622 623 RD4(sc, PLLE_AUX, ®); 624 reg |= PLLE_AUX_USE_LOCKDET; 625 reg |= PLLE_AUX_SEQ_START_STATE; 626 reg &= ~PLLE_AUX_ENABLE_SWCTL; 627 reg &= ~PLLE_AUX_SS_SWCTL; 628 WR4(sc, PLLE_AUX, reg); 629 reg |= PLLE_AUX_SEQ_START_STATE; 630 DELAY(10); 631 reg |= PLLE_AUX_SEQ_ENABLE; 632 WR4(sc, PLLE_AUX, reg); 633 634 RD4(sc, XUSBIO_PLL_CFG0, ®); 635 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; 636 reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE; 637 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; 638 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; 639 WR4(sc, XUSBIO_PLL_CFG0, reg); 640 DELAY(10); 641 642 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 643 WR4(sc, XUSBIO_PLL_CFG0, reg); 644 645 /* Enable HW control and unreset SATA PLL. */ 646 RD4(sc, SATA_PLL_CFG0, ®); 647 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 648 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; 649 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; 650 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; 651 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; 652 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; 653 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; 654 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; 655 reg |= SATA_PLL_CFG0_SEQ_START_STATE; 656 WR4(sc, SATA_PLL_CFG0, reg); 657 DELAY(10); 658 reg |= SATA_PLL_CFG0_SEQ_ENABLE; 659 WR4(sc, SATA_PLL_CFG0, reg); 660 661 /* Enable HW control of PCIe PLL. */ 662 RD4(sc, PCIE_PLL_CFG0, ®); 663 reg |= PCIE_PLL_CFG0_SEQ_ENABLE; 664 WR4(sc, PCIE_PLL_CFG0, reg); 665 666 return (0); 667 } 668 669 static int 670 tegra124_pll_set_gate(struct clknode *clknode, bool enable) 671 { 672 int rv; 673 struct pll_sc *sc; 674 675 sc = clknode_get_softc(clknode); 676 if (enable == 0) { 677 rv = pll_disable(sc); 678 return(rv); 679 } 680 681 if (sc->type == PLL_E) 682 rv = plle_enable(sc); 683 else 684 rv = pll_enable(sc); 685 return (rv); 686 } 687 688 static int 689 tegra124_pll_get_gate(struct clknode *clknode, bool *enabled) 690 { 691 uint32_t reg; 692 struct pll_sc *sc; 693 694 sc = clknode_get_softc(clknode); 695 RD4(sc, sc->base_reg, ®); 696 *enabled = reg & PLL_BASE_ENABLE ? true: false; 697 WR4(sc, sc->base_reg, reg); 698 return (0); 699 } 700 701 static int 702 pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags, 703 uint32_t m, uint32_t n, uint32_t p) 704 { 705 uint32_t reg; 706 struct mnp_bits *mnp_bits; 707 int rv; 708 709 mnp_bits = &sc->mnp_bits; 710 if (m >= (1 << mnp_bits->m_width)) 711 return (ERANGE); 712 if (n >= (1 << mnp_bits->n_width)) 713 return (ERANGE); 714 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 715 return (ERANGE); 716 717 if (flags & CLK_SET_DRYRUN) { 718 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 719 (*fout != (((fin / m) * n) /p))) 720 return (ERANGE); 721 722 *fout = ((fin / m) * n) /p; 723 724 return (0); 725 } 726 727 pll_disable(sc); 728 729 /* take pll out of IDDQ */ 730 if (sc->iddq_reg != 0) 731 MD4(sc, sc->iddq_reg, sc->iddq_mask, 0); 732 733 RD4(sc, sc->base_reg, ®); 734 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 735 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 736 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 737 mnp_bits->p_width); 738 WR4(sc, sc->base_reg, reg); 739 740 /* Enable PLL. */ 741 RD4(sc, sc->base_reg, ®); 742 reg |= PLL_BASE_ENABLE; 743 WR4(sc, sc->base_reg, reg); 744 745 /* Enable lock detection. */ 746 RD4(sc, sc->misc_reg, ®); 747 reg |= sc->lock_enable; 748 WR4(sc, sc->misc_reg, reg); 749 750 rv = wait_for_lock(sc); 751 if (rv != 0) { 752 /* Disable PLL */ 753 RD4(sc, sc->base_reg, ®); 754 reg &= ~PLL_BASE_ENABLE; 755 WR4(sc, sc->base_reg, reg); 756 return (rv); 757 } 758 RD4(sc, sc->misc_reg, ®); 759 760 pll_enable(sc); 761 *fout = ((fin / m) * n) / p; 762 return 0; 763 } 764 765 static int 766 plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 767 { 768 uint32_t m, n, p; 769 770 p = 1; 771 m = 5; 772 n = (*fout * p * m + fin / 2)/ fin; 773 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 774 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 775 } 776 777 static int 778 pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 779 { 780 uint32_t m, n, p; 781 782 p = 2; 783 m = 1; 784 n = (*fout * p * m + fin / 2)/ fin; 785 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 786 return (pll_set_std( sc, fin, fout, flags, m, n, p)); 787 } 788 789 /* 790 * PLLD2 is used as source for pixel clock for HDMI. 791 * We must be able to set it frequency very flexibly and 792 * precisely (within 5% tolerance limit allowed by HDMI specs). 793 * 794 * For this reason, it is necessary to search the full state space. 795 * Fortunately, thanks to early cycle terminations, performance 796 * is within acceptable limits. 797 */ 798 #define PLLD2_PFD_MIN 12000000 /* 12 MHz */ 799 #define PLLD2_PFD_MAX 38000000 /* 38 MHz */ 800 #define PLLD2_VCO_MIN 600000000 /* 600 MHz */ 801 #define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */ 802 803 static int 804 plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 805 { 806 uint32_t m, n, p; 807 uint32_t best_m, best_n, best_p; 808 uint64_t vco, pfd; 809 int64_t err, best_err; 810 struct mnp_bits *mnp_bits; 811 struct pdiv_table *tbl; 812 int p_idx, rv; 813 814 mnp_bits = &sc->mnp_bits; 815 tbl = sc->pdiv_table; 816 best_err = INT64_MAX; 817 818 for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) { 819 p = tbl[p_idx].divider; 820 821 /* Check constraints */ 822 vco = *fout * p; 823 if (vco < PLLD2_VCO_MIN) 824 continue; 825 if (vco > PLLD2_VCO_MAX) 826 break; 827 828 for (m = 1; m < (1 << mnp_bits->m_width); m++) { 829 n = (*fout * p * m + fin / 2) / fin; 830 831 /* Check constraints */ 832 if (n == 0) 833 continue; 834 if (n >= (1 << mnp_bits->n_width)) 835 break; 836 vco = (fin * n) / m; 837 if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN) 838 continue; 839 pfd = fin / m; 840 if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN) 841 continue; 842 843 /* Constraints passed, save best result */ 844 err = *fout - vco / p; 845 if (err < 0) 846 err = -err; 847 if (err < best_err) { 848 best_err = err; 849 best_p = p; 850 best_m = m; 851 best_n = n; 852 } 853 if (err == 0) 854 goto done; 855 } 856 } 857 done: 858 /* 859 * HDMI specification allows 5% pixel clock tolerance, 860 * we will by a slightly stricter 861 */ 862 if (best_err > ((*fout * 100) / 4)) 863 return (ERANGE); 864 865 if (flags & CLK_SET_DRYRUN) 866 return (0); 867 rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p); 868 /* XXXX Panic for rv == ERANGE ? */ 869 return (rv); 870 } 871 872 static int 873 pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 874 { 875 uint32_t m, n, p; 876 877 m = 1; 878 p = 1; 879 n = *fout * p * m / fin; 880 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 881 return (pll_set_std(sc, fin, fout, flags, m, n, p)); 882 } 883 884 static int 885 pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags) 886 { 887 uint32_t reg; 888 uint32_t m, n, p; 889 struct mnp_bits *mnp_bits; 890 int rv; 891 892 mnp_bits = &sc->mnp_bits; 893 894 p = 1; 895 m = 1; 896 n = (*fout * p * m + fin / 2)/ fin; 897 dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p); 898 899 if (m >= (1 << mnp_bits->m_width)) 900 return (ERANGE); 901 if (n >= (1 << mnp_bits->n_width)) 902 return (ERANGE); 903 if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width)) 904 return (ERANGE); 905 906 if (flags & CLK_SET_DRYRUN) { 907 if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) && 908 (*fout != (((fin / m) * n) /p))) 909 return (ERANGE); 910 *fout = ((fin / m) * n) /p; 911 return (0); 912 } 913 914 /* PLLX doesn't have bypass, disable it first. */ 915 RD4(sc, sc->base_reg, ®); 916 reg &= ~PLL_BASE_ENABLE; 917 WR4(sc, sc->base_reg, reg); 918 919 /* Set PLL. */ 920 RD4(sc, sc->base_reg, ®); 921 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); 922 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); 923 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, 924 mnp_bits->p_width); 925 WR4(sc, sc->base_reg, reg); 926 RD4(sc, sc->base_reg, ®); 927 DELAY(100); 928 929 /* Enable lock detection. */ 930 RD4(sc, sc->misc_reg, ®); 931 reg |= sc->lock_enable; 932 WR4(sc, sc->misc_reg, reg); 933 934 /* Enable PLL. */ 935 RD4(sc, sc->base_reg, ®); 936 reg |= PLL_BASE_ENABLE; 937 WR4(sc, sc->base_reg, reg); 938 939 rv = wait_for_lock(sc); 940 if (rv != 0) { 941 /* Disable PLL */ 942 RD4(sc, sc->base_reg, ®); 943 reg &= ~PLL_BASE_ENABLE; 944 WR4(sc, sc->base_reg, reg); 945 return (rv); 946 } 947 RD4(sc, sc->misc_reg, ®); 948 949 *fout = ((fin / m) * n) / p; 950 return (0); 951 } 952 953 static int 954 tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout, 955 int flags, int *stop) 956 { 957 *stop = 1; 958 int rv; 959 struct pll_sc *sc; 960 961 sc = clknode_get_softc(clknode); 962 dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__, 963 clknode_get_name(clknode), *fout, fin); 964 switch (sc->type) { 965 case PLL_A: 966 rv = plla_set_freq(sc, fin, fout, flags); 967 break; 968 case PLL_C: 969 rv = pllc_set_freq(sc, fin, fout, flags); 970 break; 971 case PLL_D2: 972 rv = plld2_set_freq(sc, fin, fout, flags); 973 break; 974 975 case PLL_REFE: 976 rv = pllrefe_set_freq(sc, fin, fout, flags); 977 break; 978 979 case PLL_X: 980 rv = pllx_set_freq(sc, fin, fout, flags); 981 break; 982 983 case PLL_U: 984 if (*fout == 480000000) /* PLLU is fixed to 480 MHz */ 985 rv = 0; 986 else 987 rv = ERANGE; 988 break; 989 default: 990 rv = ENXIO; 991 break; 992 } 993 994 return (rv); 995 } 996 997 static int 998 tegra124_pll_init(struct clknode *clk, device_t dev) 999 { 1000 struct pll_sc *sc; 1001 uint32_t reg; 1002 1003 sc = clknode_get_softc(clk); 1004 1005 /* If PLL is enabled, enable lock detect too. */ 1006 RD4(sc, sc->base_reg, ®); 1007 if (reg & PLL_BASE_ENABLE) { 1008 RD4(sc, sc->misc_reg, ®); 1009 reg |= sc->lock_enable; 1010 WR4(sc, sc->misc_reg, reg); 1011 } 1012 if (sc->type == PLL_REFE) { 1013 RD4(sc, sc->misc_reg, ®); 1014 reg &= ~(1 << 29); /* Diasble lock override */ 1015 WR4(sc, sc->misc_reg, reg); 1016 } 1017 1018 clknode_init_parent_idx(clk, 0); 1019 return(0); 1020 } 1021 1022 static int 1023 tegra124_pll_recalc(struct clknode *clk, uint64_t *freq) 1024 { 1025 struct pll_sc *sc; 1026 uint32_t m, n, p, pr; 1027 uint32_t reg, misc_reg; 1028 1029 sc = clknode_get_softc(clk); 1030 1031 RD4(sc, sc->base_reg, ®); 1032 RD4(sc, sc->misc_reg, &misc_reg); 1033 1034 get_divisors(sc, &m, &n, &pr); 1035 if (sc->type != PLL_E) 1036 p = reg_to_pdiv(sc, pr); 1037 else 1038 p = 2 * (pr - 1); 1039 1040 dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): " 1041 "e: %d, r: %d, o: %d - %s\n", __func__, 1042 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, 1043 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, 1044 is_locked(sc) ? "locked" : "unlocked"); 1045 1046 if ((m == 0) || (n == 0) || (p == 0)) { 1047 *freq = 0; 1048 return (EINVAL); 1049 } 1050 *freq = ((*freq / m) * n) / p; 1051 return (0); 1052 } 1053 1054 static int 1055 pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef) 1056 { 1057 struct clknode *clk; 1058 struct pll_sc *sc; 1059 1060 clk = clknode_create(clkdom, &tegra124_pll_class, &clkdef->clkdef); 1061 if (clk == NULL) 1062 return (ENXIO); 1063 1064 sc = clknode_get_softc(clk); 1065 sc->clkdev = clknode_get_device(clk); 1066 sc->type = clkdef->type; 1067 sc->base_reg = clkdef->base_reg; 1068 sc->misc_reg = clkdef->misc_reg; 1069 sc->lock_mask = clkdef->lock_mask; 1070 sc->lock_enable = clkdef->lock_enable; 1071 sc->iddq_reg = clkdef->iddq_reg; 1072 sc->iddq_mask = clkdef->iddq_mask; 1073 sc->flags = clkdef->flags; 1074 sc->pdiv_table = clkdef->pdiv_table; 1075 sc->mnp_bits = clkdef->mnp_bits; 1076 clknode_register(clkdom, clk); 1077 return (0); 1078 } 1079 1080 static void config_utmi_pll(struct tegra124_car_softc *sc) 1081 { 1082 uint32_t reg; 1083 /* 1084 * XXX Simplified UTMIP settings for 12MHz base clock. 1085 */ 1086 #define ENABLE_DELAY_COUNT 0x02 1087 #define STABLE_COUNT 0x2F 1088 #define ACTIVE_DELAY_COUNT 0x04 1089 #define XTAL_FREQ_COUNT 0x76 1090 1091 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); 1092 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1093 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); 1094 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1095 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); 1096 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1097 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1098 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1099 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); 1100 1101 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1102 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1103 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); 1104 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1105 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); 1106 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1107 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1108 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1109 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1110 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1111 1112 /* Prepare UTMIP requencer. */ 1113 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1114 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1115 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1116 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1117 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1118 1119 /* Powerup UTMIP. */ 1120 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); 1121 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1122 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1123 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); 1124 DELAY(10); 1125 1126 /* SW override for UTMIPLL */ 1127 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1128 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1129 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1130 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1131 DELAY(10); 1132 1133 /* HW control of UTMIPLL. */ 1134 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); 1135 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1136 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); 1137 } 1138 1139 void 1140 tegra124_init_plls(struct tegra124_car_softc *sc) 1141 { 1142 int i, rv; 1143 1144 for (i = 0; i < nitems(pll_clks); i++) { 1145 rv = pll_register(sc->clkdom, pll_clks + i); 1146 if (rv != 0) 1147 panic("pll_register failed"); 1148 } 1149 config_utmi_pll(sc); 1150 1151 } 1152