1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/kobj.h> 32 #include <sys/module.h> 33 #include <sys/malloc.h> 34 #include <sys/rman.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 41 #include <dev/clk/clk_div.h> 42 #include <dev/clk/clk_fixed.h> 43 #include <dev/clk/clk_gate.h> 44 #include <dev/clk/clk_mux.h> 45 #include <dev/hwreset/hwreset.h> 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dt-bindings/clock/tegra124-car.h> 51 52 #include "clkdev_if.h" 53 #include "hwreset_if.h" 54 #include "tegra124_car.h" 55 56 static struct ofw_compat_data compat_data[] = { 57 {"nvidia,tegra124-car", 1}, 58 {NULL, 0}, 59 }; 60 61 #define PLIST(x) static const char *x[] 62 63 /* Pure multiplexer. */ 64 #define MUX(_id, cname, plists, o, s, w) \ 65 { \ 66 .clkdef.id = _id, \ 67 .clkdef.name = cname, \ 68 .clkdef.parent_names = plists, \ 69 .clkdef.parent_cnt = nitems(plists), \ 70 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 71 .offset = o, \ 72 .shift = s, \ 73 .width = w, \ 74 } 75 76 /* Fractional divider (7.1). */ 77 #define DIV7_1(_id, cname, plist, o, s) \ 78 { \ 79 .clkdef.id = _id, \ 80 .clkdef.name = cname, \ 81 .clkdef.parent_names = (const char *[]){plist}, \ 82 .clkdef.parent_cnt = 1, \ 83 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 84 .offset = o, \ 85 .i_shift = (s) + 1, \ 86 .i_width = 7, \ 87 .f_shift = s, \ 88 .f_width = 1, \ 89 } 90 91 /* Integer divider. */ 92 #define DIV(_id, cname, plist, o, s, w, f) \ 93 { \ 94 .clkdef.id = _id, \ 95 .clkdef.name = cname, \ 96 .clkdef.parent_names = (const char *[]){plist}, \ 97 .clkdef.parent_cnt = 1, \ 98 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 99 .offset = o, \ 100 .i_shift = s, \ 101 .i_width = w, \ 102 .div_flags = f, \ 103 } 104 105 /* Gate in PLL block. */ 106 #define GATE_PLL(_id, cname, plist, o, s) \ 107 { \ 108 .clkdef.id = _id, \ 109 .clkdef.name = cname, \ 110 .clkdef.parent_names = (const char *[]){plist}, \ 111 .clkdef.parent_cnt = 1, \ 112 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 113 .offset = o, \ 114 .shift = s, \ 115 .mask = 3, \ 116 .on_value = 3, \ 117 .off_value = 0, \ 118 } 119 120 /* Standard gate. */ 121 #define GATE(_id, cname, plist, o, s) \ 122 { \ 123 .clkdef.id = _id, \ 124 .clkdef.name = cname, \ 125 .clkdef.parent_names = (const char *[]){plist}, \ 126 .clkdef.parent_cnt = 1, \ 127 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 128 .offset = o, \ 129 .shift = s, \ 130 .mask = 1, \ 131 .on_value = 1, \ 132 .off_value = 0, \ 133 } 134 135 /* Inverted gate. */ 136 #define GATE_INV(_id, cname, plist, o, s) \ 137 { \ 138 .clkdef.id = _id, \ 139 .clkdef.name = cname, \ 140 .clkdef.parent_names = (const char *[]){plist}, \ 141 .clkdef.parent_cnt = 1, \ 142 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 143 .offset = o, \ 144 .shift = s, \ 145 .mask = 1, \ 146 .on_value = 0, \ 147 .off_value = 1, \ 148 } 149 150 /* Fixed rate clock. */ 151 #define FRATE(_id, cname, _freq) \ 152 { \ 153 .clkdef.id = _id, \ 154 .clkdef.name = cname, \ 155 .clkdef.parent_names = NULL, \ 156 .clkdef.parent_cnt = 0, \ 157 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 158 .freq = _freq, \ 159 } 160 161 /* Fixed rate multipier/divider. */ 162 #define FACT(_id, cname, pname, _mult, _div) \ 163 { \ 164 .clkdef.id = _id, \ 165 .clkdef.name = cname, \ 166 .clkdef.parent_names = (const char *[]){pname}, \ 167 .clkdef.parent_cnt = 1, \ 168 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 169 .mult = _mult, \ 170 .div = _div, \ 171 } 172 173 static uint32_t osc_freqs[16] = { 174 [0] = 13000000, 175 [1] = 16800000, 176 [4] = 19200000, 177 [5] = 38400000, 178 [8] = 12000000, 179 [9] = 48000000, 180 [12] = 260000000, 181 }; 182 183 /* Parent lists. */ 184 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 185 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 186 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"}; 187 PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"}; 188 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"}; 189 PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"}; 190 191 /* Clocks adjusted online. */ 192 static struct clk_fixed_def fixed_clk_m = 193 FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000); 194 static struct clk_fixed_def fixed_osc_div_clk = 195 FACT(0, "osc_div_clk", "clk_m", 1, 1); 196 197 static struct clk_fixed_def tegra124_fixed_clks[] = { 198 /* Core clocks. */ 199 FRATE(0, "clk_s", 32768), 200 FACT(0, "clk_m_div2", "clk_m", 1, 2), 201 FACT(0, "clk_m_div4", "clk_m", 1, 3), 202 FACT(0, "pllU_60", "pllU_out", 1, 8), 203 FACT(0, "pllU_48", "pllU_out", 1, 10), 204 FACT(0, "pllU_12", "pllU_out", 1, 40), 205 FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 206 FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1), 207 FACT(0, "pllX_out0", "pllX_out", 1, 2), 208 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 209 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 210 211 /* Audio clocks. */ 212 FRATE(0, "audio0", 10000000), 213 FRATE(0, "audio1", 10000000), 214 FRATE(0, "audio2", 10000000), 215 FRATE(0, "audio3", 10000000), 216 FRATE(0, "audio4", 10000000), 217 FRATE(0, "ext_vimclk", 10000000), 218 219 /* XUSB */ 220 FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2), 221 222 }; 223 224 static struct clk_mux_def tegra124_mux_clks[] = { 225 /* Core clocks. */ 226 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 227 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 228 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 229 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 230 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 231 232 /* Base peripheral clocks. */ 233 MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1), 234 MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1), 235 236 /* USB. */ 237 MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1), 238 MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1), 239 240 }; 241 242 static struct clk_gate_def tegra124_gate_clks[] = { 243 /* Core clocks. */ 244 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 245 GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0), 246 GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22), 247 GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0), 248 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 249 GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16), 250 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 251 GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 252 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 253 GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0), 254 255 /* Base peripheral clocks. */ 256 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 257 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 258 GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7), 259 GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3), 260 }; 261 262 static struct clk_div_def tegra124_div_clks[] = { 263 /* Core clocks. */ 264 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2), 265 DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8), 266 DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2), 267 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 268 DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24), 269 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 270 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 271 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 272 DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8), 273 274 /* Base peripheral clocks. */ 275 DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0), 276 DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0), 277 }; 278 279 /* Initial setup table. */ 280 static struct tegra124_init_item clk_init_table[] = { 281 /* clock, partent, frequency, enable */ 282 {"uarta", "pllP_out0", 408000000, 0}, 283 {"uartb", "pllP_out0", 408000000, 0}, 284 {"uartc", "pllP_out0", 408000000, 0}, 285 {"uartd", "pllP_out0", 408000000, 0}, 286 {"pllA_out", NULL, 282240000, 1}, 287 {"pllA_out0", NULL, 11289600, 1}, 288 {"extperiph1", "pllA_out0", 0, 1}, 289 {"i2s0", "pllA_out0", 11289600, 0}, 290 {"i2s1", "pllA_out0", 11289600, 0}, 291 {"i2s2", "pllA_out0", 11289600, 0}, 292 {"i2s3", "pllA_out0", 11289600, 0}, 293 {"i2s4", "pllA_out0", 11289600, 0}, 294 {"vde", "pllP_out0", 0, 0}, 295 {"host1x", "pllP_out0", 136000000, 1}, 296 {"sclk", "pllP_out2", 102000000, 1}, 297 {"dvfs_soc", "pllP_out0", 51000000, 1}, 298 {"dvfs_ref", "pllP_out0", 51000000, 1}, 299 {"pllC_out0", NULL, 600000000, 0}, 300 {"pllC_out1", NULL, 100000000, 0}, 301 {"spi4", "pllP_out0", 12000000, 1}, 302 {"tsec", "pllC3_out0", 0, 0}, 303 {"msenc", "pllC3_out0", 0, 0}, 304 {"pllREFE_out", NULL, 672000000, 0}, 305 {"pc_xusb_ss", "pllU_480", 120000000, 0}, 306 {"xusb_ss", "pc_xusb_ss", 120000000, 0}, 307 {"pc_xusb_fs", "pllU_48", 48000000, 0}, 308 {"xusb_hs", "pllU_60", 60000000, 0}, 309 {"pc_xusb_falcon", "pllREFE_out", 224000000, 0}, 310 {"xusb_core_host", "pllREFE_out", 112000000, 0}, 311 {"sata", "pllP_out0", 102000000, 0}, 312 {"sata_oob", "pllP_out0", 204000000, 0}, 313 {"sata_cold", NULL, 0, 1}, 314 {"emc", NULL, 0, 1}, 315 {"mselect", NULL, 0, 1}, 316 {"csite", NULL, 0, 1}, 317 {"tsensor", "clk_m", 400000, 0}, 318 319 /* tegra124 only*/ 320 {"soc_therm", "pllP_out0", 51000000, 0}, 321 {"cclk_g", NULL, 0, 1}, 322 {"hda", "pllP_out0", 102000000, 0}, 323 {"hda2codec_2x", "pllP_out0", 48000000, 0}, 324 }; 325 326 static void 327 init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks) 328 { 329 int i, rv; 330 331 for (i = 0; i < nclks; i++) { 332 rv = clknode_div_register(sc->clkdom, clks + i); 333 if (rv != 0) 334 panic("clk_div_register failed"); 335 } 336 } 337 338 static void 339 init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks) 340 { 341 int i, rv; 342 343 for (i = 0; i < nclks; i++) { 344 rv = clknode_gate_register(sc->clkdom, clks + i); 345 if (rv != 0) 346 panic("clk_gate_register failed"); 347 } 348 } 349 350 static void 351 init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks) 352 { 353 int i, rv; 354 355 for (i = 0; i < nclks; i++) { 356 rv = clknode_mux_register(sc->clkdom, clks + i); 357 if (rv != 0) 358 panic("clk_mux_register failed"); 359 } 360 } 361 362 static void 363 init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks, 364 int nclks) 365 { 366 int i, rv; 367 uint32_t val; 368 int osc_idx; 369 370 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); 371 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; 372 fixed_clk_m.freq = osc_freqs[osc_idx]; 373 if (fixed_clk_m.freq == 0) 374 panic("Undefined input frequency"); 375 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m); 376 if (rv != 0) panic("clk_fixed_register failed"); 377 378 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 379 fixed_osc_div_clk.div = 1 << val; 380 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk); 381 if (rv != 0) panic("clk_fixed_register failed"); 382 383 for (i = 0; i < nclks; i++) { 384 rv = clknode_fixed_register(sc->clkdom, clks + i); 385 if (rv != 0) 386 panic("clk_fixed_register failed"); 387 } 388 } 389 390 static void 391 postinit_clock(struct tegra124_car_softc *sc) 392 { 393 int i; 394 struct tegra124_init_item *tbl; 395 struct clknode *clknode; 396 int rv; 397 398 for (i = 0; i < nitems(clk_init_table); i++) { 399 tbl = &clk_init_table[i]; 400 401 clknode = clknode_find_by_name(tbl->name); 402 if (clknode == NULL) { 403 device_printf(sc->dev, "Cannot find clock %s\n", 404 tbl->name); 405 continue; 406 } 407 if (tbl->parent != NULL) { 408 rv = clknode_set_parent_by_name(clknode, tbl->parent); 409 if (rv != 0) { 410 device_printf(sc->dev, 411 "Cannot set parent for %s (to %s): %d\n", 412 tbl->name, tbl->parent, rv); 413 continue; 414 } 415 } 416 if (tbl->frequency != 0) { 417 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999); 418 if (rv != 0) { 419 device_printf(sc->dev, 420 "Cannot set frequency for %s: %d\n", 421 tbl->name, rv); 422 continue; 423 } 424 } 425 if (tbl->enable!= 0) { 426 rv = clknode_enable(clknode); 427 if (rv != 0) { 428 device_printf(sc->dev, 429 "Cannot enable %s: %d\n", tbl->name, rv); 430 continue; 431 } 432 } 433 } 434 } 435 436 static void 437 register_clocks(device_t dev) 438 { 439 struct tegra124_car_softc *sc; 440 441 sc = device_get_softc(dev); 442 sc->clkdom = clkdom_create(dev); 443 if (sc->clkdom == NULL) 444 panic("clkdom == NULL"); 445 446 tegra124_init_plls(sc); 447 init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks)); 448 init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks)); 449 init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks)); 450 init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks)); 451 tegra124_periph_clock(sc); 452 tegra124_super_mux_clock(sc); 453 clkdom_finit(sc->clkdom); 454 clkdom_xlock(sc->clkdom); 455 postinit_clock(sc); 456 clkdom_unlock(sc->clkdom); 457 if (bootverbose) 458 clkdom_dump(sc->clkdom); 459 } 460 461 static int 462 tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 463 { 464 struct tegra124_car_softc *sc; 465 466 sc = device_get_softc(dev); 467 *val = bus_read_4(sc->mem_res, addr); 468 return (0); 469 } 470 471 static int 472 tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val) 473 { 474 struct tegra124_car_softc *sc; 475 476 sc = device_get_softc(dev); 477 bus_write_4(sc->mem_res, addr, val); 478 return (0); 479 } 480 481 static int 482 tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, 483 uint32_t set_mask) 484 { 485 struct tegra124_car_softc *sc; 486 uint32_t reg; 487 488 sc = device_get_softc(dev); 489 reg = bus_read_4(sc->mem_res, addr); 490 reg &= ~clear_mask; 491 reg |= set_mask; 492 bus_write_4(sc->mem_res, addr, reg); 493 return (0); 494 } 495 496 static void 497 tegra124_car_clkdev_device_lock(device_t dev) 498 { 499 struct tegra124_car_softc *sc; 500 501 sc = device_get_softc(dev); 502 mtx_lock(&sc->mtx); 503 } 504 505 static void 506 tegra124_car_clkdev_device_unlock(device_t dev) 507 { 508 struct tegra124_car_softc *sc; 509 510 sc = device_get_softc(dev); 511 mtx_unlock(&sc->mtx); 512 } 513 514 static int 515 tegra124_car_detach(device_t dev) 516 { 517 518 device_printf(dev, "Error: Clock driver cannot be detached\n"); 519 return (EBUSY); 520 } 521 522 static int 523 tegra124_car_probe(device_t dev) 524 { 525 526 if (!ofw_bus_status_okay(dev)) 527 return (ENXIO); 528 529 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 530 device_set_desc(dev, "Tegra Clock Driver"); 531 return (BUS_PROBE_DEFAULT); 532 } 533 534 return (ENXIO); 535 } 536 537 static int 538 tegra124_car_attach(device_t dev) 539 { 540 struct tegra124_car_softc *sc = device_get_softc(dev); 541 int rid, rv; 542 543 sc->dev = dev; 544 545 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 546 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 547 548 /* Resource setup. */ 549 rid = 0; 550 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 551 RF_ACTIVE); 552 if (!sc->mem_res) { 553 device_printf(dev, "cannot allocate memory resource\n"); 554 rv = ENXIO; 555 goto fail; 556 } 557 558 register_clocks(dev); 559 hwreset_register_ofw_provider(dev); 560 return (0); 561 562 fail: 563 if (sc->mem_res) 564 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 565 566 return (rv); 567 } 568 569 static int 570 tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value) 571 { 572 struct tegra124_car_softc *sc = device_get_softc(dev); 573 574 return (tegra124_hwreset_by_idx(sc, id, value)); 575 } 576 577 static device_method_t tegra124_car_methods[] = { 578 /* Device interface */ 579 DEVMETHOD(device_probe, tegra124_car_probe), 580 DEVMETHOD(device_attach, tegra124_car_attach), 581 DEVMETHOD(device_detach, tegra124_car_detach), 582 583 /* Clkdev interface*/ 584 DEVMETHOD(clkdev_read_4, tegra124_car_clkdev_read_4), 585 DEVMETHOD(clkdev_write_4, tegra124_car_clkdev_write_4), 586 DEVMETHOD(clkdev_modify_4, tegra124_car_clkdev_modify_4), 587 DEVMETHOD(clkdev_device_lock, tegra124_car_clkdev_device_lock), 588 DEVMETHOD(clkdev_device_unlock, tegra124_car_clkdev_device_unlock), 589 590 /* Reset interface */ 591 DEVMETHOD(hwreset_assert, tegra124_car_hwreset_assert), 592 593 DEVMETHOD_END 594 }; 595 596 static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods, 597 sizeof(struct tegra124_car_softc)); 598 EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver, NULL, NULL, 599 BUS_PASS_TIMER); 600