xref: /freebsd/sys/arm/nvidia/tegra124/tegra124_car.c (revision 63a938566d524836885917d95bd491aa4400b181)
1 /*-
2  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/kobj.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
37 #include <sys/rman.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43 
44 #include <dev/extres/clk/clk_div.h>
45 #include <dev/extres/clk/clk_fixed.h>
46 #include <dev/extres/clk/clk_gate.h>
47 #include <dev/extres/clk/clk_mux.h>
48 #include <dev/extres/hwreset/hwreset.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 
53 #include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
54 
55 #include "clkdev_if.h"
56 #include "hwreset_if.h"
57 #include "tegra124_car.h"
58 
59 static struct ofw_compat_data compat_data[] = {
60 	{"nvidia,tegra124-car",	1},
61 	{NULL,		 	0},
62 };
63 
64 #define	PLIST(x) static const char *x[]
65 
66 /* Pure multiplexer. */
67 #define	MUX(_id, cname, plists, o, s, w)				\
68 {									\
69 	.clkdef.id = _id,						\
70 	.clkdef.name = cname,						\
71 	.clkdef.parent_names = plists,					\
72 	.clkdef.parent_cnt = nitems(plists),				\
73 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
74 	.offset = o,							\
75 	.shift  = s,							\
76 	.width = w,							\
77 }
78 
79 /* Fractional divider (7.1). */
80 #define	DIV7_1(_id, cname, plist, o, s)					\
81 {									\
82 	.clkdef.id = _id,						\
83 	.clkdef.name = cname,						\
84 	.clkdef.parent_names = (const char *[]){plist},			\
85 	.clkdef.parent_cnt = 1,						\
86 	.clkdef.flags =  CLK_NODE_STATIC_STRINGS,			\
87 	.offset = o,							\
88 	.i_shift = (s) + 1,						\
89 	.i_width = 7,							\
90 	.f_shift = s,							\
91 	.f_width = 1,							\
92 }
93 
94 /* Integer divider. */
95 #define	DIV(_id, cname, plist, o, s, w, f)				\
96 {									\
97 	.clkdef.id = _id,						\
98 	.clkdef.name = cname,						\
99 	.clkdef.parent_names = (const char *[]){plist},			\
100 	.clkdef.parent_cnt = 1,						\
101 	.clkdef.flags =  CLK_NODE_STATIC_STRINGS,			\
102 	.offset = o,							\
103 	.i_shift = s,							\
104 	.i_width = w,							\
105 	.div_flags = f,							\
106 }
107 
108 /* Gate in PLL block. */
109 #define	GATE_PLL(_id, cname, plist, o, s)				\
110 {									\
111 	.clkdef.id = _id,						\
112 	.clkdef.name = cname,						\
113 	.clkdef.parent_names = (const char *[]){plist},			\
114 	.clkdef.parent_cnt = 1,						\
115 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
116 	.offset = o,							\
117 	.shift = s,							\
118 	.mask = 3,							\
119 	.on_value = 3,							\
120 	.off_value = 0,							\
121 }
122 
123 /* Standard gate. */
124 #define	GATE(_id, cname, plist, o, s)					\
125 {									\
126 	.clkdef.id = _id,						\
127 	.clkdef.name = cname,						\
128 	.clkdef.parent_names = (const char *[]){plist},			\
129 	.clkdef.parent_cnt = 1,						\
130 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
131 	.offset = o,							\
132 	.shift = s,							\
133 	.mask = 1,							\
134 	.on_value = 1,							\
135 	.off_value = 0,							\
136 }
137 
138 /* Inverted gate. */
139 #define	GATE_INV(_id, cname, plist, o, s)				\
140 {									\
141 	.clkdef.id = _id,						\
142 	.clkdef.name = cname,						\
143 	.clkdef.parent_names = (const char *[]){plist},			\
144 	.clkdef.parent_cnt = 1,						\
145 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
146 	.offset = o,							\
147 	.shift = s,							\
148 	.mask = 1,							\
149 	.on_value = 0,							\
150 	.off_value = 1,							\
151 }
152 
153 /* Fixed rate clock. */
154 #define	FRATE(_id, cname, _freq)					\
155 {									\
156 	.clkdef.id = _id,						\
157 	.clkdef.name = cname,						\
158 	.clkdef.parent_names = NULL,					\
159 	.clkdef.parent_cnt = 0,						\
160 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
161 	.freq = _freq,							\
162 }
163 
164 /* Fixed rate multipier/divider. */
165 #define	FACT(_id, cname, pname, _mult, _div)				\
166 {									\
167 	.clkdef.id = _id,						\
168 	.clkdef.name = cname,						\
169 	.clkdef.parent_names = (const char *[]){pname},			\
170 	.clkdef.parent_cnt = 1,						\
171 	.clkdef.flags = CLK_NODE_STATIC_STRINGS,			\
172 	.mult = _mult,							\
173 	.div = _div,							\
174 }
175 
176 static uint32_t osc_freqs[16] = {
177 	 [0] =  13000000,
178 	 [1] =  16800000,
179 	 [4] =  19200000,
180 	 [5] =  38400000,
181 	 [8] =  12000000,
182 	 [9] =  48000000,
183 	[12] = 260000000,
184 };
185 
186 
187 /* Parent lists. */
188 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
189 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
190 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};
191 PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};
192 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};
193 PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};
194 
195 
196 /* Clocks ajusted online. */
197 static struct clk_fixed_def fixed_clk_m =
198 	FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000);
199 static struct clk_fixed_def fixed_osc_div_clk =
200 	FACT(0, "osc_div_clk", "clk_m", 1, 1);
201 
202 static struct clk_fixed_def tegra124_fixed_clks[] = {
203 	/* Core clocks. */
204 	FRATE(0, "clk_s", 32768),
205 	FACT(0, "clk_m_div2", "clk_m", 1, 2),
206 	FACT(0, "clk_m_div4", "clk_m", 1, 3),
207 	FACT(0, "pllU_60", "pllU_out", 1, 8),
208 	FACT(0, "pllU_48", "pllU_out", 1, 10),
209 	FACT(0, "pllU_12", "pllU_out", 1, 40),
210 	FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2),
211 	FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1),
212 	FACT(0, "pllX_out0", "pllX_out", 1, 2),
213 	FACT(0, "pllC_UD", "pllC_out0", 1, 1),
214 	FACT(0, "pllM_UD", "pllM_out0", 1, 1),
215 
216 	/* Audio clocks. */
217 	FRATE(0, "audio0", 10000000),
218 	FRATE(0, "audio1", 10000000),
219 	FRATE(0, "audio2", 10000000),
220 	FRATE(0, "audio3", 10000000),
221 	FRATE(0, "audio4", 10000000),
222 	FRATE(0, "ext_vimclk", 10000000),
223 
224 	/* XUSB */
225 	FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2),
226 
227 };
228 
229 
230 static struct clk_mux_def tegra124_mux_clks[] = {
231 	/* Core clocks. */
232 	MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
233 	MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
234 	MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
235 	MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
236 	MUX(0, "pllE_src",  mux_plle_src, PLLE_AUX, 28, 1),
237 
238 	/* Base peripheral clocks. */
239 	MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
240 	MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
241 
242 	/* USB. */
243 	MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
244 	MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
245 
246 };
247 
248 
249 static struct clk_gate_def tegra124_gate_clks[] = {
250 	/* Core clocks. */
251 	GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
252 	GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0),
253 	GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
254 	GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0),
255 	GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
256 	GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16),
257 	GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
258 	GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
259 	GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
260 	GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0),
261 
262 	/* Base peripheral clocks. */
263 	GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
264 	GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
265 	GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
266 	GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
267 };
268 
269 static struct clk_div_def tegra124_div_clks[] = {
270 	/* Core clocks. */
271 	DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2),
272 	DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8),
273 	DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2),
274 	DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),
275 	DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24),
276 	DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
277 	DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
278 	DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),
279 	DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8),
280 
281 	/* Base peripheral clocks. */
282 	DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
283 	DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),
284 };
285 
286 /* Initial setup table. */
287 static struct  tegra124_init_item clk_init_table[] = {
288 	/* clock, partent, frequency, enable */
289 	{"uarta", "pllP_out0", 408000000, 0},
290 	{"uartb", "pllP_out0", 408000000, 0},
291 	{"uartc", "pllP_out0", 408000000, 0},
292 	{"uartd", "pllP_out0", 408000000, 0},
293 	{"pllA_out", NULL, 282240000, 1},
294 	{"pllA_out0", NULL, 11289600, 1},
295 	{"extperiph1", "pllA_out0", 0, 1},
296 	{"i2s0", "pllA_out0", 11289600, 0},
297 	{"i2s1", "pllA_out0", 11289600, 0},
298 	{"i2s2", "pllA_out0", 11289600, 0},
299 	{"i2s3", "pllA_out0", 11289600, 0},
300 	{"i2s4", "pllA_out0", 11289600, 0},
301 	{"vde", "pllP_out0", 0, 0},
302 	{"host1x", "pllP_out0", 136000000, 1},
303 	{"sclk", "pllP_out2", 102000000, 1},
304 	{"dvfs_soc", "pllP_out0", 51000000, 1},
305 	{"dvfs_ref", "pllP_out0", 51000000, 1},
306 	{"pllC_out0", NULL, 600000000, 0},
307 	{"pllC_out1", NULL, 100000000, 0},
308 	{"spi4", "pllP_out0", 12000000, 1},
309 	{"tsec", "pllC3_out0", 0, 0},
310 	{"msenc", "pllC3_out0", 0, 0},
311 	{"pllREFE_out", NULL, 672000000, 0},
312 	{"pc_xusb_ss", "pllU_480", 120000000, 0},
313 	{"xusb_ss", "pc_xusb_ss", 120000000, 0},
314 	{"pc_xusb_fs", "pllU_48", 48000000, 0},
315 	{"xusb_hs", "pllU_60", 60000000, 0},
316 	{"pc_xusb_falcon", "pllREFE_out", 224000000, 0},
317 	{"xusb_core_host", "pllREFE_out", 112000000, 0},
318 	{"sata", "pllP_out0", 102000000, 0},
319 	{"sata_oob", "pllP_out0", 204000000, 0},
320 	{"sata_cold", NULL, 0, 1},
321 	{"emc", NULL, 0, 1},
322 	{"mselect", NULL, 0, 1},
323 	{"csite", NULL, 0, 1},
324 	{"tsensor", "clk_m", 400000, 0},
325 
326 	/* tegra124 only*/
327 	{"soc_therm", "pllP_out0", 51000000, 0},
328 	{"cclk_g", NULL, 0, 1},
329 	{"hda", "pllP_out0", 102000000, 0},
330 	{"hda2codec_2x", "pllP_out0", 48000000, 0},
331 };
332 
333 static void
334 init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks)
335 {
336 	int i, rv;
337 
338 	for (i = 0; i < nclks; i++) {
339 		rv = clknode_div_register(sc->clkdom, clks + i);
340 		if (rv != 0)
341 			panic("clk_div_register failed");
342 	}
343 }
344 
345 static void
346 init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks)
347 {
348 	int i, rv;
349 
350 
351 	for (i = 0; i < nclks; i++) {
352 		rv = clknode_gate_register(sc->clkdom, clks + i);
353 		if (rv != 0)
354 			panic("clk_gate_register failed");
355 	}
356 }
357 
358 static void
359 init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks)
360 {
361 	int i, rv;
362 
363 
364 	for (i = 0; i < nclks; i++) {
365 		rv = clknode_mux_register(sc->clkdom, clks + i);
366 		if (rv != 0)
367 			panic("clk_mux_register failed");
368 	}
369 }
370 
371 static void
372 init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks,
373     int nclks)
374 {
375 	int i, rv;
376 	uint32_t val;
377 	int osc_idx;
378 
379 	CLKDEV_READ_4(sc->dev, OSC_CTRL, &val);
380 	osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
381 	fixed_clk_m.freq = osc_freqs[osc_idx];
382 	if (fixed_clk_m.freq == 0)
383 		panic("Undefined input frequency");
384 	rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m);
385 	if (rv != 0) panic("clk_fixed_register failed");
386 
387 	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
388 	fixed_osc_div_clk.div = 1 << val;
389 	rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk);
390 	if (rv != 0) panic("clk_fixed_register failed");
391 
392 	for (i = 0; i < nclks; i++) {
393 		rv = clknode_fixed_register(sc->clkdom, clks + i);
394 		if (rv != 0)
395 			panic("clk_fixed_register failed");
396 	}
397 }
398 
399 static void
400 postinit_clock(struct tegra124_car_softc *sc)
401 {
402 	int i;
403 	struct tegra124_init_item *tbl;
404 	struct clknode *clknode;
405 	int rv;
406 
407 	for (i = 0; i < nitems(clk_init_table); i++) {
408 		tbl = &clk_init_table[i];
409 
410 		clknode =  clknode_find_by_name(tbl->name);
411 		if (clknode == NULL) {
412 			device_printf(sc->dev, "Cannot find clock %s\n",
413 			    tbl->name);
414 			continue;
415 		}
416 		if (tbl->parent != NULL) {
417 			rv = clknode_set_parent_by_name(clknode, tbl->parent);
418 			if (rv != 0) {
419 				device_printf(sc->dev,
420 				    "Cannot set parent for %s (to %s): %d\n",
421 				    tbl->name, tbl->parent, rv);
422 				continue;
423 			}
424 		}
425 		if (tbl->frequency != 0) {
426 			rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999);
427 			if (rv != 0) {
428 				device_printf(sc->dev,
429 				    "Cannot set frequency for %s: %d\n",
430 				    tbl->name, rv);
431 				continue;
432 			}
433 		}
434 		if (tbl->enable!= 0) {
435 			rv = clknode_enable(clknode);
436 			if (rv != 0) {
437 				device_printf(sc->dev,
438 				    "Cannot enable %s: %d\n", tbl->name, rv);
439 				continue;
440 			}
441 		}
442 	}
443 }
444 
445 static void
446 register_clocks(device_t dev)
447 {
448 	struct tegra124_car_softc *sc;
449 
450 	sc = device_get_softc(dev);
451 	sc->clkdom = clkdom_create(dev);
452 	if (sc->clkdom == NULL)
453 		panic("clkdom == NULL");
454 
455 	tegra124_init_plls(sc);
456 	init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks));
457 	init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks));
458 	init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks));
459 	init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks));
460 	tegra124_periph_clock(sc);
461 	tegra124_super_mux_clock(sc);
462 	clkdom_finit(sc->clkdom);
463 	clkdom_xlock(sc->clkdom);
464 	postinit_clock(sc);
465 	clkdom_unlock(sc->clkdom);
466 	if (bootverbose)
467 		clkdom_dump(sc->clkdom);
468 }
469 
470 static int
471 tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
472 {
473 	struct tegra124_car_softc *sc;
474 
475 	sc = device_get_softc(dev);
476 	*val = bus_read_4(sc->mem_res, addr);
477 	return (0);
478 }
479 
480 static int
481 tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
482 {
483 	struct tegra124_car_softc *sc;
484 
485 	sc = device_get_softc(dev);
486 	bus_write_4(sc->mem_res, addr, val);
487 	return (0);
488 }
489 
490 static int
491 tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask,
492     uint32_t set_mask)
493 {
494 	struct tegra124_car_softc *sc;
495 	uint32_t reg;
496 
497 	sc = device_get_softc(dev);
498 	reg = bus_read_4(sc->mem_res, addr);
499 	reg &= ~clear_mask;
500 	reg |= set_mask;
501 	bus_write_4(sc->mem_res, addr, reg);
502 	return (0);
503 }
504 
505 static void
506 tegra124_car_clkdev_device_lock(device_t dev)
507 {
508 	struct tegra124_car_softc *sc;
509 
510 	sc = device_get_softc(dev);
511 	mtx_lock(&sc->mtx);
512 }
513 
514 static void
515 tegra124_car_clkdev_device_unlock(device_t dev)
516 {
517 	struct tegra124_car_softc *sc;
518 
519 	sc = device_get_softc(dev);
520 	mtx_unlock(&sc->mtx);
521 }
522 
523 static int
524 tegra124_car_detach(device_t dev)
525 {
526 
527 	device_printf(dev, "Error: Clock driver cannot be detached\n");
528 	return (EBUSY);
529 }
530 
531 static int
532 tegra124_car_probe(device_t dev)
533 {
534 
535 	if (!ofw_bus_status_okay(dev))
536 		return (ENXIO);
537 
538 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
539 		device_set_desc(dev, "Tegra Clock Driver");
540 		return (BUS_PROBE_DEFAULT);
541 	}
542 
543 	return (ENXIO);
544 }
545 
546 static int
547 tegra124_car_attach(device_t dev)
548 {
549 	struct tegra124_car_softc *sc = device_get_softc(dev);
550 	int rid, rv;
551 
552 	sc->dev = dev;
553 
554 	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
555 	sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
556 
557 	/* Resource setup. */
558 	rid = 0;
559 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
560 	    RF_ACTIVE);
561 	if (!sc->mem_res) {
562 		device_printf(dev, "cannot allocate memory resource\n");
563 		rv = ENXIO;
564 		goto fail;
565 	}
566 
567 	register_clocks(dev);
568 	hwreset_register_ofw_provider(dev);
569 	return (0);
570 
571 fail:
572 	if (sc->mem_res)
573 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
574 
575 	return (rv);
576 }
577 
578 static int
579 tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value)
580 {
581 	struct tegra124_car_softc *sc = device_get_softc(dev);
582 
583 	return (tegra124_hwreset_by_idx(sc, id, value));
584 }
585 
586 static device_method_t tegra124_car_methods[] = {
587 	/* Device interface */
588 	DEVMETHOD(device_probe,		tegra124_car_probe),
589 	DEVMETHOD(device_attach,	tegra124_car_attach),
590 	DEVMETHOD(device_detach,	tegra124_car_detach),
591 
592 	/* Clkdev  interface*/
593 	DEVMETHOD(clkdev_read_4,	tegra124_car_clkdev_read_4),
594 	DEVMETHOD(clkdev_write_4,	tegra124_car_clkdev_write_4),
595 	DEVMETHOD(clkdev_modify_4,	tegra124_car_clkdev_modify_4),
596 	DEVMETHOD(clkdev_device_lock,	tegra124_car_clkdev_device_lock),
597 	DEVMETHOD(clkdev_device_unlock,	tegra124_car_clkdev_device_unlock),
598 
599 	/* Reset interface */
600 	DEVMETHOD(hwreset_assert,	tegra124_car_hwreset_assert),
601 
602 	DEVMETHOD_END
603 };
604 
605 static devclass_t tegra124_car_devclass;
606 static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods,
607     sizeof(struct tegra124_car_softc));
608 EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver,
609     tegra124_car_devclass, NULL, NULL, BUS_PASS_TIMER);
610